Lines Matching +full:0 +full:x1000
34 #size-cells = <0>;
36 PowerPC,8560@0 {
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>;
45 clock-frequency = <0>;
52 reg = <0x00000000 0x20000000>;
59 ranges = <0x0 0xff700000 0x00100000>;
60 clock-frequency = <0>;
62 ecm-law@0 {
64 reg = <0x0 0x1000>;
70 reg = <0x1000 0x1000>;
77 reg = <0x2000 0x1000>;
79 interrupts = <0x12 0x2>;
84 reg = <0x20000 0x1000>;
85 cache-line-size = <0x20>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K
88 interrupts = <0x10 0x2>;
93 #size-cells = <0>;
94 cell-index = <0>;
96 reg = <0x3000 0x100>;
97 interrupts = <0x2b 0x2>;
104 #size-cells = <0>;
107 reg = <0x3100 0x100>;
108 interrupts = <0x2b 0x2>;
117 reg = <0x21300 0x4>;
118 ranges = <0x0 0x21100 0x200>;
119 cell-index = <0>;
120 dma-channel@0 {
123 reg = <0x0 0x80>;
124 cell-index = <0>;
131 reg = <0x80 0x80>;
139 reg = <0x100 0x80>;
147 reg = <0x180 0x80>;
157 cell-index = <0>;
161 reg = <0x24000 0x1000>;
162 ranges = <0x0 0x24000 0x1000>;
164 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
171 #size-cells = <0>;
173 reg = <0x520 0x20>;
176 interrupts = <0x6 0x1>;
177 reg = <0x19>;
182 interrupts = <0x7 0x1>;
183 reg = <0x1a>;
188 interrupts = <0x8 0x1>;
189 reg = <0x1b>;
194 interrupts = <0x8 0x1>;
195 reg = <0x1c>;
199 reg = <0x11>;
212 reg = <0x25000 0x1000>;
213 ranges = <0x0 0x25000 0x1000>;
215 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
222 #size-cells = <0>;
224 reg = <0x520 0x20>;
227 reg = <0x11>;
235 #address-cells = <0>;
238 reg = <0x40000 0x40000>;
246 reg = <0x919c0 0x30>;
252 ranges = <0x0 0x80000 0x10000>;
254 data@0 {
256 reg = <0x0 0x4000 0x9000 0x2000>;
264 reg = <0x919f0 0x10 0x915f0 0x10>;
270 #address-cells = <0>;
272 interrupts = <0x2e 0x2>;
274 reg = <0x90c00 0x80>;
282 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
284 fsl,cpm-command = <0x16200300>;
285 interrupts = <0x21 0x8>;
294 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
296 fsl,cpm-command = <0x1a400300>;
297 interrupts = <0x22 0x8>;
305 reg = <0xe0000 0x1000>;
315 reg = <0xff708000 0x1000>;
317 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
320 /* IDSEL 0x02 */
321 0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
322 0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
323 0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
324 0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
327 interrupts = <0x18 0x2>;
328 bus-range = <0x0 0x0>;
329 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
330 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
337 reg = <0xff705000 0x100>; // BRx, ORx, etc.
340 0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
341 0x1 0x0 0xe4000000 0x4000000 // 64MB flash
342 0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
343 0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
344 0x5 0x0 0xfc000000 0x0c00000 // EPLD
345 0x6 0x0 0xe0000000 0x4000000 // 64MB flash
346 0x7 0x0 0x80000000 0x0200000 // ATM1,2
349 epld@5,0 {
353 reg = <0x5 0x0 0xc00000>;
355 0x0 0x0 0x5 0x000000 0x1fff // LED disp.
356 0x1 0x0 0x5 0x100000 0x1fff // switches
357 0x2 0x0 0x5 0x200000 0x1fff // ID reg.
358 0x3 0x0 0x5 0x300000 0x1fff // status reg.
359 0x4 0x0 0x5 0x400000 0x1fff // reset reg.
360 0x5 0x0 0x5 0x500000 0x1fff // Wind port
361 0x7 0x0 0x5 0x700000 0x1fff // UART #1
362 0x8 0x0 0x5 0x800000 0x1fff // UART #2
363 0x9 0x0 0x5 0x900000 0x1fff // RTC
364 0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
367 bidr@2,0 {
369 reg = <0x2 0x0 0x10>;
372 bcsr@3,0 {
374 reg = <0x3 0x0 0x10>;
377 brstcr@4,0 {
379 reg = <0x4 0x0 0x10>;
382 serial0: serial@7,0 {
385 reg = <0x7 0x0 0x100>;
387 interrupts = <0x9 0x2>;
391 serial1: serial@8,0 {
394 reg = <0x8 0x0 0x100>;
396 interrupts = <0xa 0x2>;
400 rtc@9,0 {
402 reg = <0x9 0x0 0x1fff>;