ce5a7e2d | 13-May-2019 |
Nadav Amit <nadav.amit@gmail.com> |
x86: Halt on exit
In some cases, shutdown through the test device and Bochs might fail. Just hang in a loop that executes halt in such cases. Remove the __builtin_unreachable() as it is not needed a
x86: Halt on exit
In some cases, shutdown through the test device and Bochs might fail. Just hang in a loop that executes halt in such cases. Remove the __builtin_unreachable() as it is not needed anymore.
Signed-off-by: Nadav Amit <nadav.amit@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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7fd49c4a | 03-May-2019 |
Nadav Amit <nadav.amit@gmail.com> |
x86: Remove redundant page zeroing
Now that alloc_page() zeros the page, remove the redundant page zeroing.
Suggested-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Nadav Amit <nadav.amit@gma
x86: Remove redundant page zeroing
Now that alloc_page() zeros the page, remove the redundant page zeroing.
Suggested-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Nadav Amit <nadav.amit@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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e0e5509b | 03-May-2019 |
Nadav Amit <nadav.amit@gmail.com> |
x86: Incorporate timestamp in delay(), call it in io_delay()
There is no guarantee that a self-IPI would be delivered immediately. In eventinj, io_delay() is called after self-IPI is generated but d
x86: Incorporate timestamp in delay(), call it in io_delay()
There is no guarantee that a self-IPI would be delivered immediately. In eventinj, io_delay() is called after self-IPI is generated but does nothing.
In general, there is mess in regard to delay() and io_delay(). There are two definitions of delay() and they do not really look on the timestamp counter and instead count invocations of "pause" (or even "nop"), which might be different on different CPUs/setups, for example due to different pause-loop-exiting configurations.
To address these issues change io_delay() to really do a delay, based on timestamp counter, and move common functions into delay.[hc].
Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Nadav Amit <nadav.amit@gmail.com> [Drop the taskswitch2.c io_delay too - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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bdc714e0 | 02-Apr-2019 |
Marc Orr <marcorr@google.com> |
Add leak scenario to virt_x2apic_mode_test
While working on virt_x2apic_mode_test, we noticed that KVM allows for a buggy or malicious L1 to get at L0's x2APIC MSRs via nested. The issue is in KVM's
Add leak scenario to virt_x2apic_mode_test
While working on virt_x2apic_mode_test, we noticed that KVM allows for a buggy or malicious L1 to get at L0's x2APIC MSRs via nested. The issue is in KVM's nested_vmx_prepare_msr_bitmap() function. Specifically, an L1 can execute the following sequence:
1. WRMSR(IA32_SPEC_CTRL, 1), which causes the spec_ctrl variable, in nested_vmx_prepare_msr_bitmap() to become true. 2. Clear "virtualize x2APIC mode" 3. Set "APIC-register virualization"
Then, KVM will copy L1's MSR bitmap for the x2APIC MSR range into L0, and run L2 with "Virtualize x2APIC mode" disabled, which gives L2 unfettered access to L0's x2APIC msrs.
Thus, this patch extends virt_x2apic_mode_test with a test case for this scenario.
Note, this patch was used to discover and fix the issue described in the KVM patch titled "KVM: x86: nVMX: close leak of L0's x2APIC MSRs".
Signed-off-by: Marc Orr <marcorr@google.com> Reviewed-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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2a2546b7 | 02-Apr-2019 |
Marc Orr <marcorr@google.com> |
Test VMX's virtualize x2APIC mode w/ nested
This patch extends x86/vmx_tests.c to test enabling virtualize x2APIC mode for nested VMX. The basic premises of the test is to pass values between L1 and
Test VMX's virtualize x2APIC mode w/ nested
This patch extends x86/vmx_tests.c to test enabling virtualize x2APIC mode for nested VMX. The basic premises of the test is to pass values between L1 and L2 via the virtual APIC page. Emphasis is placed on validating that L2 can never read/write L0's APIC registers, which would be disastrous.
Note, this test was used to detect and fix the issue described in the KVM patch titled "KVM: x86: nVMX: fix x2APIC VTPR read intercept".
Signed-off-by: Marc Orr <marcorr@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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5868743a | 02-Apr-2019 |
Marc Orr <marcorr@google.com> |
apic_reg_virt_test: Make APIC-access addr 4k page
This patch introduces split_large_page(), which is used to force the APIC-access address to be a 4k page. Otherwise, the apic_reg_virt_test fails on
apic_reg_virt_test: Make APIC-access addr 4k page
This patch introduces split_large_page(), which is used to force the APIC-access address to be a 4k page. Otherwise, the apic_reg_virt_test fails on upstream.
Signed-off-by: Marc Orr <marcorr@google.com> Reviewed-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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268752cd | 02-Apr-2019 |
Marc Orr <marcorr@google.com> |
Test nested APIC-register virtualization
This patch adds a test to validate the APIC-register virtualization execution control with nested virtualization. Specific test cases include: APIC-access vi
Test nested APIC-register virtualization
This patch adds a test to validate the APIC-register virtualization execution control with nested virtualization. Specific test cases include: APIC-access virtualization, APIC-access virtualization with Use TPR Shadow, and APIC-register virtualization.
Signed-off-by: Marc Orr <marcorr@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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bfed1760 | 22-Feb-2019 |
Krish Sadhukhan <krish.sadhukhan@oracle.com> |
Check Host Control Registers on vmentry of L2 guests
According to section "Checks on VMX Controls" in Intel SDM vol 3C, the following checks are performed on vmentry of L2 guests:
- The CR0 fie
Check Host Control Registers on vmentry of L2 guests
According to section "Checks on VMX Controls" in Intel SDM vol 3C, the following checks are performed on vmentry of L2 guests:
- The CR0 field must not set any bit to a value not supported in VMX operation. - The CR4 field must not set any bit to a value not supported in VMX operation. - On processors that support Intel 64 architecture, the CR3 field must be such that bits 63:52 and bits in the range 51:32 beyond the processor’s physical-address width must be 0.
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Conflicts: x86/vmx_tests.c
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e8b0bc33 | 21-Nov-2018 |
Jim Mattson <jmattson@google.com> |
x86: nVMX: Basic test of NMI-window exiting
Test various NMI-window exiting scenarios. In the active activity state, test without any blocking, with blocking by MOV-SS, no blocking with event inject
x86: nVMX: Basic test of NMI-window exiting
Test various NMI-window exiting scenarios. In the active activity state, test without any blocking, with blocking by MOV-SS, no blocking with event injection, and with blocking by NMI. In the halted activity state, test without any blocking, with and without event injection.
Signed-off-by: Jim Mattson <jmattson@google.com> Reviewed-by: Peter Shier <pshier@google.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
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ca43ec68 | 14-Sep-2018 |
Jim Mattson <jmattson@google.com> |
x86: nvmx: Check #NM VM-exit reflection
When L1 intercepts #NM exceptions encountered in L2, the #NM exception should always be reflected from L0 to L1.
Signed-off-by: Jim Mattson <jmattson@google.
x86: nvmx: Check #NM VM-exit reflection
When L1 intercepts #NM exceptions encountered in L2, the #NM exception should always be reflected from L0 to L1.
Signed-off-by: Jim Mattson <jmattson@google.com> Reviewed-by: Peter Shier <pshier@google.com> Reviewed-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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06846df5 | 28-Sep-2018 |
Thomas Huth <thuth@redhat.com> |
x86: Add missing prototypes and mark more local functions as static
To be able to compile with -Wmissing-prototypes, we also need prototypes for functions that are called from assembler code. We put
x86: Add missing prototypes and mark more local functions as static
To be able to compile with -Wmissing-prototypes, we also need prototypes for functions that are called from assembler code. We put the prototypes into the .c files and not into header files here, since these functions are not called from other .c files. While we're at it, also mark some more functions as static in these files which are only used locally.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1538123582-17442-3-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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96d79976 | 20-Jul-2018 |
Andre Przywara <andre.przywara@arm.com> |
mark exit() and abort() as non-returning functions
exit() and abort() are functions that never return, and (at least) GCC has an attribute to flag those functions accordingly. This allows the compil
mark exit() and abort() as non-returning functions
exit() and abort() are functions that never return, and (at least) GCC has an attribute to flag those functions accordingly. This allows the compiler to do further optimizations and to omit various warnings about uninitialized variables, for instance. Since the actual "play-dead" function is in (inline) assembly, the compiler does not recognize its fatal nature, so help it with the __builtin_unreachable() hint. Flag the prototypes of our fatal functions accordingly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andrew Jones <drjones@redhat.com>
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0f4f2acb | 21-Jul-2018 |
Eugene Korenevsky <ekorenevsky@gmail.com> |
x86: io: force carriage return on \n put to serial port
When '\n' (line feed) is put to serial port, put '\r' (carriage return) as well. This makes the serial port output to look properly (without s
x86: io: force carriage return on \n put to serial port
When '\n' (line feed) is put to serial port, put '\r' (carriage return) as well. This makes the serial port output to look properly (without stairs) at real hardware. Also the output looks well at QEMU/KVM and BOCHS emulators.
Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com> Message-Id: <20180721185915.GA21451@vnote> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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b3a7cfdc | 21-Jul-2018 |
Eugene Korenevsky <ekorenevsky@gmail.com> |
x86: io: fix 8250 serial controller initialization
These changes make serial controller working at real hardware and BOCHS: - Disable interrupts - Set up LCR, FCR, MCR properly
Signed-off-by: Eugen
x86: io: fix 8250 serial controller initialization
These changes make serial controller working at real hardware and BOCHS: - Disable interrupts - Set up LCR, FCR, MCR properly
Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com> Message-Id: <20180721185657.GA21275@vnote> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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faea4fc6 | 22-Jun-2018 |
Liran Alon <liran.alon@oracle.com> |
x86: nVMX: Enhance basic vmwrite/vmread test
Check that "read-only" fields are writable when the IA32_VMX_MISC MSR reports that software can use VMWRITE to write to any supported field in the VMCS.
x86: nVMX: Enhance basic vmwrite/vmread test
Check that "read-only" fields are writable when the IA32_VMX_MISC MSR reports that software can use VMWRITE to write to any supported field in the VMCS.
Signed-off-by: Jim Mattson <jmattson@google.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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60d8090c | 22-Jun-2018 |
Liran Alon <liran.alon@oracle.com> |
x86: lib: Define const for all ALU flags
Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
e60c87fd | 22-Jun-2018 |
Liran Alon <liran.alon@oracle.com> |
x86: lib: Introduce utils for btr/bts
Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
8d2cdb35 | 26-Jun-2018 |
Marc Orr <marcorr@google.com> |
x86: Add test for nested VM entry prereqs
This patch adds a test for the prereq checks done as a part of a nested VM launch related to event injection.
Signed-off-by: Marc Orr <marcorr@google.com>
x86: Add test for nested VM entry prereqs
This patch adds a test for the prereq checks done as a part of a nested VM launch related to event injection.
Signed-off-by: Marc Orr <marcorr@google.com> Message-Id: <20180626014818.26541-1-marcorr@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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7db17e21 | 27-Jun-2018 |
Thomas Huth <thuth@redhat.com> |
Make remaining x86 code compilable with -Wstrict-prototypes
This way the functions can not be called anymore with arbitrary parameters by accident.
Signed-off-by: Thomas Huth <thuth@redhat.com> Mes
Make remaining x86 code compilable with -Wstrict-prototypes
This way the functions can not be called anymore with arbitrary parameters by accident.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1530086528-21665-4-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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728e71ee | 23-Mar-2018 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: add UMIP test
The UMIP feature can be emulated by KVM, so it's useful to add a test that it works properly.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
e38858bc | 10-May-2018 |
Jim Mattson <jmattson@google.com> |
Enhance test of disabled APIC
The test now checks to see that the memory "behind" the APIC has either bus error semantics (writes ignored, reads return all 1s) or memory semantics, and that this mem
Enhance test of disabled APIC
The test now checks to see that the memory "behind" the APIC has either bus error semantics (writes ignored, reads return all 1s) or memory semantics, and that this memory is exposed when the APIC is either disabled or in x2APIC mode. The test also checks to see that scribbling on the memory "behind" the APIC has no effect on CR8 when MMIO access to the APIC is disabled.
Signed-off-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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2352e986 | 13-Apr-2018 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: move TSC_ADJUST MSR to msr.h
The MSR is defined in two places, and a third is coming. Centralize the definition.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
ebc1b903 | 23-Mar-2018 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: fix compiler and assembly warnings
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
22207960 | 21-Mar-2018 |
Liran Alon <liran.alon@oracle.com> |
x86: lib: Rename set_ioapic_redir() to ioapic_set_redir()
This is consistent with the naming scheme of rest of ioapic utils.
Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Krish Sad
x86: lib: Rename set_ioapic_redir() to ioapic_set_redir()
This is consistent with the naming scheme of rest of ioapic utils.
Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Message-Id: <1521674594-12085-4-git-send-email-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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f66d11ca | 21-Mar-2018 |
Arbel Moshe <arbel.moshe@oracle.com> |
x86: lib: Expose IOAPIC/APIC globals and utils to lib
Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhuk
x86: lib: Expose IOAPIC/APIC globals and utils to lib
Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Message-Id: <1521674594-12085-3-git-send-email-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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