1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 257 ctrl_cpu0 |= CPU_MSR_BITMAP; 258 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 259 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 260 } 261 262 static void *get_msr_bitmap(void) 263 { 264 void *msr_bitmap; 265 266 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 267 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 268 } else { 269 msr_bitmap = alloc_page(); 270 memset(msr_bitmap, 0xff, PAGE_SIZE); 271 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 272 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 273 } 274 275 return msr_bitmap; 276 } 277 278 static void disable_intercept_for_x2apic_msrs(void) 279 { 280 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 281 u32 msr; 282 283 for (msr = APIC_BASE_MSR; 284 msr < (APIC_BASE_MSR+0xff); 285 msr += BITS_PER_LONG) { 286 unsigned int word = msr / BITS_PER_LONG; 287 288 msr_bitmap[word] = 0; 289 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 290 } 291 } 292 293 static int test_ctrl_pat_init(struct vmcs *vmcs) 294 { 295 u64 ctrl_ent; 296 u64 ctrl_exi; 297 298 msr_bmp_init(); 299 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 300 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 301 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 302 printf("\tSave/load PAT is not supported\n"); 303 return 1; 304 } 305 306 ctrl_ent = vmcs_read(ENT_CONTROLS); 307 ctrl_exi = vmcs_read(EXI_CONTROLS); 308 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 309 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 310 vmcs_write(ENT_CONTROLS, ctrl_ent); 311 vmcs_write(EXI_CONTROLS, ctrl_exi); 312 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 313 vmcs_write(GUEST_PAT, 0x0); 314 vmcs_write(HOST_PAT, ia32_pat); 315 return VMX_TEST_START; 316 } 317 318 static void test_ctrl_pat_main(void) 319 { 320 u64 guest_ia32_pat; 321 322 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 323 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 324 printf("\tENT_LOAD_PAT is not supported.\n"); 325 else { 326 if (guest_ia32_pat != 0) { 327 report("Entry load PAT", 0); 328 return; 329 } 330 } 331 wrmsr(MSR_IA32_CR_PAT, 0x6); 332 vmcall(); 333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 334 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 335 report("Entry load PAT", guest_ia32_pat == ia32_pat); 336 } 337 338 static int test_ctrl_pat_exit_handler(void) 339 { 340 u64 guest_rip; 341 ulong reason; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 reason = vmcs_read(EXI_REASON) & 0xff; 346 switch (reason) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report("Exit save PAT", guest_pat == 0x6); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report("Entry load EFER", 0); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report("Entry load EFER", guest_ia32_efer == ia32_efer); 403 } 404 405 static int test_ctrl_efer_exit_handler(void) 406 { 407 u64 guest_rip; 408 ulong reason; 409 u64 guest_efer; 410 411 guest_rip = vmcs_read(GUEST_RIP); 412 reason = vmcs_read(EXI_REASON) & 0xff; 413 switch (reason) { 414 case VMX_VMCALL: 415 guest_efer = vmcs_read(GUEST_EFER); 416 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 417 printf("\tEXI_SAVE_EFER is not supported\n"); 418 vmcs_write(GUEST_EFER, ia32_efer); 419 } else { 420 report("Exit save EFER", guest_efer == ia32_efer); 421 } 422 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 423 printf("\tEXI_LOAD_EFER is not supported\n"); 424 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 425 } else { 426 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 427 } 428 vmcs_write(GUEST_PAT, ia32_efer); 429 vmcs_write(GUEST_RIP, guest_rip + 3); 430 return VMX_TEST_RESUME; 431 default: 432 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 433 break; 434 } 435 return VMX_TEST_VMEXIT; 436 } 437 438 u32 guest_cr0, guest_cr4; 439 440 static void cr_shadowing_main(void) 441 { 442 u32 cr0, cr4, tmp; 443 444 // Test read through 445 vmx_set_test_stage(0); 446 guest_cr0 = read_cr0(); 447 if (vmx_get_test_stage() == 1) 448 report("Read through CR0", 0); 449 else 450 vmcall(); 451 vmx_set_test_stage(1); 452 guest_cr4 = read_cr4(); 453 if (vmx_get_test_stage() == 2) 454 report("Read through CR4", 0); 455 else 456 vmcall(); 457 // Test write through 458 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 459 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 460 vmx_set_test_stage(2); 461 write_cr0(guest_cr0); 462 if (vmx_get_test_stage() == 3) 463 report("Write throuth CR0", 0); 464 else 465 vmcall(); 466 vmx_set_test_stage(3); 467 write_cr4(guest_cr4); 468 if (vmx_get_test_stage() == 4) 469 report("Write through CR4", 0); 470 else 471 vmcall(); 472 // Test read shadow 473 vmx_set_test_stage(4); 474 vmcall(); 475 cr0 = read_cr0(); 476 if (vmx_get_test_stage() != 5) 477 report("Read shadowing CR0", cr0 == guest_cr0); 478 vmx_set_test_stage(5); 479 cr4 = read_cr4(); 480 if (vmx_get_test_stage() != 6) 481 report("Read shadowing CR4", cr4 == guest_cr4); 482 // Test write shadow (same value with shadow) 483 vmx_set_test_stage(6); 484 write_cr0(guest_cr0); 485 if (vmx_get_test_stage() == 7) 486 report("Write shadowing CR0 (same value with shadow)", 0); 487 else 488 vmcall(); 489 vmx_set_test_stage(7); 490 write_cr4(guest_cr4); 491 if (vmx_get_test_stage() == 8) 492 report("Write shadowing CR4 (same value with shadow)", 0); 493 else 494 vmcall(); 495 // Test write shadow (different value) 496 vmx_set_test_stage(8); 497 tmp = guest_cr0 ^ X86_CR0_TS; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 510 vmx_set_test_stage(10); 511 tmp = guest_cr4 ^ X86_CR4_TSD; 512 asm volatile("mov %0, %%rsi\n\t" 513 "mov %%rsi, %%cr4\n\t" 514 ::"m"(tmp) 515 :"rsi", "memory", "cc"); 516 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 517 vmx_set_test_stage(11); 518 tmp = guest_cr4 ^ X86_CR4_DE; 519 asm volatile("mov %0, %%rsi\n\t" 520 "mov %%rsi, %%cr4\n\t" 521 ::"m"(tmp) 522 :"rsi", "memory", "cc"); 523 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 524 } 525 526 static int cr_shadowing_exit_handler(void) 527 { 528 u64 guest_rip; 529 ulong reason; 530 u32 insn_len; 531 u32 exit_qual; 532 533 guest_rip = vmcs_read(GUEST_RIP); 534 reason = vmcs_read(EXI_REASON) & 0xff; 535 insn_len = vmcs_read(EXI_INST_LEN); 536 exit_qual = vmcs_read(EXI_QUALIFICATION); 537 switch (reason) { 538 case VMX_VMCALL: 539 switch (vmx_get_test_stage()) { 540 case 0: 541 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 542 break; 543 case 1: 544 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 545 break; 546 case 2: 547 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 548 break; 549 case 3: 550 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 551 break; 552 case 4: 553 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 554 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 556 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 557 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 558 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 559 break; 560 case 6: 561 report("Write shadowing CR0 (same value)", 562 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 563 break; 564 case 7: 565 report("Write shadowing CR4 (same value)", 566 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 567 break; 568 default: 569 // Should not reach here 570 report("unexpected stage, %d", false, 571 vmx_get_test_stage()); 572 print_vmexit_info(); 573 return VMX_TEST_VMEXIT; 574 } 575 vmcs_write(GUEST_RIP, guest_rip + insn_len); 576 return VMX_TEST_RESUME; 577 case VMX_CR: 578 switch (vmx_get_test_stage()) { 579 case 4: 580 report("Read shadowing CR0", 0); 581 vmx_inc_test_stage(); 582 break; 583 case 5: 584 report("Read shadowing CR4", 0); 585 vmx_inc_test_stage(); 586 break; 587 case 6: 588 report("Write shadowing CR0 (same value)", 0); 589 vmx_inc_test_stage(); 590 break; 591 case 7: 592 report("Write shadowing CR4 (same value)", 0); 593 vmx_inc_test_stage(); 594 break; 595 case 8: 596 case 9: 597 // 0x600 encodes "mov %esi, %cr0" 598 if (exit_qual == 0x600) 599 vmx_inc_test_stage(); 600 break; 601 case 10: 602 case 11: 603 // 0x604 encodes "mov %esi, %cr4" 604 if (exit_qual == 0x604) 605 vmx_inc_test_stage(); 606 break; 607 default: 608 // Should not reach here 609 report("unexpected stage, %d", false, 610 vmx_get_test_stage()); 611 print_vmexit_info(); 612 return VMX_TEST_VMEXIT; 613 } 614 vmcs_write(GUEST_RIP, guest_rip + insn_len); 615 return VMX_TEST_RESUME; 616 default: 617 report("Unknown exit reason, %ld", false, reason); 618 print_vmexit_info(); 619 } 620 return VMX_TEST_VMEXIT; 621 } 622 623 static int iobmp_init(struct vmcs *vmcs) 624 { 625 u32 ctrl_cpu0; 626 627 io_bitmap_a = alloc_page(); 628 io_bitmap_b = alloc_page(); 629 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 630 ctrl_cpu0 |= CPU_IO_BITMAP; 631 ctrl_cpu0 &= (~CPU_IO); 632 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 633 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 634 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 635 return VMX_TEST_START; 636 } 637 638 static void iobmp_main(void) 639 { 640 // stage 0, test IO pass 641 vmx_set_test_stage(0); 642 inb(0x5000); 643 outb(0x0, 0x5000); 644 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 645 // test IO width, in/out 646 ((u8 *)io_bitmap_a)[0] = 0xFF; 647 vmx_set_test_stage(2); 648 inb(0x0); 649 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 650 vmx_set_test_stage(3); 651 outw(0x0, 0x0); 652 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 653 vmx_set_test_stage(4); 654 inl(0x0); 655 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 656 // test low/high IO port 657 vmx_set_test_stage(5); 658 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 659 inb(0x5000); 660 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 661 vmx_set_test_stage(6); 662 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 663 inb(0x9000); 664 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 665 // test partial pass 666 vmx_set_test_stage(7); 667 inl(0x4FFF); 668 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 669 // test overrun 670 vmx_set_test_stage(8); 671 memset(io_bitmap_a, 0x0, PAGE_SIZE); 672 memset(io_bitmap_b, 0x0, PAGE_SIZE); 673 inl(0xFFFF); 674 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 675 vmx_set_test_stage(9); 676 vmcall(); 677 outb(0x0, 0x0); 678 report("I/O bitmap - ignore unconditional exiting", 679 vmx_get_test_stage() == 9); 680 vmx_set_test_stage(10); 681 vmcall(); 682 outb(0x0, 0x0); 683 report("I/O bitmap - unconditional exiting", 684 vmx_get_test_stage() == 11); 685 } 686 687 static int iobmp_exit_handler(void) 688 { 689 u64 guest_rip; 690 ulong reason, exit_qual; 691 u32 insn_len, ctrl_cpu0; 692 693 guest_rip = vmcs_read(GUEST_RIP); 694 reason = vmcs_read(EXI_REASON) & 0xff; 695 exit_qual = vmcs_read(EXI_QUALIFICATION); 696 insn_len = vmcs_read(EXI_INST_LEN); 697 switch (reason) { 698 case VMX_IO: 699 switch (vmx_get_test_stage()) { 700 case 0: 701 case 1: 702 vmx_inc_test_stage(); 703 break; 704 case 2: 705 report("I/O bitmap - I/O width, byte", 706 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 707 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 708 vmx_inc_test_stage(); 709 break; 710 case 3: 711 report("I/O bitmap - I/O width, word", 712 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 713 report("I/O bitmap - I/O direction, out", 714 !(exit_qual & VMX_IO_IN)); 715 vmx_inc_test_stage(); 716 break; 717 case 4: 718 report("I/O bitmap - I/O width, long", 719 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 720 vmx_inc_test_stage(); 721 break; 722 case 5: 723 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 724 vmx_inc_test_stage(); 725 break; 726 case 6: 727 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 728 vmx_inc_test_stage(); 729 break; 730 case 7: 731 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 732 vmx_inc_test_stage(); 733 break; 734 case 8: 735 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 736 vmx_inc_test_stage(); 737 break; 738 case 9: 739 case 10: 740 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 741 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 742 vmx_inc_test_stage(); 743 break; 744 default: 745 // Should not reach here 746 report("unexpected stage, %d", false, 747 vmx_get_test_stage()); 748 print_vmexit_info(); 749 return VMX_TEST_VMEXIT; 750 } 751 vmcs_write(GUEST_RIP, guest_rip + insn_len); 752 return VMX_TEST_RESUME; 753 case VMX_VMCALL: 754 switch (vmx_get_test_stage()) { 755 case 9: 756 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 757 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 758 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 759 break; 760 case 10: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 default: 766 // Should not reach here 767 report("unexpected stage, %d", false, 768 vmx_get_test_stage()); 769 print_vmexit_info(); 770 return VMX_TEST_VMEXIT; 771 } 772 vmcs_write(GUEST_RIP, guest_rip + insn_len); 773 return VMX_TEST_RESUME; 774 default: 775 printf("guest_rip = %#lx\n", guest_rip); 776 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 777 break; 778 } 779 return VMX_TEST_VMEXIT; 780 } 781 782 #define INSN_CPU0 0 783 #define INSN_CPU1 1 784 #define INSN_ALWAYS_TRAP 2 785 786 #define FIELD_EXIT_QUAL (1 << 0) 787 #define FIELD_INSN_INFO (1 << 1) 788 789 asm( 790 "insn_hlt: hlt;ret\n\t" 791 "insn_invlpg: invlpg 0x12345678;ret\n\t" 792 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 793 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 794 "insn_rdtsc: rdtsc;ret\n\t" 795 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 796 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 797 #ifdef __x86_64__ 798 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 799 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 800 #endif 801 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 802 "insn_pause: pause;ret\n\t" 803 "insn_wbinvd: wbinvd;ret\n\t" 804 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 805 "insn_invd: invd;ret\n\t" 806 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 807 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 808 "insn_sidt: sidt idt_descr;ret\n\t" 809 "insn_lidt: lidt idt_descr;ret\n\t" 810 "insn_sldt: sldt %ax;ret\n\t" 811 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 812 "insn_str: str %ax;ret\n\t" 813 "insn_rdrand: rdrand %rax;ret\n\t" 814 "insn_rdseed: rdseed %rax;ret\n\t" 815 ); 816 extern void insn_hlt(void); 817 extern void insn_invlpg(void); 818 extern void insn_mwait(void); 819 extern void insn_rdpmc(void); 820 extern void insn_rdtsc(void); 821 extern void insn_cr3_load(void); 822 extern void insn_cr3_store(void); 823 #ifdef __x86_64__ 824 extern void insn_cr8_load(void); 825 extern void insn_cr8_store(void); 826 #endif 827 extern void insn_monitor(void); 828 extern void insn_pause(void); 829 extern void insn_wbinvd(void); 830 extern void insn_sgdt(void); 831 extern void insn_lgdt(void); 832 extern void insn_sidt(void); 833 extern void insn_lidt(void); 834 extern void insn_sldt(void); 835 extern void insn_lldt(void); 836 extern void insn_str(void); 837 extern void insn_cpuid(void); 838 extern void insn_invd(void); 839 extern void insn_rdrand(void); 840 extern void insn_rdseed(void); 841 842 u32 cur_insn; 843 u64 cr3; 844 845 struct insn_table { 846 const char *name; 847 u32 flag; 848 void (*insn_func)(void); 849 u32 type; 850 u32 reason; 851 ulong exit_qual; 852 u32 insn_info; 853 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 854 // which field need to be tested, reason is always tested 855 u32 test_field; 856 }; 857 858 /* 859 * Add more test cases of instruction intercept here. Elements in this 860 * table is: 861 * name/control flag/insn function/type/exit reason/exit qulification/ 862 * instruction info/field to test 863 * The last field defines which fields (exit_qual and insn_info) need to be 864 * tested in exit handler. If set to 0, only "reason" is checked. 865 */ 866 static struct insn_table insn_table[] = { 867 // Flags for Primary Processor-Based VM-Execution Controls 868 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 869 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 870 0x12345678, 0, FIELD_EXIT_QUAL}, 871 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 872 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 873 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 874 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 875 FIELD_EXIT_QUAL}, 876 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 877 FIELD_EXIT_QUAL}, 878 #ifdef __x86_64__ 879 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 880 FIELD_EXIT_QUAL}, 881 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 882 FIELD_EXIT_QUAL}, 883 #endif 884 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 885 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 886 // Flags for Secondary Processor-Based VM-Execution Controls 887 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 888 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 889 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 890 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 893 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 894 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 895 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 896 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 897 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 898 // Instructions always trap 899 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 900 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 901 // Instructions never trap 902 {NULL}, 903 }; 904 905 static int insn_intercept_init(struct vmcs *vmcs) 906 { 907 u32 ctrl_cpu; 908 909 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 910 ctrl_cpu &= ctrl_cpu_rev[0].clr; 911 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 912 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 913 cr3 = read_cr3(); 914 return VMX_TEST_START; 915 } 916 917 static void insn_intercept_main(void) 918 { 919 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 920 vmx_set_test_stage(cur_insn * 2); 921 if ((insn_table[cur_insn].type == INSN_CPU0 && 922 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 923 (insn_table[cur_insn].type == INSN_CPU1 && 924 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 925 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 926 insn_table[cur_insn].type - INSN_CPU0, 927 insn_table[cur_insn].name); 928 continue; 929 } 930 931 if ((insn_table[cur_insn].type == INSN_CPU0 && 932 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 933 (insn_table[cur_insn].type == INSN_CPU1 && 934 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 935 /* skip hlt, it stalls the guest and is tested below */ 936 if (insn_table[cur_insn].insn_func != insn_hlt) 937 insn_table[cur_insn].insn_func(); 938 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 939 insn_table[cur_insn].name); 940 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 941 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 942 insn_table[cur_insn].type - INSN_CPU0, 943 insn_table[cur_insn].name); 944 945 vmcall(); 946 947 insn_table[cur_insn].insn_func(); 948 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 949 insn_table[cur_insn].name); 950 951 vmx_set_test_stage(cur_insn * 2 + 1); 952 vmcall(); 953 } 954 } 955 956 static int insn_intercept_exit_handler(void) 957 { 958 u64 guest_rip; 959 u32 reason; 960 ulong exit_qual; 961 u32 insn_len; 962 u32 insn_info; 963 bool pass; 964 965 guest_rip = vmcs_read(GUEST_RIP); 966 reason = vmcs_read(EXI_REASON) & 0xff; 967 exit_qual = vmcs_read(EXI_QUALIFICATION); 968 insn_len = vmcs_read(EXI_INST_LEN); 969 insn_info = vmcs_read(EXI_INST_INFO); 970 971 if (reason == VMX_VMCALL) { 972 u32 val = 0; 973 974 if (insn_table[cur_insn].type == INSN_CPU0) 975 val = vmcs_read(CPU_EXEC_CTRL0); 976 else if (insn_table[cur_insn].type == INSN_CPU1) 977 val = vmcs_read(CPU_EXEC_CTRL1); 978 979 if (vmx_get_test_stage() & 1) 980 val &= ~insn_table[cur_insn].flag; 981 else 982 val |= insn_table[cur_insn].flag; 983 984 if (insn_table[cur_insn].type == INSN_CPU0) 985 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 986 else if (insn_table[cur_insn].type == INSN_CPU1) 987 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 988 } else { 989 pass = (cur_insn * 2 == vmx_get_test_stage()) && 990 insn_table[cur_insn].reason == reason; 991 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 992 insn_table[cur_insn].exit_qual != exit_qual) 993 pass = false; 994 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 995 insn_table[cur_insn].insn_info != insn_info) 996 pass = false; 997 if (pass) 998 vmx_inc_test_stage(); 999 } 1000 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1001 return VMX_TEST_RESUME; 1002 } 1003 1004 /** 1005 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1006 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1007 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1008 * 1009 * Returns 0 on success, 1 on failure. 1010 * 1011 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1012 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1013 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1014 */ 1015 static int __setup_ept(u64 hpa, bool enable_ad) 1016 { 1017 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1018 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1019 printf("\tEPT is not supported"); 1020 return 1; 1021 } 1022 if (!(ept_vpid.val & EPT_CAP_WB)) { 1023 printf("WB memtype for EPT walks not supported\n"); 1024 return 1; 1025 } 1026 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1027 printf("\tPWL4 is not supported\n"); 1028 return 1; 1029 } 1030 1031 eptp = EPT_MEM_TYPE_WB; 1032 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1033 eptp |= hpa; 1034 if (enable_ad) 1035 eptp |= EPTP_AD_FLAG; 1036 1037 vmcs_write(EPTP, eptp); 1038 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1039 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1040 1041 return 0; 1042 } 1043 1044 /** 1045 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1046 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1047 * 1048 * Returns 0 on success, 1 on failure. 1049 * 1050 * This is the "real" function for setting up EPT tables, i.e. use this for 1051 * tests that need to run code in the guest with EPT enabled. 1052 */ 1053 static int setup_ept(bool enable_ad) 1054 { 1055 unsigned long end_of_memory; 1056 1057 pml4 = alloc_page(); 1058 1059 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1060 return 1; 1061 1062 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1063 if (end_of_memory < (1ul << 32)) 1064 end_of_memory = (1ul << 32); 1065 /* Cannot use large EPT pages if we need to track EPT 1066 * accessed/dirty bits at 4K granularity. 1067 */ 1068 setup_ept_range(pml4, 0, end_of_memory, 0, 1069 !enable_ad && ept_2m_supported(), 1070 EPT_WA | EPT_RA | EPT_EA); 1071 return 0; 1072 } 1073 1074 /** 1075 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1076 * 1077 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1078 * for use by tests that need EPT enabled to verify dependent VMCS controls 1079 * but never expect to fully enter the guest, i.e. don't need setup the actual 1080 * EPT tables. 1081 */ 1082 static void setup_dummy_ept(void) 1083 { 1084 if (__setup_ept(0, false)) 1085 report_abort("EPT setup unexpectedly failed"); 1086 } 1087 1088 static int enable_unrestricted_guest(void) 1089 { 1090 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1091 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1092 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1093 return 1; 1094 1095 setup_dummy_ept(); 1096 1097 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1098 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1099 1100 return 0; 1101 } 1102 1103 static void ept_enable_ad_bits(void) 1104 { 1105 eptp |= EPTP_AD_FLAG; 1106 vmcs_write(EPTP, eptp); 1107 } 1108 1109 static void ept_disable_ad_bits(void) 1110 { 1111 eptp &= ~EPTP_AD_FLAG; 1112 vmcs_write(EPTP, eptp); 1113 } 1114 1115 static void ept_enable_ad_bits_or_skip_test(void) 1116 { 1117 if (!ept_ad_bits_supported()) 1118 test_skip("EPT AD bits not supported."); 1119 ept_enable_ad_bits(); 1120 } 1121 1122 static int apic_version; 1123 1124 static int ept_init_common(bool have_ad) 1125 { 1126 int ret; 1127 struct pci_dev pcidev; 1128 1129 if (setup_ept(have_ad)) 1130 return VMX_TEST_EXIT; 1131 data_page1 = alloc_page(); 1132 data_page2 = alloc_page(); 1133 *((u32 *)data_page1) = MAGIC_VAL_1; 1134 *((u32 *)data_page2) = MAGIC_VAL_2; 1135 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1136 EPT_RA | EPT_WA | EPT_EA); 1137 1138 apic_version = apic_read(APIC_LVR); 1139 1140 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1141 if (ret != PCIDEVADDR_INVALID) { 1142 pci_dev_init(&pcidev, ret); 1143 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1144 } 1145 1146 return VMX_TEST_START; 1147 } 1148 1149 static int ept_init(struct vmcs *vmcs) 1150 { 1151 return ept_init_common(false); 1152 } 1153 1154 static void ept_common(void) 1155 { 1156 vmx_set_test_stage(0); 1157 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1158 *((u32 *)data_page1) != MAGIC_VAL_1) 1159 report("EPT basic framework - read", 0); 1160 else { 1161 *((u32 *)data_page2) = MAGIC_VAL_3; 1162 vmcall(); 1163 if (vmx_get_test_stage() == 1) { 1164 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1165 *((u32 *)data_page2) == MAGIC_VAL_2) 1166 report("EPT basic framework", 1); 1167 else 1168 report("EPT basic framework - remap", 1); 1169 } 1170 } 1171 // Test EPT Misconfigurations 1172 vmx_set_test_stage(1); 1173 vmcall(); 1174 *((u32 *)data_page1) = MAGIC_VAL_1; 1175 if (vmx_get_test_stage() != 2) { 1176 report("EPT misconfigurations", 0); 1177 goto t1; 1178 } 1179 vmx_set_test_stage(2); 1180 vmcall(); 1181 *((u32 *)data_page1) = MAGIC_VAL_1; 1182 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1183 t1: 1184 // Test EPT violation 1185 vmx_set_test_stage(3); 1186 vmcall(); 1187 *((u32 *)data_page1) = MAGIC_VAL_1; 1188 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1189 // Violation caused by EPT paging structure 1190 vmx_set_test_stage(4); 1191 vmcall(); 1192 *((u32 *)data_page1) = MAGIC_VAL_2; 1193 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1194 1195 // MMIO Read/Write 1196 vmx_set_test_stage(5); 1197 vmcall(); 1198 1199 *(u32 volatile *)pci_physaddr; 1200 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1201 1202 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1203 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1204 } 1205 1206 static void ept_main(void) 1207 { 1208 ept_common(); 1209 1210 // Test EPT access to L1 MMIO 1211 vmx_set_test_stage(7); 1212 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1213 1214 // Test invalid operand for INVEPT 1215 vmcall(); 1216 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1217 } 1218 1219 static bool invept_test(int type, u64 eptp) 1220 { 1221 bool ret, supported; 1222 1223 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1224 ret = invept(type, eptp); 1225 1226 if (ret == !supported) 1227 return false; 1228 1229 if (!supported) 1230 printf("WARNING: unsupported invept passed!\n"); 1231 else 1232 printf("WARNING: invept failed!\n"); 1233 1234 return true; 1235 } 1236 1237 static int pml_exit_handler(void) 1238 { 1239 u16 index, count; 1240 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1241 u64 *pmlbuf = pml_log; 1242 u64 guest_rip = vmcs_read(GUEST_RIP);; 1243 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1244 u32 insn_len = vmcs_read(EXI_INST_LEN); 1245 1246 switch (reason) { 1247 case VMX_VMCALL: 1248 switch (vmx_get_test_stage()) { 1249 case 0: 1250 index = vmcs_read(GUEST_PML_INDEX); 1251 for (count = index + 1; count < PML_INDEX; count++) { 1252 if (pmlbuf[count] == (u64)data_page2) { 1253 vmx_inc_test_stage(); 1254 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1255 break; 1256 } 1257 } 1258 break; 1259 case 1: 1260 index = vmcs_read(GUEST_PML_INDEX); 1261 /* Keep clearing the dirty bit till a overflow */ 1262 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1263 break; 1264 default: 1265 report("unexpected stage, %d.", false, 1266 vmx_get_test_stage()); 1267 print_vmexit_info(); 1268 return VMX_TEST_VMEXIT; 1269 } 1270 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1271 return VMX_TEST_RESUME; 1272 case VMX_PML_FULL: 1273 vmx_inc_test_stage(); 1274 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1275 return VMX_TEST_RESUME; 1276 default: 1277 report("Unknown exit reason, %ld", false, reason); 1278 print_vmexit_info(); 1279 } 1280 return VMX_TEST_VMEXIT; 1281 } 1282 1283 static int ept_exit_handler_common(bool have_ad) 1284 { 1285 u64 guest_rip; 1286 u64 guest_cr3; 1287 ulong reason; 1288 u32 insn_len; 1289 u32 exit_qual; 1290 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1291 1292 guest_rip = vmcs_read(GUEST_RIP); 1293 guest_cr3 = vmcs_read(GUEST_CR3); 1294 reason = vmcs_read(EXI_REASON) & 0xff; 1295 insn_len = vmcs_read(EXI_INST_LEN); 1296 exit_qual = vmcs_read(EXI_QUALIFICATION); 1297 switch (reason) { 1298 case VMX_VMCALL: 1299 switch (vmx_get_test_stage()) { 1300 case 0: 1301 check_ept_ad(pml4, guest_cr3, 1302 (unsigned long)data_page1, 1303 have_ad ? EPT_ACCESS_FLAG : 0, 1304 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1305 check_ept_ad(pml4, guest_cr3, 1306 (unsigned long)data_page2, 1307 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1308 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1309 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1310 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1311 if (have_ad) 1312 ept_sync(INVEPT_SINGLE, eptp);; 1313 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1314 *((u32 *)data_page2) == MAGIC_VAL_2) { 1315 vmx_inc_test_stage(); 1316 install_ept(pml4, (unsigned long)data_page2, 1317 (unsigned long)data_page2, 1318 EPT_RA | EPT_WA | EPT_EA); 1319 } else 1320 report("EPT basic framework - write", 0); 1321 break; 1322 case 1: 1323 install_ept(pml4, (unsigned long)data_page1, 1324 (unsigned long)data_page1, EPT_WA); 1325 ept_sync(INVEPT_SINGLE, eptp); 1326 break; 1327 case 2: 1328 install_ept(pml4, (unsigned long)data_page1, 1329 (unsigned long)data_page1, 1330 EPT_RA | EPT_WA | EPT_EA | 1331 (2 << EPT_MEM_TYPE_SHIFT)); 1332 ept_sync(INVEPT_SINGLE, eptp); 1333 break; 1334 case 3: 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1337 1, &data_page1_pte)); 1338 set_ept_pte(pml4, (unsigned long)data_page1, 1339 1, data_page1_pte & ~EPT_PRESENT); 1340 ept_sync(INVEPT_SINGLE, eptp); 1341 break; 1342 case 4: 1343 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1344 2, &data_page1_pte)); 1345 data_page1_pte &= PAGE_MASK; 1346 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1347 2, &data_page1_pte_pte)); 1348 set_ept_pte(pml4, data_page1_pte, 2, 1349 data_page1_pte_pte & ~EPT_PRESENT); 1350 ept_sync(INVEPT_SINGLE, eptp); 1351 break; 1352 case 5: 1353 install_ept(pml4, (unsigned long)pci_physaddr, 1354 (unsigned long)pci_physaddr, 0); 1355 ept_sync(INVEPT_SINGLE, eptp); 1356 break; 1357 case 7: 1358 if (!invept_test(0, eptp)) 1359 vmx_inc_test_stage(); 1360 break; 1361 // Should not reach here 1362 default: 1363 report("ERROR - unexpected stage, %d.", false, 1364 vmx_get_test_stage()); 1365 print_vmexit_info(); 1366 return VMX_TEST_VMEXIT; 1367 } 1368 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1369 return VMX_TEST_RESUME; 1370 case VMX_EPT_MISCONFIG: 1371 switch (vmx_get_test_stage()) { 1372 case 1: 1373 case 2: 1374 vmx_inc_test_stage(); 1375 install_ept(pml4, (unsigned long)data_page1, 1376 (unsigned long)data_page1, 1377 EPT_RA | EPT_WA | EPT_EA); 1378 ept_sync(INVEPT_SINGLE, eptp); 1379 break; 1380 // Should not reach here 1381 default: 1382 report("ERROR - unexpected stage, %d.", false, 1383 vmx_get_test_stage()); 1384 print_vmexit_info(); 1385 return VMX_TEST_VMEXIT; 1386 } 1387 return VMX_TEST_RESUME; 1388 case VMX_EPT_VIOLATION: 1389 switch(vmx_get_test_stage()) { 1390 case 3: 1391 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1392 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1393 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1394 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1395 EPT_VLT_PADDR)) 1396 vmx_inc_test_stage(); 1397 set_ept_pte(pml4, (unsigned long)data_page1, 1398 1, data_page1_pte | (EPT_PRESENT)); 1399 ept_sync(INVEPT_SINGLE, eptp); 1400 break; 1401 case 4: 1402 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1403 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1404 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1405 if (exit_qual == (EPT_VLT_RD | 1406 (have_ad ? EPT_VLT_WR : 0) | 1407 EPT_VLT_LADDR_VLD)) 1408 vmx_inc_test_stage(); 1409 set_ept_pte(pml4, data_page1_pte, 2, 1410 data_page1_pte_pte | (EPT_PRESENT)); 1411 ept_sync(INVEPT_SINGLE, eptp); 1412 break; 1413 case 5: 1414 if (exit_qual & EPT_VLT_RD) 1415 vmx_inc_test_stage(); 1416 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1417 1, &memaddr_pte)); 1418 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1419 ept_sync(INVEPT_SINGLE, eptp); 1420 break; 1421 case 6: 1422 if (exit_qual & EPT_VLT_WR) 1423 vmx_inc_test_stage(); 1424 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1425 1, &memaddr_pte)); 1426 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1427 ept_sync(INVEPT_SINGLE, eptp); 1428 break; 1429 default: 1430 // Should not reach here 1431 report("ERROR : unexpected stage, %d", false, 1432 vmx_get_test_stage()); 1433 print_vmexit_info(); 1434 return VMX_TEST_VMEXIT; 1435 } 1436 return VMX_TEST_RESUME; 1437 default: 1438 report("Unknown exit reason, %ld", false, reason); 1439 print_vmexit_info(); 1440 } 1441 return VMX_TEST_VMEXIT; 1442 } 1443 1444 static int ept_exit_handler(void) 1445 { 1446 return ept_exit_handler_common(false); 1447 } 1448 1449 static int eptad_init(struct vmcs *vmcs) 1450 { 1451 int r = ept_init_common(true); 1452 1453 if (r == VMX_TEST_EXIT) 1454 return r; 1455 1456 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1457 printf("\tEPT A/D bits are not supported"); 1458 return VMX_TEST_EXIT; 1459 } 1460 1461 return r; 1462 } 1463 1464 static int pml_init(struct vmcs *vmcs) 1465 { 1466 u32 ctrl_cpu; 1467 int r = eptad_init(vmcs); 1468 1469 if (r == VMX_TEST_EXIT) 1470 return r; 1471 1472 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1473 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1474 printf("\tPML is not supported"); 1475 return VMX_TEST_EXIT; 1476 } 1477 1478 pml_log = alloc_page(); 1479 vmcs_write(PMLADDR, (u64)pml_log); 1480 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1481 1482 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1483 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1484 1485 return VMX_TEST_START; 1486 } 1487 1488 static void pml_main(void) 1489 { 1490 int count = 0; 1491 1492 vmx_set_test_stage(0); 1493 *((u32 *)data_page2) = 0x1; 1494 vmcall(); 1495 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1496 1497 while (vmx_get_test_stage() == 1) { 1498 vmcall(); 1499 *((u32 *)data_page2) = 0x1; 1500 if (count++ > PML_INDEX) 1501 break; 1502 } 1503 report("PML Full Event", vmx_get_test_stage() == 2); 1504 } 1505 1506 static void eptad_main(void) 1507 { 1508 ept_common(); 1509 } 1510 1511 static int eptad_exit_handler(void) 1512 { 1513 return ept_exit_handler_common(true); 1514 } 1515 1516 static bool invvpid_test(int type, u16 vpid) 1517 { 1518 bool ret, supported; 1519 1520 supported = ept_vpid.val & 1521 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1522 ret = invvpid(type, vpid, 0); 1523 1524 if (ret == !supported) 1525 return false; 1526 1527 if (!supported) 1528 printf("WARNING: unsupported invvpid passed!\n"); 1529 else 1530 printf("WARNING: invvpid failed!\n"); 1531 1532 return true; 1533 } 1534 1535 static int vpid_init(struct vmcs *vmcs) 1536 { 1537 u32 ctrl_cpu1; 1538 1539 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1540 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1541 printf("\tVPID is not supported"); 1542 return VMX_TEST_EXIT; 1543 } 1544 1545 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1546 ctrl_cpu1 |= CPU_VPID; 1547 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1548 return VMX_TEST_START; 1549 } 1550 1551 static void vpid_main(void) 1552 { 1553 vmx_set_test_stage(0); 1554 vmcall(); 1555 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1556 vmx_set_test_stage(2); 1557 vmcall(); 1558 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1559 vmx_set_test_stage(4); 1560 vmcall(); 1561 report("INVVPID ALL", vmx_get_test_stage() == 5); 1562 } 1563 1564 static int vpid_exit_handler(void) 1565 { 1566 u64 guest_rip; 1567 ulong reason; 1568 u32 insn_len; 1569 1570 guest_rip = vmcs_read(GUEST_RIP); 1571 reason = vmcs_read(EXI_REASON) & 0xff; 1572 insn_len = vmcs_read(EXI_INST_LEN); 1573 1574 switch (reason) { 1575 case VMX_VMCALL: 1576 switch(vmx_get_test_stage()) { 1577 case 0: 1578 if (!invvpid_test(INVVPID_ADDR, 1)) 1579 vmx_inc_test_stage(); 1580 break; 1581 case 2: 1582 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1583 vmx_inc_test_stage(); 1584 break; 1585 case 4: 1586 if (!invvpid_test(INVVPID_ALL, 1)) 1587 vmx_inc_test_stage(); 1588 break; 1589 default: 1590 report("ERROR: unexpected stage, %d", false, 1591 vmx_get_test_stage()); 1592 print_vmexit_info(); 1593 return VMX_TEST_VMEXIT; 1594 } 1595 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1596 return VMX_TEST_RESUME; 1597 default: 1598 report("Unknown exit reason, %ld", false, reason); 1599 print_vmexit_info(); 1600 } 1601 return VMX_TEST_VMEXIT; 1602 } 1603 1604 #define TIMER_VECTOR 222 1605 1606 static volatile bool timer_fired; 1607 1608 static void timer_isr(isr_regs_t *regs) 1609 { 1610 timer_fired = true; 1611 apic_write(APIC_EOI, 0); 1612 } 1613 1614 static int interrupt_init(struct vmcs *vmcs) 1615 { 1616 msr_bmp_init(); 1617 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1618 handle_irq(TIMER_VECTOR, timer_isr); 1619 return VMX_TEST_START; 1620 } 1621 1622 static void interrupt_main(void) 1623 { 1624 long long start, loops; 1625 1626 vmx_set_test_stage(0); 1627 1628 apic_write(APIC_LVTT, TIMER_VECTOR); 1629 irq_enable(); 1630 1631 apic_write(APIC_TMICT, 1); 1632 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1633 asm volatile ("nop"); 1634 report("direct interrupt while running guest", timer_fired); 1635 1636 apic_write(APIC_TMICT, 0); 1637 irq_disable(); 1638 vmcall(); 1639 timer_fired = false; 1640 apic_write(APIC_TMICT, 1); 1641 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1642 asm volatile ("nop"); 1643 report("intercepted interrupt while running guest", timer_fired); 1644 1645 irq_enable(); 1646 apic_write(APIC_TMICT, 0); 1647 irq_disable(); 1648 vmcall(); 1649 timer_fired = false; 1650 start = rdtsc(); 1651 apic_write(APIC_TMICT, 1000000); 1652 1653 asm volatile ("sti; hlt"); 1654 1655 report("direct interrupt + hlt", 1656 rdtsc() - start > 1000000 && timer_fired); 1657 1658 apic_write(APIC_TMICT, 0); 1659 irq_disable(); 1660 vmcall(); 1661 timer_fired = false; 1662 start = rdtsc(); 1663 apic_write(APIC_TMICT, 1000000); 1664 1665 asm volatile ("sti; hlt"); 1666 1667 report("intercepted interrupt + hlt", 1668 rdtsc() - start > 10000 && timer_fired); 1669 1670 apic_write(APIC_TMICT, 0); 1671 irq_disable(); 1672 vmcall(); 1673 timer_fired = false; 1674 start = rdtsc(); 1675 apic_write(APIC_TMICT, 1000000); 1676 1677 irq_enable(); 1678 asm volatile ("nop"); 1679 vmcall(); 1680 1681 report("direct interrupt + activity state hlt", 1682 rdtsc() - start > 10000 && timer_fired); 1683 1684 apic_write(APIC_TMICT, 0); 1685 irq_disable(); 1686 vmcall(); 1687 timer_fired = false; 1688 start = rdtsc(); 1689 apic_write(APIC_TMICT, 1000000); 1690 1691 irq_enable(); 1692 asm volatile ("nop"); 1693 vmcall(); 1694 1695 report("intercepted interrupt + activity state hlt", 1696 rdtsc() - start > 10000 && timer_fired); 1697 1698 apic_write(APIC_TMICT, 0); 1699 irq_disable(); 1700 vmx_set_test_stage(7); 1701 vmcall(); 1702 timer_fired = false; 1703 apic_write(APIC_TMICT, 1); 1704 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1705 asm volatile ("nop"); 1706 report("running a guest with interrupt acknowledgement set", timer_fired); 1707 1708 apic_write(APIC_TMICT, 0); 1709 irq_enable(); 1710 timer_fired = false; 1711 vmcall(); 1712 report("Inject an event to a halted guest", timer_fired); 1713 } 1714 1715 static int interrupt_exit_handler(void) 1716 { 1717 u64 guest_rip = vmcs_read(GUEST_RIP); 1718 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1719 u32 insn_len = vmcs_read(EXI_INST_LEN); 1720 1721 switch (reason) { 1722 case VMX_VMCALL: 1723 switch (vmx_get_test_stage()) { 1724 case 0: 1725 case 2: 1726 case 5: 1727 vmcs_write(PIN_CONTROLS, 1728 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1729 break; 1730 case 7: 1731 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1732 vmcs_write(PIN_CONTROLS, 1733 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1734 break; 1735 case 1: 1736 case 3: 1737 vmcs_write(PIN_CONTROLS, 1738 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1739 break; 1740 case 4: 1741 case 6: 1742 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1743 break; 1744 1745 case 8: 1746 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1747 vmcs_write(ENT_INTR_INFO, 1748 TIMER_VECTOR | 1749 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1750 INTR_INFO_VALID_MASK); 1751 break; 1752 } 1753 vmx_inc_test_stage(); 1754 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1755 return VMX_TEST_RESUME; 1756 case VMX_EXTINT: 1757 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1758 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1759 handle_external_interrupt(vector); 1760 } else { 1761 irq_enable(); 1762 asm volatile ("nop"); 1763 irq_disable(); 1764 } 1765 if (vmx_get_test_stage() >= 2) 1766 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1767 return VMX_TEST_RESUME; 1768 default: 1769 report("Unknown exit reason, %ld", false, reason); 1770 print_vmexit_info(); 1771 } 1772 1773 return VMX_TEST_VMEXIT; 1774 } 1775 1776 static int dbgctls_init(struct vmcs *vmcs) 1777 { 1778 u64 dr7 = 0x402; 1779 u64 zero = 0; 1780 1781 msr_bmp_init(); 1782 asm volatile( 1783 "mov %0,%%dr0\n\t" 1784 "mov %0,%%dr1\n\t" 1785 "mov %0,%%dr2\n\t" 1786 "mov %1,%%dr7\n\t" 1787 : : "r" (zero), "r" (dr7)); 1788 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1789 vmcs_write(GUEST_DR7, 0x404); 1790 vmcs_write(GUEST_DEBUGCTL, 0x2); 1791 1792 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1793 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1794 1795 return VMX_TEST_START; 1796 } 1797 1798 static void dbgctls_main(void) 1799 { 1800 u64 dr7, debugctl; 1801 1802 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1803 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1804 /* Commented out: KVM does not support DEBUGCTL so far */ 1805 (void)debugctl; 1806 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1807 1808 dr7 = 0x408; 1809 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1810 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1811 1812 vmx_set_test_stage(0); 1813 vmcall(); 1814 report("Save debug controls", vmx_get_test_stage() == 1); 1815 1816 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1817 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1818 printf("\tDebug controls are always loaded/saved\n"); 1819 return; 1820 } 1821 vmx_set_test_stage(2); 1822 vmcall(); 1823 1824 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1825 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1826 /* Commented out: KVM does not support DEBUGCTL so far */ 1827 (void)debugctl; 1828 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1829 1830 dr7 = 0x408; 1831 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1832 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1833 1834 vmx_set_test_stage(3); 1835 vmcall(); 1836 report("Don't save debug controls", vmx_get_test_stage() == 4); 1837 } 1838 1839 static int dbgctls_exit_handler(void) 1840 { 1841 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1842 u32 insn_len = vmcs_read(EXI_INST_LEN); 1843 u64 guest_rip = vmcs_read(GUEST_RIP); 1844 u64 dr7, debugctl; 1845 1846 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1847 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1848 1849 switch (reason) { 1850 case VMX_VMCALL: 1851 switch (vmx_get_test_stage()) { 1852 case 0: 1853 if (dr7 == 0x400 && debugctl == 0 && 1854 vmcs_read(GUEST_DR7) == 0x408 /* && 1855 Commented out: KVM does not support DEBUGCTL so far 1856 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1857 vmx_inc_test_stage(); 1858 break; 1859 case 2: 1860 dr7 = 0x402; 1861 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1862 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1863 vmcs_write(GUEST_DR7, 0x404); 1864 vmcs_write(GUEST_DEBUGCTL, 0x2); 1865 1866 vmcs_write(ENT_CONTROLS, 1867 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1868 vmcs_write(EXI_CONTROLS, 1869 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1870 break; 1871 case 3: 1872 if (dr7 == 0x400 && debugctl == 0 && 1873 vmcs_read(GUEST_DR7) == 0x404 /* && 1874 Commented out: KVM does not support DEBUGCTL so far 1875 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1876 vmx_inc_test_stage(); 1877 break; 1878 } 1879 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1880 return VMX_TEST_RESUME; 1881 default: 1882 report("Unknown exit reason, %d", false, reason); 1883 print_vmexit_info(); 1884 } 1885 return VMX_TEST_VMEXIT; 1886 } 1887 1888 struct vmx_msr_entry { 1889 u32 index; 1890 u32 reserved; 1891 u64 value; 1892 } __attribute__((packed)); 1893 1894 #define MSR_MAGIC 0x31415926 1895 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1896 1897 static int msr_switch_init(struct vmcs *vmcs) 1898 { 1899 msr_bmp_init(); 1900 exit_msr_store = alloc_page(); 1901 exit_msr_load = alloc_page(); 1902 entry_msr_load = alloc_page(); 1903 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1904 entry_msr_load[0].value = MSR_MAGIC; 1905 1906 vmx_set_test_stage(1); 1907 vmcs_write(ENT_MSR_LD_CNT, 1); 1908 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1909 vmcs_write(EXI_MSR_ST_CNT, 1); 1910 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1911 vmcs_write(EXI_MSR_LD_CNT, 1); 1912 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1913 return VMX_TEST_START; 1914 } 1915 1916 static void msr_switch_main(void) 1917 { 1918 if (vmx_get_test_stage() == 1) { 1919 report("VM entry MSR load", 1920 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1921 vmx_set_test_stage(2); 1922 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1923 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1924 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1925 exit_msr_load[0].value = MSR_MAGIC + 2; 1926 } 1927 vmcall(); 1928 } 1929 1930 static int msr_switch_exit_handler(void) 1931 { 1932 ulong reason; 1933 1934 reason = vmcs_read(EXI_REASON); 1935 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1936 report("VM exit MSR store", 1937 exit_msr_store[0].value == MSR_MAGIC + 1); 1938 report("VM exit MSR load", 1939 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1940 vmx_set_test_stage(3); 1941 entry_msr_load[0].index = MSR_FS_BASE; 1942 return VMX_TEST_RESUME; 1943 } 1944 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1945 __func__, vmx_get_test_stage(), reason); 1946 return VMX_TEST_EXIT; 1947 } 1948 1949 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1950 { 1951 ulong reason; 1952 1953 if (failure->early) { 1954 printf("ERROR %s: early exit\n", __func__); 1955 return VMX_TEST_EXIT; 1956 } 1957 1958 reason = vmcs_read(EXI_REASON); 1959 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1960 vmx_get_test_stage() == 3) { 1961 report("VM entry MSR load: try to load FS_BASE", 1962 vmcs_read(EXI_QUALIFICATION) == 1); 1963 return VMX_TEST_VMEXIT; 1964 } 1965 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1966 __func__, vmx_get_test_stage(), reason); 1967 return VMX_TEST_EXIT; 1968 } 1969 1970 static int vmmcall_init(struct vmcs *vmcs) 1971 { 1972 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1973 return VMX_TEST_START; 1974 } 1975 1976 static void vmmcall_main(void) 1977 { 1978 asm volatile( 1979 "mov $0xABCD, %%rax\n\t" 1980 "vmmcall\n\t" 1981 ::: "rax"); 1982 1983 report("VMMCALL", 0); 1984 } 1985 1986 static int vmmcall_exit_handler(void) 1987 { 1988 ulong reason; 1989 1990 reason = vmcs_read(EXI_REASON); 1991 switch (reason) { 1992 case VMX_VMCALL: 1993 printf("here\n"); 1994 report("VMMCALL triggers #UD", 0); 1995 break; 1996 case VMX_EXC_NMI: 1997 report("VMMCALL triggers #UD", 1998 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1999 break; 2000 default: 2001 report("Unknown exit reason, %ld", false, reason); 2002 print_vmexit_info(); 2003 } 2004 2005 return VMX_TEST_VMEXIT; 2006 } 2007 2008 static int disable_rdtscp_init(struct vmcs *vmcs) 2009 { 2010 u32 ctrl_cpu1; 2011 2012 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2013 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2014 ctrl_cpu1 &= ~CPU_RDTSCP; 2015 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2016 } 2017 2018 return VMX_TEST_START; 2019 } 2020 2021 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2022 { 2023 switch (vmx_get_test_stage()) { 2024 case 0: 2025 report("RDTSCP triggers #UD", true); 2026 vmx_inc_test_stage(); 2027 regs->rip += 3; 2028 break; 2029 case 2: 2030 report("RDPID triggers #UD", true); 2031 vmx_inc_test_stage(); 2032 regs->rip += 4; 2033 break; 2034 } 2035 return; 2036 2037 } 2038 2039 static void disable_rdtscp_main(void) 2040 { 2041 /* Test that #UD is properly injected in L2. */ 2042 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2043 2044 vmx_set_test_stage(0); 2045 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2046 vmcall(); 2047 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2048 2049 handle_exception(UD_VECTOR, 0); 2050 vmcall(); 2051 } 2052 2053 static int disable_rdtscp_exit_handler(void) 2054 { 2055 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2056 2057 switch (reason) { 2058 case VMX_VMCALL: 2059 switch (vmx_get_test_stage()) { 2060 case 0: 2061 report("RDTSCP triggers #UD", false); 2062 vmx_inc_test_stage(); 2063 /* fallthrough */ 2064 case 1: 2065 vmx_inc_test_stage(); 2066 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2067 return VMX_TEST_RESUME; 2068 case 2: 2069 report("RDPID triggers #UD", false); 2070 break; 2071 } 2072 break; 2073 2074 default: 2075 report("Unknown exit reason, %d", false, reason); 2076 print_vmexit_info(); 2077 } 2078 return VMX_TEST_VMEXIT; 2079 } 2080 2081 static int int3_init(struct vmcs *vmcs) 2082 { 2083 vmcs_write(EXC_BITMAP, ~0u); 2084 return VMX_TEST_START; 2085 } 2086 2087 static void int3_guest_main(void) 2088 { 2089 asm volatile ("int3"); 2090 } 2091 2092 static int int3_exit_handler(void) 2093 { 2094 u32 reason = vmcs_read(EXI_REASON); 2095 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2096 2097 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2098 (intr_info & INTR_INFO_VALID_MASK) && 2099 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2100 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2101 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2102 2103 return VMX_TEST_VMEXIT; 2104 } 2105 2106 static int into_init(struct vmcs *vmcs) 2107 { 2108 vmcs_write(EXC_BITMAP, ~0u); 2109 return VMX_TEST_START; 2110 } 2111 2112 static void into_guest_main(void) 2113 { 2114 struct far_pointer32 fp = { 2115 .offset = (uintptr_t)&&into, 2116 .selector = KERNEL_CS32, 2117 }; 2118 register uintptr_t rsp asm("rsp"); 2119 2120 if (fp.offset != (uintptr_t)&&into) { 2121 printf("Code address too high.\n"); 2122 return; 2123 } 2124 if ((u32)rsp != rsp) { 2125 printf("Stack address too high.\n"); 2126 return; 2127 } 2128 2129 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2130 return; 2131 into: 2132 asm volatile (".code32;" 2133 "movl $0x7fffffff, %eax;" 2134 "addl %eax, %eax;" 2135 "into;" 2136 "lret;" 2137 ".code64"); 2138 __builtin_unreachable(); 2139 } 2140 2141 static int into_exit_handler(void) 2142 { 2143 u32 reason = vmcs_read(EXI_REASON); 2144 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2145 2146 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2147 (intr_info & INTR_INFO_VALID_MASK) && 2148 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2149 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2150 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2151 2152 return VMX_TEST_VMEXIT; 2153 } 2154 2155 static void exit_monitor_from_l2_main(void) 2156 { 2157 printf("Calling exit(0) from l2...\n"); 2158 exit(0); 2159 } 2160 2161 static int exit_monitor_from_l2_handler(void) 2162 { 2163 report("The guest should have killed the VMM", false); 2164 return VMX_TEST_EXIT; 2165 } 2166 2167 static void assert_exit_reason(u64 expected) 2168 { 2169 u64 actual = vmcs_read(EXI_REASON); 2170 2171 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2172 exit_reason_description(expected), 2173 exit_reason_description(actual)); 2174 } 2175 2176 static void skip_exit_insn(void) 2177 { 2178 u64 guest_rip = vmcs_read(GUEST_RIP); 2179 u32 insn_len = vmcs_read(EXI_INST_LEN); 2180 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2181 } 2182 2183 static void skip_exit_vmcall(void) 2184 { 2185 assert_exit_reason(VMX_VMCALL); 2186 skip_exit_insn(); 2187 } 2188 2189 static void v2_null_test_guest(void) 2190 { 2191 } 2192 2193 static void v2_null_test(void) 2194 { 2195 test_set_guest(v2_null_test_guest); 2196 enter_guest(); 2197 report(__func__, 1); 2198 } 2199 2200 static void v2_multiple_entries_test_guest(void) 2201 { 2202 vmx_set_test_stage(1); 2203 vmcall(); 2204 vmx_set_test_stage(2); 2205 } 2206 2207 static void v2_multiple_entries_test(void) 2208 { 2209 test_set_guest(v2_multiple_entries_test_guest); 2210 enter_guest(); 2211 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2212 skip_exit_vmcall(); 2213 enter_guest(); 2214 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2215 report(__func__, 1); 2216 } 2217 2218 static int fixture_test_data = 1; 2219 2220 static void fixture_test_teardown(void *data) 2221 { 2222 *((int *) data) = 1; 2223 } 2224 2225 static void fixture_test_guest(void) 2226 { 2227 fixture_test_data++; 2228 } 2229 2230 2231 static void fixture_test_setup(void) 2232 { 2233 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2234 "fixture_test_teardown didn't run?!"); 2235 fixture_test_data = 2; 2236 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2237 test_set_guest(fixture_test_guest); 2238 } 2239 2240 static void fixture_test_case1(void) 2241 { 2242 fixture_test_setup(); 2243 TEST_ASSERT_EQ(2, fixture_test_data); 2244 enter_guest(); 2245 TEST_ASSERT_EQ(3, fixture_test_data); 2246 report(__func__, 1); 2247 } 2248 2249 static void fixture_test_case2(void) 2250 { 2251 fixture_test_setup(); 2252 TEST_ASSERT_EQ(2, fixture_test_data); 2253 enter_guest(); 2254 TEST_ASSERT_EQ(3, fixture_test_data); 2255 report(__func__, 1); 2256 } 2257 2258 enum ept_access_op { 2259 OP_READ, 2260 OP_WRITE, 2261 OP_EXEC, 2262 OP_FLUSH_TLB, 2263 OP_EXIT, 2264 }; 2265 2266 static struct ept_access_test_data { 2267 unsigned long gpa; 2268 unsigned long *gva; 2269 unsigned long hpa; 2270 unsigned long *hva; 2271 enum ept_access_op op; 2272 } ept_access_test_data; 2273 2274 extern unsigned char ret42_start; 2275 extern unsigned char ret42_end; 2276 2277 /* Returns 42. */ 2278 asm( 2279 ".align 64\n" 2280 "ret42_start:\n" 2281 "mov $42, %eax\n" 2282 "ret\n" 2283 "ret42_end:\n" 2284 ); 2285 2286 static void 2287 diagnose_ept_violation_qual(u64 expected, u64 actual) 2288 { 2289 2290 #define DIAGNOSE(flag) \ 2291 do { \ 2292 if ((expected & flag) != (actual & flag)) \ 2293 printf(#flag " %sexpected\n", \ 2294 (expected & flag) ? "" : "un"); \ 2295 } while (0) 2296 2297 DIAGNOSE(EPT_VLT_RD); 2298 DIAGNOSE(EPT_VLT_WR); 2299 DIAGNOSE(EPT_VLT_FETCH); 2300 DIAGNOSE(EPT_VLT_PERM_RD); 2301 DIAGNOSE(EPT_VLT_PERM_WR); 2302 DIAGNOSE(EPT_VLT_PERM_EX); 2303 DIAGNOSE(EPT_VLT_LADDR_VLD); 2304 DIAGNOSE(EPT_VLT_PADDR); 2305 2306 #undef DIAGNOSE 2307 } 2308 2309 static void do_ept_access_op(enum ept_access_op op) 2310 { 2311 ept_access_test_data.op = op; 2312 enter_guest(); 2313 } 2314 2315 /* 2316 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2317 * needed by tests that modify guest PTEs. 2318 */ 2319 static void ept_access_test_guest_flush_tlb(void) 2320 { 2321 do_ept_access_op(OP_FLUSH_TLB); 2322 skip_exit_vmcall(); 2323 } 2324 2325 /* 2326 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2327 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2328 * a huge page. 2329 */ 2330 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2331 unsigned long clear, unsigned long set) 2332 { 2333 struct ept_access_test_data *data = &ept_access_test_data; 2334 unsigned long orig_pte; 2335 unsigned long pte; 2336 2337 /* Screw with the mapping at the requested level. */ 2338 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2339 pte = orig_pte; 2340 if (mkhuge) 2341 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2342 else 2343 pte = orig_pte; 2344 pte = (pte & ~clear) | set; 2345 set_ept_pte(pml4, gpa, level, pte); 2346 ept_sync(INVEPT_SINGLE, eptp); 2347 2348 return orig_pte; 2349 } 2350 2351 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2352 { 2353 set_ept_pte(pml4, gpa, level, orig_pte); 2354 } 2355 2356 static void do_ept_violation(bool leaf, enum ept_access_op op, 2357 u64 expected_qual, u64 expected_paddr) 2358 { 2359 u64 qual; 2360 2361 /* Try the access and observe the violation. */ 2362 do_ept_access_op(op); 2363 2364 assert_exit_reason(VMX_EPT_VIOLATION); 2365 2366 qual = vmcs_read(EXI_QUALIFICATION); 2367 2368 diagnose_ept_violation_qual(expected_qual, qual); 2369 TEST_EXPECT_EQ(expected_qual, qual); 2370 2371 #if 0 2372 /* Disable for now otherwise every test will fail */ 2373 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2374 (unsigned long) ( 2375 op == OP_EXEC ? data->gva + 1 : data->gva)); 2376 #endif 2377 /* 2378 * TODO: tests that probe expected_paddr in pages other than the one at 2379 * the beginning of the 1g region. 2380 */ 2381 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2382 } 2383 2384 static void 2385 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2386 unsigned long set, enum ept_access_op op, 2387 u64 expected_qual) 2388 { 2389 struct ept_access_test_data *data = &ept_access_test_data; 2390 unsigned long orig_pte; 2391 2392 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2393 2394 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2395 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2396 data->gpa); 2397 2398 /* Fix the violation and resume the op loop. */ 2399 ept_untwiddle(data->gpa, level, orig_pte); 2400 enter_guest(); 2401 skip_exit_vmcall(); 2402 } 2403 2404 static void 2405 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2406 enum ept_access_op op, u64 expected_qual) 2407 { 2408 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2409 expected_qual); 2410 if (ept_huge_pages_supported(level)) 2411 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2412 expected_qual); 2413 } 2414 2415 static void ept_violation(unsigned long clear, unsigned long set, 2416 enum ept_access_op op, u64 expected_qual) 2417 { 2418 ept_violation_at_level(1, clear, set, op, expected_qual); 2419 ept_violation_at_level(2, clear, set, op, expected_qual); 2420 ept_violation_at_level(3, clear, set, op, expected_qual); 2421 ept_violation_at_level(4, clear, set, op, expected_qual); 2422 } 2423 2424 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2425 u64 expected_qual) 2426 { 2427 ept_violation(EPT_PRESENT, access, op, 2428 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2429 } 2430 2431 /* 2432 * For translations that don't involve a GVA, that is physical address (paddr) 2433 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2434 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2435 * translations don't involve GVAs, such as when the hardware does the guest 2436 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2437 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2438 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2439 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2440 * 2441 * Note that paddr violations can also be triggered by loading PAE page tables 2442 * with wonky addresses. We don't test that yet. 2443 * 2444 * This function modifies the EPT entry that maps the GPA that the guest page 2445 * table entry mapping ept_access_data.gva resides on. 2446 * 2447 * @ept_access EPT permissions to set. Other permissions are cleared. 2448 * 2449 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2450 * 2451 * @op Guest operation to perform with ept_access_data.gva. 2452 * 2453 * @expect_violation 2454 * Is a violation expected during the paddr access? 2455 * 2456 * @expected_qual Expected qualification for the EPT violation. 2457 * EPT_VLT_PADDR should be clear. 2458 */ 2459 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2460 enum ept_access_op op, bool expect_violation, 2461 u64 expected_qual) 2462 { 2463 struct ept_access_test_data *data = &ept_access_test_data; 2464 unsigned long *ptep; 2465 unsigned long gpa; 2466 unsigned long orig_epte; 2467 2468 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2469 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2470 TEST_ASSERT(ptep); 2471 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2472 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2473 ept_access_test_guest_flush_tlb(); 2474 2475 /* 2476 * Now modify the access bits on the EPT entry for the GPA that the 2477 * guest PTE resides on. Note that by modifying a single EPT entry, 2478 * we're potentially affecting 512 guest PTEs. However, we've carefully 2479 * constructed our test such that those other 511 PTEs aren't used by 2480 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2481 * PTE we're modifying is at the beginning of a 4K page and the 2482 * following 511 entires are also under our control (and not touched by 2483 * the guest). 2484 */ 2485 gpa = virt_to_phys(ptep); 2486 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2487 /* 2488 * Make sure the guest page table page is mapped with a 4K EPT entry, 2489 * otherwise our level=1 twiddling below will fail. We use the 2490 * identity map (gpa = gpa) since page tables are shared with the host. 2491 */ 2492 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2493 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2494 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2495 2496 if (expect_violation) { 2497 do_ept_violation(/*leaf=*/true, op, 2498 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2499 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2500 do_ept_access_op(op); 2501 } else { 2502 do_ept_access_op(op); 2503 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2504 } 2505 2506 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2507 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2508 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2509 2510 skip_exit_vmcall(); 2511 } 2512 2513 static void ept_access_allowed_paddr(unsigned long ept_access, 2514 unsigned long pte_ad, 2515 enum ept_access_op op) 2516 { 2517 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2518 /*expected_qual=*/-1); 2519 } 2520 2521 static void ept_access_violation_paddr(unsigned long ept_access, 2522 unsigned long pte_ad, 2523 enum ept_access_op op, 2524 u64 expected_qual) 2525 { 2526 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2527 expected_qual); 2528 } 2529 2530 2531 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2532 unsigned long clear, 2533 unsigned long set, 2534 enum ept_access_op op) 2535 { 2536 struct ept_access_test_data *data = &ept_access_test_data; 2537 unsigned long orig_pte; 2538 2539 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2540 2541 /* No violation. Should proceed to vmcall. */ 2542 do_ept_access_op(op); 2543 skip_exit_vmcall(); 2544 2545 ept_untwiddle(data->gpa, level, orig_pte); 2546 } 2547 2548 static void ept_allowed_at_level(int level, unsigned long clear, 2549 unsigned long set, enum ept_access_op op) 2550 { 2551 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2552 if (ept_huge_pages_supported(level)) 2553 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2554 } 2555 2556 static void ept_allowed(unsigned long clear, unsigned long set, 2557 enum ept_access_op op) 2558 { 2559 ept_allowed_at_level(1, clear, set, op); 2560 ept_allowed_at_level(2, clear, set, op); 2561 ept_allowed_at_level(3, clear, set, op); 2562 ept_allowed_at_level(4, clear, set, op); 2563 } 2564 2565 static void ept_ignored_bit(int bit) 2566 { 2567 /* Set the bit. */ 2568 ept_allowed(0, 1ul << bit, OP_READ); 2569 ept_allowed(0, 1ul << bit, OP_WRITE); 2570 ept_allowed(0, 1ul << bit, OP_EXEC); 2571 2572 /* Clear the bit. */ 2573 ept_allowed(1ul << bit, 0, OP_READ); 2574 ept_allowed(1ul << bit, 0, OP_WRITE); 2575 ept_allowed(1ul << bit, 0, OP_EXEC); 2576 } 2577 2578 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2579 { 2580 ept_allowed(EPT_PRESENT, access, op); 2581 } 2582 2583 2584 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2585 unsigned long clear, 2586 unsigned long set, 2587 enum ept_access_op op) 2588 { 2589 struct ept_access_test_data *data = &ept_access_test_data; 2590 unsigned long orig_pte; 2591 2592 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2593 2594 do_ept_access_op(op); 2595 assert_exit_reason(VMX_EPT_MISCONFIG); 2596 2597 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2598 #if 0 2599 /* broken: */ 2600 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2601 #endif 2602 #if 0 2603 /* 2604 * broken: 2605 * According to description of exit qual for EPT violation, 2606 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2607 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2608 * to be set for msiconfig. 2609 */ 2610 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2611 (unsigned long) ( 2612 op == OP_EXEC ? data->gva + 1 : data->gva)); 2613 #endif 2614 2615 /* Fix the violation and resume the op loop. */ 2616 ept_untwiddle(data->gpa, level, orig_pte); 2617 enter_guest(); 2618 skip_exit_vmcall(); 2619 } 2620 2621 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2622 unsigned long clear, 2623 unsigned long set) 2624 { 2625 /* The op shouldn't matter (read, write, exec), so try them all! */ 2626 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2627 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2628 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2629 } 2630 2631 static void ept_misconfig_at_level(int level, unsigned long clear, 2632 unsigned long set) 2633 { 2634 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2635 if (ept_huge_pages_supported(level)) 2636 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2637 } 2638 2639 static void ept_misconfig(unsigned long clear, unsigned long set) 2640 { 2641 ept_misconfig_at_level(1, clear, set); 2642 ept_misconfig_at_level(2, clear, set); 2643 ept_misconfig_at_level(3, clear, set); 2644 ept_misconfig_at_level(4, clear, set); 2645 } 2646 2647 static void ept_access_misconfig(unsigned long access) 2648 { 2649 ept_misconfig(EPT_PRESENT, access); 2650 } 2651 2652 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2653 { 2654 /* Setting the bit causes a misconfig. */ 2655 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2656 2657 /* Making the entry non-present turns reserved bits into ignored. */ 2658 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2659 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2660 } 2661 2662 static void ept_reserved_bit_at_level_huge(int level, int bit) 2663 { 2664 /* Setting the bit causes a misconfig. */ 2665 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2666 2667 /* Making the entry non-present turns reserved bits into ignored. */ 2668 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2669 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2670 } 2671 2672 static void ept_reserved_bit_at_level(int level, int bit) 2673 { 2674 /* Setting the bit causes a misconfig. */ 2675 ept_misconfig_at_level(level, 0, 1ul << bit); 2676 2677 /* Making the entry non-present turns reserved bits into ignored. */ 2678 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2679 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2680 } 2681 2682 static void ept_reserved_bit(int bit) 2683 { 2684 ept_reserved_bit_at_level(1, bit); 2685 ept_reserved_bit_at_level(2, bit); 2686 ept_reserved_bit_at_level(3, bit); 2687 ept_reserved_bit_at_level(4, bit); 2688 } 2689 2690 #define PAGE_2M_ORDER 9 2691 #define PAGE_1G_ORDER 18 2692 2693 static void *get_1g_page(void) 2694 { 2695 static void *alloc; 2696 2697 if (!alloc) 2698 alloc = alloc_pages(PAGE_1G_ORDER); 2699 return alloc; 2700 } 2701 2702 static void ept_access_test_teardown(void *unused) 2703 { 2704 /* Exit the guest cleanly. */ 2705 do_ept_access_op(OP_EXIT); 2706 } 2707 2708 static void ept_access_test_guest(void) 2709 { 2710 struct ept_access_test_data *data = &ept_access_test_data; 2711 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2712 2713 while (true) { 2714 switch (data->op) { 2715 case OP_READ: 2716 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2717 break; 2718 case OP_WRITE: 2719 *data->gva = MAGIC_VAL_2; 2720 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2721 *data->gva = MAGIC_VAL_1; 2722 break; 2723 case OP_EXEC: 2724 TEST_ASSERT_EQ(42, code()); 2725 break; 2726 case OP_FLUSH_TLB: 2727 write_cr3(read_cr3()); 2728 break; 2729 case OP_EXIT: 2730 return; 2731 default: 2732 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2733 } 2734 vmcall(); 2735 } 2736 } 2737 2738 static void ept_access_test_setup(void) 2739 { 2740 struct ept_access_test_data *data = &ept_access_test_data; 2741 unsigned long npages = 1ul << PAGE_1G_ORDER; 2742 unsigned long size = npages * PAGE_SIZE; 2743 unsigned long *page_table = current_page_table(); 2744 unsigned long pte; 2745 2746 if (setup_ept(false)) 2747 test_skip("EPT not supported"); 2748 2749 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2750 if (cpuid_maxphyaddr() < 40) 2751 test_skip("Test needs MAXPHYADDR >= 40"); 2752 2753 test_set_guest(ept_access_test_guest); 2754 test_add_teardown(ept_access_test_teardown, NULL); 2755 2756 data->hva = get_1g_page(); 2757 TEST_ASSERT(data->hva); 2758 data->hpa = virt_to_phys(data->hva); 2759 2760 data->gpa = 1ul << 39; 2761 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2762 size); 2763 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2764 install_pages(page_table, data->gpa, size, data->gva); 2765 2766 /* 2767 * Make sure nothing's mapped here so the tests that screw with the 2768 * pml4 entry don't inadvertently break something. 2769 */ 2770 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2771 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2772 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2773 2774 data->hva[0] = MAGIC_VAL_1; 2775 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2776 } 2777 2778 static void ept_access_test_not_present(void) 2779 { 2780 ept_access_test_setup(); 2781 /* --- */ 2782 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2783 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2784 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2785 } 2786 2787 static void ept_access_test_read_only(void) 2788 { 2789 ept_access_test_setup(); 2790 2791 /* r-- */ 2792 ept_access_allowed(EPT_RA, OP_READ); 2793 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2794 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2795 } 2796 2797 static void ept_access_test_write_only(void) 2798 { 2799 ept_access_test_setup(); 2800 /* -w- */ 2801 ept_access_misconfig(EPT_WA); 2802 } 2803 2804 static void ept_access_test_read_write(void) 2805 { 2806 ept_access_test_setup(); 2807 /* rw- */ 2808 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2809 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2810 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2811 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2812 } 2813 2814 2815 static void ept_access_test_execute_only(void) 2816 { 2817 ept_access_test_setup(); 2818 /* --x */ 2819 if (ept_execute_only_supported()) { 2820 ept_access_violation(EPT_EA, OP_READ, 2821 EPT_VLT_RD | EPT_VLT_PERM_EX); 2822 ept_access_violation(EPT_EA, OP_WRITE, 2823 EPT_VLT_WR | EPT_VLT_PERM_EX); 2824 ept_access_allowed(EPT_EA, OP_EXEC); 2825 } else { 2826 ept_access_misconfig(EPT_EA); 2827 } 2828 } 2829 2830 static void ept_access_test_read_execute(void) 2831 { 2832 ept_access_test_setup(); 2833 /* r-x */ 2834 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2835 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2836 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2837 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2838 } 2839 2840 static void ept_access_test_write_execute(void) 2841 { 2842 ept_access_test_setup(); 2843 /* -wx */ 2844 ept_access_misconfig(EPT_WA | EPT_EA); 2845 } 2846 2847 static void ept_access_test_read_write_execute(void) 2848 { 2849 ept_access_test_setup(); 2850 /* rwx */ 2851 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2852 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2853 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2854 } 2855 2856 static void ept_access_test_reserved_bits(void) 2857 { 2858 int i; 2859 int maxphyaddr; 2860 2861 ept_access_test_setup(); 2862 2863 /* Reserved bits above maxphyaddr. */ 2864 maxphyaddr = cpuid_maxphyaddr(); 2865 for (i = maxphyaddr; i <= 51; i++) { 2866 report_prefix_pushf("reserved_bit=%d", i); 2867 ept_reserved_bit(i); 2868 report_prefix_pop(); 2869 } 2870 2871 /* Level-specific reserved bits. */ 2872 ept_reserved_bit_at_level_nohuge(2, 3); 2873 ept_reserved_bit_at_level_nohuge(2, 4); 2874 ept_reserved_bit_at_level_nohuge(2, 5); 2875 ept_reserved_bit_at_level_nohuge(2, 6); 2876 /* 2M alignment. */ 2877 for (i = 12; i < 20; i++) { 2878 report_prefix_pushf("reserved_bit=%d", i); 2879 ept_reserved_bit_at_level_huge(2, i); 2880 report_prefix_pop(); 2881 } 2882 ept_reserved_bit_at_level_nohuge(3, 3); 2883 ept_reserved_bit_at_level_nohuge(3, 4); 2884 ept_reserved_bit_at_level_nohuge(3, 5); 2885 ept_reserved_bit_at_level_nohuge(3, 6); 2886 /* 1G alignment. */ 2887 for (i = 12; i < 29; i++) { 2888 report_prefix_pushf("reserved_bit=%d", i); 2889 ept_reserved_bit_at_level_huge(3, i); 2890 report_prefix_pop(); 2891 } 2892 ept_reserved_bit_at_level(4, 3); 2893 ept_reserved_bit_at_level(4, 4); 2894 ept_reserved_bit_at_level(4, 5); 2895 ept_reserved_bit_at_level(4, 6); 2896 ept_reserved_bit_at_level(4, 7); 2897 } 2898 2899 static void ept_access_test_ignored_bits(void) 2900 { 2901 ept_access_test_setup(); 2902 /* 2903 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2904 * far as translation is concerned even if AD bits are enabled in the 2905 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2906 * control is 0. 2907 */ 2908 ept_ignored_bit(8); 2909 ept_ignored_bit(9); 2910 ept_ignored_bit(10); 2911 ept_ignored_bit(11); 2912 ept_ignored_bit(52); 2913 ept_ignored_bit(53); 2914 ept_ignored_bit(54); 2915 ept_ignored_bit(55); 2916 ept_ignored_bit(56); 2917 ept_ignored_bit(57); 2918 ept_ignored_bit(58); 2919 ept_ignored_bit(59); 2920 ept_ignored_bit(60); 2921 ept_ignored_bit(61); 2922 ept_ignored_bit(62); 2923 ept_ignored_bit(63); 2924 } 2925 2926 static void ept_access_test_paddr_not_present_ad_disabled(void) 2927 { 2928 ept_access_test_setup(); 2929 ept_disable_ad_bits(); 2930 2931 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2932 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2933 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2934 } 2935 2936 static void ept_access_test_paddr_not_present_ad_enabled(void) 2937 { 2938 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2939 2940 ept_access_test_setup(); 2941 ept_enable_ad_bits_or_skip_test(); 2942 2943 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2944 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2945 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2946 } 2947 2948 static void ept_access_test_paddr_read_only_ad_disabled(void) 2949 { 2950 /* 2951 * When EPT AD bits are disabled, all accesses to guest paging 2952 * structures are reported separately as a read and (after 2953 * translation of the GPA to host physical address) a read+write 2954 * if the A/D bits have to be set. 2955 */ 2956 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2957 2958 ept_access_test_setup(); 2959 ept_disable_ad_bits(); 2960 2961 /* Can't update A bit, so all accesses fail. */ 2962 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2963 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2964 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2965 /* AD bits disabled, so only writes try to update the D bit. */ 2966 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2967 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2968 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2969 /* Both A and D already set, so read-only is OK. */ 2970 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2971 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2972 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2973 } 2974 2975 static void ept_access_test_paddr_read_only_ad_enabled(void) 2976 { 2977 /* 2978 * When EPT AD bits are enabled, all accesses to guest paging 2979 * structures are considered writes as far as EPT translation 2980 * is concerned. 2981 */ 2982 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2983 2984 ept_access_test_setup(); 2985 ept_enable_ad_bits_or_skip_test(); 2986 2987 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2988 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2989 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2990 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2991 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2992 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2993 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2994 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2995 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2996 } 2997 2998 static void ept_access_test_paddr_read_write(void) 2999 { 3000 ept_access_test_setup(); 3001 /* Read-write access to paging structure. */ 3002 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3003 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3004 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3005 } 3006 3007 static void ept_access_test_paddr_read_write_execute(void) 3008 { 3009 ept_access_test_setup(); 3010 /* RWX access to paging structure. */ 3011 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3012 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3013 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3014 } 3015 3016 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3017 { 3018 /* 3019 * When EPT AD bits are disabled, all accesses to guest paging 3020 * structures are reported separately as a read and (after 3021 * translation of the GPA to host physical address) a read+write 3022 * if the A/D bits have to be set. 3023 */ 3024 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3025 3026 ept_access_test_setup(); 3027 ept_disable_ad_bits(); 3028 3029 /* Can't update A bit, so all accesses fail. */ 3030 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3031 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3032 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3033 /* AD bits disabled, so only writes try to update the D bit. */ 3034 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3035 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3036 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3037 /* Both A and D already set, so read-only is OK. */ 3038 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3039 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3040 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3041 } 3042 3043 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3044 { 3045 /* 3046 * When EPT AD bits are enabled, all accesses to guest paging 3047 * structures are considered writes as far as EPT translation 3048 * is concerned. 3049 */ 3050 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3051 3052 ept_access_test_setup(); 3053 ept_enable_ad_bits_or_skip_test(); 3054 3055 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3056 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3057 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3058 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3062 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3063 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3064 } 3065 3066 static void ept_access_test_paddr_not_present_page_fault(void) 3067 { 3068 ept_access_test_setup(); 3069 /* 3070 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3071 * page is read-only in EPT but GVA is also mapped read only in PT. 3072 * Thus guest page fault before host takes EPT violation for trying to 3073 * update A bit. 3074 */ 3075 } 3076 3077 static void ept_access_test_force_2m_page(void) 3078 { 3079 ept_access_test_setup(); 3080 3081 TEST_ASSERT_EQ(ept_2m_supported(), true); 3082 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3083 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3084 EPT_VLT_WR | EPT_VLT_PERM_RD | 3085 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3086 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3087 } 3088 3089 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3090 { 3091 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3092 3093 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3094 3095 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3096 return false; 3097 3098 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3099 return false; 3100 3101 if (vpid >> 16) 3102 return false; 3103 3104 if (type != INVVPID_ALL && !vpid) 3105 return false; 3106 3107 if (type == INVVPID_ADDR && !is_canonical(gla)) 3108 return false; 3109 3110 return true; 3111 } 3112 3113 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3114 { 3115 int rc; 3116 bool valid = invvpid_valid(type, vpid, gla); 3117 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3118 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3119 /* 3120 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3121 * that we can tell if it is updated by INVVPID. 3122 */ 3123 vmcs_read(~0); 3124 rc = invvpid(type, vpid, gla); 3125 report("INVVPID type %ld VPID %lx GLA %lx %s", 3126 !rc == valid, type, vpid, gla, 3127 valid ? "passes" : "fails"); 3128 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3129 vmcs_read(VMX_INST_ERROR) == expected, 3130 rc ? "failed" : "successful", 3131 expected, vmcs_read(VMX_INST_ERROR)); 3132 } 3133 3134 static void ds_invvpid(void *data) 3135 { 3136 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3137 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3138 3139 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3140 asm volatile("invvpid %0, %1" 3141 : 3142 : "m"(*(struct invvpid_operand *)data), 3143 "r"(type)); 3144 } 3145 3146 /* 3147 * The SS override is ignored in 64-bit mode, so we use an addressing 3148 * mode with %rsp as the base register to generate an implicit SS 3149 * reference. 3150 */ 3151 static void ss_invvpid(void *data) 3152 { 3153 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3154 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3155 3156 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3157 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3158 : "+r"(data) 3159 : "r"(type)); 3160 } 3161 3162 static void invvpid_test_gp(void) 3163 { 3164 bool fault; 3165 3166 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3167 (void *)NONCANONICAL); 3168 report("INVVPID with non-canonical DS operand raises #GP", fault); 3169 } 3170 3171 static void invvpid_test_ss(void) 3172 { 3173 bool fault; 3174 3175 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3176 (void *)NONCANONICAL); 3177 report("INVVPID with non-canonical SS operand raises #SS", fault); 3178 } 3179 3180 static void invvpid_test_pf(void) 3181 { 3182 void *vpage = alloc_vpage(); 3183 bool fault; 3184 3185 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3186 report("INVVPID with unmapped operand raises #PF", fault); 3187 } 3188 3189 static void try_compat_invvpid(void *unused) 3190 { 3191 struct far_pointer32 fp = { 3192 .offset = (uintptr_t)&&invvpid, 3193 .selector = KERNEL_CS32, 3194 }; 3195 register uintptr_t rsp asm("rsp"); 3196 3197 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3198 "Code address too high."); 3199 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3200 3201 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3202 return; 3203 invvpid: 3204 asm volatile (".code32;" 3205 "invvpid (%eax), %eax;" 3206 "lret;" 3207 ".code64"); 3208 __builtin_unreachable(); 3209 } 3210 3211 static void invvpid_test_compatibility_mode(void) 3212 { 3213 bool fault; 3214 3215 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3216 report("Compatibility mode INVVPID raises #UD", fault); 3217 } 3218 3219 static void invvpid_test_not_in_vmx_operation(void) 3220 { 3221 bool fault; 3222 3223 TEST_ASSERT(!vmx_off()); 3224 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3225 report("INVVPID outside of VMX operation raises #UD", fault); 3226 TEST_ASSERT(!vmx_on()); 3227 } 3228 3229 /* 3230 * This does not test real-address mode, virtual-8086 mode, protected mode, 3231 * or CPL > 0. 3232 */ 3233 static void invvpid_test_v2(void) 3234 { 3235 u64 msr; 3236 int i; 3237 unsigned types = 0; 3238 unsigned type; 3239 3240 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3241 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3242 test_skip("VPID not supported"); 3243 3244 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3245 3246 if (!(msr & VPID_CAP_INVVPID)) 3247 test_skip("INVVPID not supported.\n"); 3248 3249 if (msr & VPID_CAP_INVVPID_ADDR) 3250 types |= 1u << INVVPID_ADDR; 3251 if (msr & VPID_CAP_INVVPID_CXTGLB) 3252 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3253 if (msr & VPID_CAP_INVVPID_ALL) 3254 types |= 1u << INVVPID_ALL; 3255 if (msr & VPID_CAP_INVVPID_CXTLOC) 3256 types |= 1u << INVVPID_CONTEXT_LOCAL; 3257 3258 if (!types) 3259 test_skip("No INVVPID types supported.\n"); 3260 3261 for (i = -127; i < 128; i++) 3262 try_invvpid(i, 0xffff, 0); 3263 3264 /* 3265 * VPID must not be more than 16 bits. 3266 */ 3267 for (i = 0; i < 64; i++) 3268 for (type = 0; type < 4; type++) 3269 if (types & (1u << type)) 3270 try_invvpid(type, 1ul << i, 0); 3271 3272 /* 3273 * VPID must not be zero, except for "all contexts." 3274 */ 3275 for (type = 0; type < 4; type++) 3276 if (types & (1u << type)) 3277 try_invvpid(type, 0, 0); 3278 3279 /* 3280 * The gla operand is only validated for single-address INVVPID. 3281 */ 3282 if (types & (1u << INVVPID_ADDR)) 3283 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3284 3285 invvpid_test_gp(); 3286 invvpid_test_ss(); 3287 invvpid_test_pf(); 3288 invvpid_test_compatibility_mode(); 3289 invvpid_test_not_in_vmx_operation(); 3290 } 3291 3292 /* 3293 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3294 * at least as far as the guest-state checks. Returns false if the 3295 * VMLAUNCH fails early and execution falls through to the next 3296 * instruction. 3297 */ 3298 static bool vmlaunch_succeeds(void) 3299 { 3300 u32 exit_reason; 3301 3302 /* 3303 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3304 * unsupported VMCS component"). The caller can then check 3305 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3306 */ 3307 vmcs_write(~0u, 0); 3308 3309 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3310 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3311 : 3312 : "r" ((u64)HOST_RSP) 3313 : "cc", "memory" 3314 : success); 3315 return false; 3316 success: 3317 exit_reason = vmcs_read(EXI_REASON); 3318 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3319 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3320 return true; 3321 } 3322 3323 /* 3324 * Try to launch the current VMCS. 3325 */ 3326 static void test_vmx_vmlaunch(u32 xerror, bool xfail) 3327 { 3328 bool success = vmlaunch_succeeds(); 3329 u32 vmx_inst_err; 3330 3331 report_xfail("vmlaunch %s", xfail, success == !xerror, 3332 !xerror ? "succeeds" : "fails"); 3333 if (!success && xerror) { 3334 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3335 report("VMX inst error is %d (actual %d)", 3336 vmx_inst_err == xerror, xerror, vmx_inst_err); 3337 } 3338 } 3339 3340 static void test_vmx_invalid_controls(bool xfail) 3341 { 3342 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD, xfail); 3343 } 3344 3345 static void test_vmx_valid_controls(bool xfail) 3346 { 3347 test_vmx_vmlaunch(0, xfail); 3348 } 3349 3350 /* 3351 * Test a particular value of a VM-execution control bit, if the value 3352 * is required or if the value is zero. 3353 */ 3354 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3355 enum Encoding encoding, unsigned bit, 3356 unsigned val) 3357 { 3358 u32 mask = 1u << bit; 3359 bool expected; 3360 u32 controls; 3361 3362 if (msr.set & mask) 3363 TEST_ASSERT(msr.clr & mask); 3364 3365 /* 3366 * We can't arbitrarily turn on a control bit, because it may 3367 * introduce dependencies on other VMCS fields. So, we only 3368 * test turning on bits that have a required setting. 3369 */ 3370 if (val && (msr.clr & mask) && !(msr.set & mask)) 3371 return; 3372 3373 report_prefix_pushf("%s %s bit %d", 3374 val ? "Set" : "Clear", name, bit); 3375 3376 controls = vmcs_read(encoding); 3377 if (val) { 3378 vmcs_write(encoding, msr.set | mask); 3379 expected = (msr.clr & mask); 3380 } else { 3381 vmcs_write(encoding, msr.set & ~mask); 3382 expected = !(msr.set & mask); 3383 } 3384 if (expected) 3385 test_vmx_valid_controls(false); 3386 else 3387 test_vmx_invalid_controls(false); 3388 vmcs_write(encoding, controls); 3389 report_prefix_pop(); 3390 } 3391 3392 /* 3393 * Test reserved values of a VM-execution control bit, based on the 3394 * allowed bit settings from the corresponding VMX capability MSR. 3395 */ 3396 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3397 enum Encoding encoding, unsigned bit) 3398 { 3399 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3400 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3401 } 3402 3403 /* 3404 * Reserved bits in the pin-based VM-execution controls must be set 3405 * properly. Software may consult the VMX capability MSRs to determine 3406 * the proper settings. 3407 * [Intel SDM] 3408 */ 3409 static void test_pin_based_ctls(void) 3410 { 3411 unsigned bit; 3412 3413 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3414 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3415 for (bit = 0; bit < 32; bit++) 3416 test_rsvd_ctl_bit("pin-based controls", 3417 ctrl_pin_rev, PIN_CONTROLS, bit); 3418 } 3419 3420 /* 3421 * Reserved bits in the primary processor-based VM-execution controls 3422 * must be set properly. Software may consult the VMX capability MSRs 3423 * to determine the proper settings. 3424 * [Intel SDM] 3425 */ 3426 static void test_primary_processor_based_ctls(void) 3427 { 3428 unsigned bit; 3429 3430 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3431 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3432 for (bit = 0; bit < 32; bit++) 3433 test_rsvd_ctl_bit("primary processor-based controls", 3434 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3435 } 3436 3437 /* 3438 * If the "activate secondary controls" primary processor-based 3439 * VM-execution control is 1, reserved bits in the secondary 3440 * processor-based VM-execution controls must be cleared. Software may 3441 * consult the VMX capability MSRs to determine which bits are 3442 * reserved. 3443 * If the "activate secondary controls" primary processor-based 3444 * VM-execution control is 0 (or if the processor does not support the 3445 * 1-setting of that control), no checks are performed on the 3446 * secondary processor-based VM-execution controls. 3447 * [Intel SDM] 3448 */ 3449 static void test_secondary_processor_based_ctls(void) 3450 { 3451 u32 primary; 3452 u32 secondary; 3453 unsigned bit; 3454 3455 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3456 return; 3457 3458 primary = vmcs_read(CPU_EXEC_CTRL0); 3459 secondary = vmcs_read(CPU_EXEC_CTRL1); 3460 3461 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3462 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3463 for (bit = 0; bit < 32; bit++) 3464 test_rsvd_ctl_bit("secondary processor-based controls", 3465 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3466 3467 /* 3468 * When the "activate secondary controls" VM-execution control 3469 * is clear, there are no checks on the secondary controls. 3470 */ 3471 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3472 vmcs_write(CPU_EXEC_CTRL1, ~0); 3473 report("Secondary processor-based controls ignored", 3474 vmlaunch_succeeds()); 3475 vmcs_write(CPU_EXEC_CTRL1, secondary); 3476 vmcs_write(CPU_EXEC_CTRL0, primary); 3477 } 3478 3479 static void try_cr3_target_count(unsigned i, unsigned max) 3480 { 3481 report_prefix_pushf("CR3 target count 0x%x", i); 3482 vmcs_write(CR3_TARGET_COUNT, i); 3483 if (i <= max) 3484 test_vmx_valid_controls(false); 3485 else 3486 test_vmx_invalid_controls(false); 3487 report_prefix_pop(); 3488 } 3489 3490 /* 3491 * The CR3-target count must not be greater than 4. Future processors 3492 * may support a different number of CR3-target values. Software 3493 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3494 * number of values supported. 3495 * [Intel SDM] 3496 */ 3497 static void test_cr3_targets(void) 3498 { 3499 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3500 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3501 unsigned i; 3502 3503 printf("\nSupported CR3 targets: %d\n", supported_targets); 3504 TEST_ASSERT(supported_targets <= 256); 3505 3506 try_cr3_target_count(-1u, supported_targets); 3507 try_cr3_target_count(0x80000000, supported_targets); 3508 try_cr3_target_count(0x7fffffff, supported_targets); 3509 for (i = 0; i <= supported_targets + 1; i++) 3510 try_cr3_target_count(i, supported_targets); 3511 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3512 } 3513 3514 /* 3515 * Test a particular address setting in the VMCS 3516 */ 3517 static void test_vmcs_addr(const char *name, 3518 enum Encoding encoding, 3519 u64 align, 3520 bool ignored, 3521 bool xfail_beyond_mapped_ram, 3522 u64 addr) 3523 { 3524 bool xfail = 3525 (xfail_beyond_mapped_ram && 3526 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3527 addr < (1ul << cpuid_maxphyaddr())); 3528 3529 report_prefix_pushf("%s = %lx", name, addr); 3530 vmcs_write(encoding, addr); 3531 if (ignored || (IS_ALIGNED(addr, align) && 3532 addr < (1ul << cpuid_maxphyaddr()))) 3533 test_vmx_valid_controls(xfail); 3534 else 3535 test_vmx_invalid_controls(xfail); 3536 report_prefix_pop(); 3537 xfail = false; 3538 } 3539 3540 /* 3541 * Test interesting values for a VMCS address 3542 */ 3543 static void test_vmcs_addr_values(const char *name, 3544 enum Encoding encoding, 3545 u64 align, 3546 bool ignored, 3547 bool xfail_beyond_mapped_ram, 3548 u32 bit_start, u32 bit_end) 3549 { 3550 unsigned i; 3551 u64 orig_val = vmcs_read(encoding); 3552 3553 for (i = bit_start; i <= bit_end; i++) 3554 test_vmcs_addr(name, encoding, align, ignored, 3555 xfail_beyond_mapped_ram, 1ul << i); 3556 3557 test_vmcs_addr(name, encoding, align, ignored, 3558 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3559 test_vmcs_addr(name, encoding, align, ignored, 3560 xfail_beyond_mapped_ram, PAGE_SIZE); 3561 test_vmcs_addr(name, encoding, align, ignored, 3562 xfail_beyond_mapped_ram, 3563 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3564 test_vmcs_addr(name, encoding, align, ignored, 3565 xfail_beyond_mapped_ram, -1ul); 3566 3567 vmcs_write(encoding, orig_val); 3568 } 3569 3570 /* 3571 * Test a physical address reference in the VMCS, when the corresponding 3572 * feature is enabled and when the corresponding feature is disabled. 3573 */ 3574 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3575 const char *field_name, 3576 const char *control_name, u64 align, 3577 bool xfail_beyond_mapped_ram, 3578 bool control_primary) 3579 { 3580 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3581 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3582 u64 page_addr; 3583 3584 if (control_primary) { 3585 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3586 return; 3587 } else { 3588 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3589 return; 3590 } 3591 3592 page_addr = vmcs_read(field); 3593 3594 report_prefix_pushf("%s enabled", control_name); 3595 if (control_primary) { 3596 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3597 } else { 3598 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3599 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3600 } 3601 3602 test_vmcs_addr_values(field_name, field, align, false, 3603 xfail_beyond_mapped_ram, 0, 63); 3604 report_prefix_pop(); 3605 3606 report_prefix_pushf("%s disabled", control_name); 3607 if (control_primary) { 3608 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3609 } else { 3610 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3611 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3612 } 3613 3614 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3615 report_prefix_pop(); 3616 3617 vmcs_write(field, page_addr); 3618 vmcs_write(CPU_EXEC_CTRL0, primary); 3619 vmcs_write(CPU_EXEC_CTRL1, secondary); 3620 } 3621 3622 /* 3623 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3624 * each I/O-bitmap address must be 0. Neither address should set any 3625 * bits beyond the processor's physical-address width. 3626 * [Intel SDM] 3627 */ 3628 static void test_io_bitmaps(void) 3629 { 3630 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3631 "I/O bitmap A", "Use I/O bitmaps", 3632 PAGE_SIZE, false, true); 3633 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3634 "I/O bitmap B", "Use I/O bitmaps", 3635 PAGE_SIZE, false, true); 3636 } 3637 3638 /* 3639 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3640 * the MSR-bitmap address must be 0. The address should not set any 3641 * bits beyond the processor's physical-address width. 3642 * [Intel SDM] 3643 */ 3644 static void test_msr_bitmap(void) 3645 { 3646 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3647 "MSR bitmap", "Use MSR bitmaps", 3648 PAGE_SIZE, false, true); 3649 } 3650 3651 /* 3652 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3653 * address must satisfy the following checks: 3654 * - Bits 11:0 of the address must be 0. 3655 * - The address should not set any bits beyond the processor's 3656 * physical-address width. 3657 * [Intel SDM] 3658 */ 3659 static void test_apic_virt_addr(void) 3660 { 3661 /* 3662 * Ensure the processor will never use the virtual-APIC page, since 3663 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3664 * what we're trying to achieve and fails vmentry. 3665 */ 3666 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3667 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3668 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3669 "virtual-APIC address", "Use TPR shadow", 3670 PAGE_SIZE, false, true); 3671 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3672 } 3673 3674 /* 3675 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3676 * APIC-access address must satisfy the following checks: 3677 * - Bits 11:0 of the address must be 0. 3678 * - The address should not set any bits beyond the processor's 3679 * physical-address width. 3680 * [Intel SDM] 3681 */ 3682 static void test_apic_access_addr(void) 3683 { 3684 void *apic_access_page = alloc_page(); 3685 3686 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3687 3688 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3689 "APIC-access address", 3690 "virtualize APIC-accesses", PAGE_SIZE, 3691 false, false); 3692 } 3693 3694 static bool set_bit_pattern(u8 mask, u32 *secondary) 3695 { 3696 u8 i; 3697 bool flag = false; 3698 u32 test_bits[3] = { 3699 CPU_VIRT_X2APIC, 3700 CPU_APIC_REG_VIRT, 3701 CPU_VINTD 3702 }; 3703 3704 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3705 if ((mask & (1u << i)) && 3706 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3707 *secondary |= test_bits[i]; 3708 flag = true; 3709 } 3710 } 3711 3712 return (flag); 3713 } 3714 3715 /* 3716 * If the "use TPR shadow" VM-execution control is 0, the following 3717 * VM-execution controls must also be 0: 3718 * - virtualize x2APIC mode 3719 * - APIC-register virtualization 3720 * - virtual-interrupt delivery 3721 * [Intel SDM] 3722 * 3723 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3724 * "virtualize APIC accesses" VM-execution control must be 0. 3725 * [Intel SDM] 3726 */ 3727 static void test_apic_virtual_ctls(void) 3728 { 3729 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3730 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3731 u32 primary = saved_primary; 3732 u32 secondary = saved_secondary; 3733 bool ctrl = false; 3734 char str[10] = "disabled"; 3735 u8 i = 0, j; 3736 3737 /* 3738 * First test 3739 */ 3740 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3741 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3742 return; 3743 3744 primary |= CPU_SECONDARY; 3745 primary &= ~CPU_TPR_SHADOW; 3746 vmcs_write(CPU_EXEC_CTRL0, primary); 3747 3748 while (1) { 3749 for (j = 1; j < 8; j++) { 3750 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3751 if (primary & CPU_TPR_SHADOW) { 3752 ctrl = true; 3753 } else { 3754 if (! set_bit_pattern(j, &secondary)) 3755 ctrl = true; 3756 else 3757 ctrl = false; 3758 } 3759 3760 vmcs_write(CPU_EXEC_CTRL1, secondary); 3761 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3762 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3763 if (ctrl) 3764 test_vmx_valid_controls(false); 3765 else 3766 test_vmx_invalid_controls(false); 3767 report_prefix_pop(); 3768 } 3769 3770 if (i == 1) 3771 break; 3772 i++; 3773 3774 primary |= CPU_TPR_SHADOW; 3775 vmcs_write(CPU_EXEC_CTRL0, primary); 3776 strcpy(str, "enabled"); 3777 } 3778 3779 /* 3780 * Second test 3781 */ 3782 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3783 3784 primary = saved_primary; 3785 secondary = saved_secondary; 3786 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3787 return; 3788 3789 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3790 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3791 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3792 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3793 test_vmx_valid_controls(false); 3794 report_prefix_pop(); 3795 3796 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3797 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3798 test_vmx_valid_controls(false); 3799 report_prefix_pop(); 3800 3801 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3802 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3803 test_vmx_invalid_controls(false); 3804 report_prefix_pop(); 3805 3806 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3807 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3808 test_vmx_valid_controls(false); 3809 report_prefix_pop(); 3810 3811 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3812 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3813 } 3814 3815 /* 3816 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3817 * "external-interrupt exiting" VM-execution control must be 1. 3818 * [Intel SDM] 3819 */ 3820 static void test_virtual_intr_ctls(void) 3821 { 3822 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3823 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3824 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3825 u32 primary = saved_primary; 3826 u32 secondary = saved_secondary; 3827 u32 pin = saved_pin; 3828 3829 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3830 (ctrl_pin_rev.clr & PIN_EXTINT))) 3831 return; 3832 3833 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3834 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3835 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3836 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3837 test_vmx_valid_controls(false); 3838 report_prefix_pop(); 3839 3840 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3841 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3842 test_vmx_invalid_controls(false); 3843 report_prefix_pop(); 3844 3845 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3846 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3847 test_vmx_valid_controls(false); 3848 report_prefix_pop(); 3849 3850 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3851 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3852 test_vmx_invalid_controls(false); 3853 report_prefix_pop(); 3854 3855 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3856 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3857 vmcs_write(PIN_CONTROLS, saved_pin); 3858 } 3859 3860 static void test_pi_desc_addr(u64 addr, bool ctrl) 3861 { 3862 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3863 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3864 if (ctrl) 3865 test_vmx_valid_controls(false); 3866 else 3867 test_vmx_invalid_controls(false); 3868 report_prefix_pop(); 3869 } 3870 3871 /* 3872 * If the “process posted interrupts†VM-execution control is 1, the 3873 * following must be true: 3874 * 3875 * - The “virtual-interrupt delivery†VM-execution control is 1. 3876 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3877 * - The posted-interrupt notification vector has a value in the 3878 * - range 0–255 (bits 15:8 are all 0). 3879 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3880 * - The posted-interrupt descriptor address does not set any bits 3881 * beyond the processor's physical-address width. 3882 * [Intel SDM] 3883 */ 3884 static void test_posted_intr(void) 3885 { 3886 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3887 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3888 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3889 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3890 u32 primary = saved_primary; 3891 u32 secondary = saved_secondary; 3892 u32 pin = saved_pin; 3893 u32 exit_ctl = exit_ctl_saved; 3894 u16 vec; 3895 int i; 3896 3897 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3898 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3899 (ctrl_exit_rev.clr & EXI_INTA))) 3900 return; 3901 3902 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3903 3904 /* 3905 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3906 */ 3907 pin |= PIN_POST_INTR; 3908 vmcs_write(PIN_CONTROLS, pin); 3909 secondary &= ~CPU_VINTD; 3910 vmcs_write(CPU_EXEC_CTRL1, secondary); 3911 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3912 test_vmx_invalid_controls(false); 3913 report_prefix_pop(); 3914 3915 secondary |= CPU_VINTD; 3916 vmcs_write(CPU_EXEC_CTRL1, secondary); 3917 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3918 test_vmx_invalid_controls(false); 3919 report_prefix_pop(); 3920 3921 exit_ctl &= ~EXI_INTA; 3922 vmcs_write(EXI_CONTROLS, exit_ctl); 3923 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3924 test_vmx_invalid_controls(false); 3925 report_prefix_pop(); 3926 3927 exit_ctl |= EXI_INTA; 3928 vmcs_write(EXI_CONTROLS, exit_ctl); 3929 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3930 test_vmx_valid_controls(false); 3931 report_prefix_pop(); 3932 3933 secondary &= ~CPU_VINTD; 3934 vmcs_write(CPU_EXEC_CTRL1, secondary); 3935 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3936 test_vmx_invalid_controls(false); 3937 report_prefix_pop(); 3938 3939 secondary |= CPU_VINTD; 3940 vmcs_write(CPU_EXEC_CTRL1, secondary); 3941 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3942 test_vmx_valid_controls(false); 3943 report_prefix_pop(); 3944 3945 /* 3946 * Test posted-interrupt notification vector 3947 */ 3948 for (i = 0; i < 8; i++) { 3949 vec = (1ul << i); 3950 vmcs_write(PINV, vec); 3951 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3952 test_vmx_valid_controls(false); 3953 report_prefix_pop(); 3954 } 3955 for (i = 8; i < 16; i++) { 3956 vec = (1ul << i); 3957 vmcs_write(PINV, vec); 3958 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3959 test_vmx_invalid_controls(false); 3960 report_prefix_pop(); 3961 } 3962 3963 vec &= ~(0xff << 8); 3964 vmcs_write(PINV, vec); 3965 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3966 test_vmx_valid_controls(false); 3967 report_prefix_pop(); 3968 3969 /* 3970 * Test posted-interrupt descriptor addresss 3971 */ 3972 for (i = 0; i < 6; i++) { 3973 test_pi_desc_addr(1ul << i, false); 3974 } 3975 3976 test_pi_desc_addr(0xf0, false); 3977 test_pi_desc_addr(0xff, false); 3978 test_pi_desc_addr(0x0f, false); 3979 test_pi_desc_addr(0x8000, true); 3980 test_pi_desc_addr(0x00, true); 3981 test_pi_desc_addr(0xc000, true); 3982 3983 test_vmcs_addr_values("process-posted interrupts", 3984 POSTED_INTR_DESC_ADDR, 64, 3985 false, false, 0, 63); 3986 3987 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3988 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3989 vmcs_write(PIN_CONTROLS, saved_pin); 3990 } 3991 3992 static void test_apic_ctls(void) 3993 { 3994 test_apic_virt_addr(); 3995 test_apic_access_addr(); 3996 test_apic_virtual_ctls(); 3997 test_virtual_intr_ctls(); 3998 test_posted_intr(); 3999 } 4000 4001 /* 4002 * If the “enable VPID†VM-execution control is 1, the value of the 4003 * of the VPID VM-execution control field must not be 0000H. 4004 * [Intel SDM] 4005 */ 4006 static void test_vpid(void) 4007 { 4008 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4009 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4010 u16 vpid = 0x0000; 4011 int i; 4012 4013 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4014 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4015 test_skip("Secondary controls and/or VPID not supported"); 4016 return; 4017 } 4018 4019 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4020 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4021 vmcs_write(VPID, vpid); 4022 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4023 test_vmx_valid_controls(false); 4024 report_prefix_pop(); 4025 4026 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4027 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4028 test_vmx_invalid_controls(false); 4029 report_prefix_pop(); 4030 4031 for (i = 0; i < 16; i++) { 4032 vpid = (short)1 << i;; 4033 vmcs_write(VPID, vpid); 4034 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4035 test_vmx_valid_controls(false); 4036 report_prefix_pop(); 4037 } 4038 4039 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4040 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4041 } 4042 4043 static void set_vtpr(unsigned vtpr) 4044 { 4045 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4046 } 4047 4048 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4049 { 4050 bool valid = true; 4051 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4052 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4053 4054 if ((primary & CPU_TPR_SHADOW) && 4055 (!(primary & CPU_SECONDARY) || 4056 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4057 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4058 4059 set_vtpr(vtpr); 4060 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4061 threshold, (vtpr >> 4) & 0xf); 4062 if (valid) 4063 test_vmx_valid_controls(false); 4064 else 4065 test_vmx_invalid_controls(false); 4066 report_prefix_pop(); 4067 } 4068 4069 static void test_invalid_event_injection(void) 4070 { 4071 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4072 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4073 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4074 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4075 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4076 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4077 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4078 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4079 u32 cnt; 4080 4081 /* Setup */ 4082 report_prefix_push("invalid event injection"); 4083 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4084 vmcs_write(ENT_INST_LEN, 0x00000001); 4085 4086 /* The field’s interruption type is not set to a reserved value. */ 4087 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4088 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4089 "RESERVED interruption type invalid [-]", 4090 ent_intr_info); 4091 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4092 test_vmx_invalid_controls(false); 4093 report_prefix_pop(); 4094 4095 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4096 DE_VECTOR; 4097 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4098 "RESERVED interruption type invalid [+]", 4099 ent_intr_info); 4100 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4101 test_vmx_valid_controls(false); 4102 report_prefix_pop(); 4103 4104 /* If the interruption type is other event, the vector is 0. */ 4105 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4106 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4107 "(OTHER EVENT && vector != 0) invalid [-]", 4108 ent_intr_info); 4109 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4110 test_vmx_invalid_controls(false); 4111 report_prefix_pop(); 4112 4113 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4114 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4115 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4116 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4117 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4118 test_vmx_invalid_controls(false); 4119 report_prefix_pop(); 4120 4121 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4122 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4123 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4124 "(NMI && vector == 2) valid [+]", ent_intr_info); 4125 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4126 test_vmx_valid_controls(false); 4127 report_prefix_pop(); 4128 4129 /* 4130 * If the interruption type 4131 * is HW exception, the vector is at most 31. 4132 */ 4133 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4134 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4135 "(HW exception && vector > 31) invalid [-]", 4136 ent_intr_info); 4137 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4138 test_vmx_invalid_controls(false); 4139 report_prefix_pop(); 4140 4141 /* 4142 * deliver-error-code is 1 iff either 4143 * (a) the "unrestricted guest" VM-execution control is 0 4144 * (b) CR0.PE is set. 4145 */ 4146 4147 /* Assert that unrestricted guest is disabled or unsupported */ 4148 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4149 !(secondary_save & CPU_URG)); 4150 4151 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4152 GP_VECTOR; 4153 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4154 "error code <-> (!URG || prot_mode) [-]", 4155 ent_intr_info); 4156 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4157 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4158 test_vmx_invalid_controls(false); 4159 report_prefix_pop(); 4160 4161 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4162 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4163 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4164 "error code <-> (!URG || prot_mode) [+]", 4165 ent_intr_info); 4166 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4167 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4168 test_vmx_valid_controls(false); 4169 report_prefix_pop(); 4170 4171 if (enable_unrestricted_guest()) 4172 goto skip_unrestricted_guest; 4173 4174 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4175 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4176 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4177 "error code <-> (!URG || prot_mode) [-]", 4178 ent_intr_info); 4179 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4180 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4181 test_vmx_invalid_controls(false); 4182 report_prefix_pop(); 4183 4184 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4185 GP_VECTOR; 4186 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4187 "error code <-> (!URG || prot_mode) [-]", 4188 ent_intr_info); 4189 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4190 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4191 test_vmx_invalid_controls(false); 4192 report_prefix_pop(); 4193 4194 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4195 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4196 4197 skip_unrestricted_guest: 4198 vmcs_write(GUEST_CR0, guest_cr0_save); 4199 4200 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4201 report_prefix_push("error code <-> HW exception"); 4202 for (cnt = 0; cnt < 8; cnt++) { 4203 u32 exception_type_mask = cnt << 8; 4204 u32 deliver_error_code_mask = 4205 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4206 INTR_INFO_DELIVER_CODE_MASK : 0; 4207 4208 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4209 exception_type_mask | GP_VECTOR; 4210 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4211 ent_intr_info); 4212 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4213 test_vmx_invalid_controls(false); 4214 report_prefix_pop(); 4215 } 4216 report_prefix_pop(); 4217 4218 /* 4219 * deliver-error-code is 1 iff the the vector 4220 * indicates an exception that would normally deliver an error code 4221 */ 4222 report_prefix_push("error code <-> vector delivers error code"); 4223 for (cnt = 0; cnt < 32; cnt++) { 4224 bool has_error_code = false; 4225 u32 deliver_error_code_mask; 4226 4227 switch (cnt) { 4228 case DF_VECTOR: 4229 case TS_VECTOR: 4230 case NP_VECTOR: 4231 case SS_VECTOR: 4232 case GP_VECTOR: 4233 case PF_VECTOR: 4234 case AC_VECTOR: 4235 has_error_code = true; 4236 } 4237 4238 /* Negative case */ 4239 deliver_error_code_mask = has_error_code ? 4240 0 : 4241 INTR_INFO_DELIVER_CODE_MASK; 4242 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4243 INTR_TYPE_HARD_EXCEPTION | cnt; 4244 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4245 ent_intr_info); 4246 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4247 test_vmx_invalid_controls(false); 4248 report_prefix_pop(); 4249 4250 /* Positive case */ 4251 deliver_error_code_mask = has_error_code ? 4252 INTR_INFO_DELIVER_CODE_MASK : 4253 0; 4254 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4255 INTR_TYPE_HARD_EXCEPTION | cnt; 4256 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4257 ent_intr_info); 4258 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4259 test_vmx_valid_controls(false); 4260 report_prefix_pop(); 4261 } 4262 report_prefix_pop(); 4263 4264 /* Reserved bits in the field (30:12) are 0. */ 4265 report_prefix_push("reserved bits clear"); 4266 for (cnt = 12; cnt <= 30; cnt++) { 4267 ent_intr_info = ent_intr_info_base | 4268 INTR_INFO_DELIVER_CODE_MASK | 4269 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4270 (1U << cnt); 4271 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4272 ent_intr_info); 4273 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4274 test_vmx_invalid_controls(false); 4275 report_prefix_pop(); 4276 } 4277 report_prefix_pop(); 4278 4279 /* 4280 * If deliver-error-code is 1 4281 * bits 31:15 of the VM-entry exception error-code field are 0. 4282 */ 4283 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4284 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4285 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4286 "VM-entry exception error code[31:15] clear", 4287 ent_intr_info); 4288 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4289 for (cnt = 15; cnt <= 31; cnt++) { 4290 ent_intr_err = 1U << cnt; 4291 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4292 ent_intr_err); 4293 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4294 test_vmx_invalid_controls(false); 4295 report_prefix_pop(); 4296 } 4297 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4298 report_prefix_pop(); 4299 4300 /* 4301 * If the interruption type is software interrupt, software exception, 4302 * or privileged software exception, the VM-entry instruction-length 4303 * field is in the range 0–15. 4304 */ 4305 4306 for (cnt = 0; cnt < 3; cnt++) { 4307 switch (cnt) { 4308 case 0: 4309 ent_intr_info = ent_intr_info_base | 4310 INTR_TYPE_SOFT_INTR; 4311 break; 4312 case 1: 4313 ent_intr_info = ent_intr_info_base | 4314 INTR_TYPE_SOFT_EXCEPTION; 4315 break; 4316 case 2: 4317 ent_intr_info = ent_intr_info_base | 4318 INTR_TYPE_PRIV_SW_EXCEPTION; 4319 break; 4320 } 4321 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4322 "VM-entry instruction-length check", 4323 ent_intr_info); 4324 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4325 4326 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4327 ent_intr_len = -1; 4328 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4329 ent_intr_len); 4330 vmcs_write(ENT_INST_LEN, ent_intr_len); 4331 test_vmx_invalid_controls(false); 4332 report_prefix_pop(); 4333 4334 /* Instruction length set to 16 should fail */ 4335 ent_intr_len = 0x00000010; 4336 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4337 ent_intr_len); 4338 vmcs_write(ENT_INST_LEN, 0x00000010); 4339 test_vmx_invalid_controls(false); 4340 report_prefix_pop(); 4341 4342 report_prefix_pop(); 4343 } 4344 4345 /* Cleanup */ 4346 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4347 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4348 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4349 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4350 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4351 vmcs_write(GUEST_CR0, guest_cr0_save); 4352 report_prefix_pop(); 4353 } 4354 4355 /* 4356 * Test interesting vTPR values for a given TPR threshold. 4357 */ 4358 static void test_vtpr_values(unsigned threshold) 4359 { 4360 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4361 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4362 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4363 } 4364 4365 static void try_tpr_threshold(unsigned threshold) 4366 { 4367 bool valid = true; 4368 4369 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4370 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4371 4372 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4373 (secondary & CPU_VINTD))) 4374 valid = !(threshold >> 4); 4375 4376 set_vtpr(-1); 4377 vmcs_write(TPR_THRESHOLD, threshold); 4378 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4379 if (valid) 4380 test_vmx_valid_controls(false); 4381 else 4382 test_vmx_invalid_controls(false); 4383 report_prefix_pop(); 4384 4385 if (valid) 4386 test_vtpr_values(threshold); 4387 } 4388 4389 /* 4390 * Test interesting TPR threshold values. 4391 */ 4392 static void test_tpr_threshold_values(void) 4393 { 4394 unsigned i; 4395 4396 for (i = 0; i < 0x10; i++) 4397 try_tpr_threshold(i); 4398 for (i = 4; i < 32; i++) 4399 try_tpr_threshold(1u << i); 4400 try_tpr_threshold(-1u); 4401 try_tpr_threshold(0x7fffffff); 4402 } 4403 4404 /* 4405 * This test covers the following two VM entry checks: 4406 * 4407 * i) If the "use TPR shadow" VM-execution control is 1 and the 4408 * "virtual-interrupt delivery" VM-execution control is 0, bits 4409 * 31:4 of the TPR threshold VM-execution control field must 4410 be 0. 4411 * [Intel SDM] 4412 * 4413 * ii) If the "use TPR shadow" VM-execution control is 1, the 4414 * "virtual-interrupt delivery" VM-execution control is 0 4415 * and the "virtualize APIC accesses" VM-execution control 4416 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4417 * control field must not be greater than the value of bits 4418 * 7:4 of VTPR. 4419 * [Intel SDM] 4420 */ 4421 static void test_tpr_threshold(void) 4422 { 4423 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4424 void *virtual_apic_page; 4425 4426 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4427 return; 4428 4429 virtual_apic_page = alloc_page(); 4430 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4431 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4432 4433 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4434 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4435 test_tpr_threshold_values(); 4436 report_prefix_pop(); 4437 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4438 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4439 test_tpr_threshold_values(); 4440 report_prefix_pop(); 4441 4442 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4443 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4444 vmcs_write(CPU_EXEC_CTRL0, primary); 4445 return; 4446 } 4447 4448 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4449 4450 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4451 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4452 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4453 test_tpr_threshold_values(); 4454 report_prefix_pop(); 4455 4456 vmcs_write(CPU_EXEC_CTRL0, 4457 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4458 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4459 test_tpr_threshold_values(); 4460 report_prefix_pop(); 4461 } 4462 4463 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4464 vmcs_write(CPU_EXEC_CTRL0, 4465 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4466 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4467 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4468 test_tpr_threshold_values(); 4469 report_prefix_pop(); 4470 4471 vmcs_write(CPU_EXEC_CTRL0, 4472 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4473 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4474 test_tpr_threshold_values(); 4475 report_prefix_pop(); 4476 } 4477 4478 if ((ctrl_cpu_rev[1].clr & 4479 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4480 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4481 vmcs_write(CPU_EXEC_CTRL0, 4482 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4483 vmcs_write(CPU_EXEC_CTRL1, 4484 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4485 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4486 test_tpr_threshold_values(); 4487 report_prefix_pop(); 4488 4489 vmcs_write(CPU_EXEC_CTRL0, 4490 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4491 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4492 test_tpr_threshold_values(); 4493 report_prefix_pop(); 4494 } 4495 4496 vmcs_write(CPU_EXEC_CTRL1, secondary); 4497 vmcs_write(CPU_EXEC_CTRL0, primary); 4498 } 4499 4500 /* 4501 * This test verifies the following two vmentry checks: 4502 * 4503 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4504 * VM-execution control must be 0. 4505 * [Intel SDM] 4506 * 4507 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4508 * exiting” VM-execution control must be 0. 4509 * [Intel SDM] 4510 */ 4511 static void test_nmi_ctrls(void) 4512 { 4513 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4514 4515 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4516 (PIN_NMI | PIN_VIRT_NMI)) { 4517 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4518 return; 4519 } 4520 4521 /* Save the controls so that we can restore them after our tests */ 4522 pin_ctrls = vmcs_read(PIN_CONTROLS); 4523 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4524 4525 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4526 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4527 4528 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4529 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4530 test_vmx_valid_controls(false); 4531 report_prefix_pop(); 4532 4533 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4534 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4535 test_vmx_invalid_controls(false); 4536 report_prefix_pop(); 4537 4538 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4539 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4540 test_vmx_valid_controls(false); 4541 report_prefix_pop(); 4542 4543 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4544 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4545 test_vmx_valid_controls(false); 4546 report_prefix_pop(); 4547 4548 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4549 report_info("NMI-window exiting is not supported, skipping..."); 4550 goto done; 4551 } 4552 4553 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4554 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4555 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4556 test_vmx_invalid_controls(false); 4557 report_prefix_pop(); 4558 4559 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4560 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4561 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4562 test_vmx_valid_controls(false); 4563 report_prefix_pop(); 4564 4565 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4566 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4567 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4568 test_vmx_valid_controls(false); 4569 report_prefix_pop(); 4570 4571 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4572 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4573 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4574 test_vmx_valid_controls(false); 4575 report_prefix_pop(); 4576 4577 /* Restore the controls to their original values */ 4578 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4579 done: 4580 vmcs_write(PIN_CONTROLS, pin_ctrls); 4581 } 4582 4583 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4584 { 4585 vmcs_write(EPTP, eptp); 4586 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4587 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4588 if (ctrl) 4589 test_vmx_valid_controls(false); 4590 else 4591 test_vmx_invalid_controls(false); 4592 report_prefix_pop(); 4593 4594 } 4595 4596 /* 4597 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4598 * control field must satisfy the following checks: 4599 * 4600 * - The EPT memory type (bits 2:0) must be a value supported by the 4601 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4602 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4603 * indicating an EPT page-walk length of 4. 4604 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4605 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4606 * indicating that the processor does not support accessed and dirty 4607 * dirty flags for EPT. 4608 * - Reserved bits 11:7 and 63:N (where N is the processor's 4609 * physical-address width) must all be 0. 4610 * 4611 * 2. If the "unrestricted guest" VM-execution control is 1, the 4612 * "enable EPT" VM-execution control must also be 1. 4613 */ 4614 static void test_ept_eptp(void) 4615 { 4616 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4617 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4618 u64 eptp_saved = vmcs_read(EPTP); 4619 u32 primary = primary_saved; 4620 u32 secondary = secondary_saved; 4621 u64 msr, eptp = eptp_saved; 4622 bool un_cache = false; 4623 bool wr_bk = false; 4624 bool ctrl; 4625 u32 i, maxphysaddr; 4626 u64 j, resv_bits_mask = 0; 4627 4628 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4629 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4630 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4631 return; 4632 } 4633 4634 /* 4635 * Memory type (bits 2:0) 4636 */ 4637 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4638 if (msr & EPT_CAP_UC) 4639 un_cache = true; 4640 if (msr & EPT_CAP_WB) 4641 wr_bk = true; 4642 4643 primary |= CPU_SECONDARY; 4644 vmcs_write(CPU_EXEC_CTRL0, primary); 4645 secondary |= CPU_EPT; 4646 vmcs_write(CPU_EXEC_CTRL1, secondary); 4647 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4648 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4649 vmcs_write(EPTP, eptp); 4650 4651 for (i = 0; i < 8; i++) { 4652 if (i == 0) { 4653 if (un_cache) { 4654 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4655 ctrl = true; 4656 } else { 4657 ctrl = false; 4658 } 4659 } else if (i == 6) { 4660 if (wr_bk) { 4661 report_info("EPT paging structure memory-type is Write-back\n"); 4662 ctrl = true; 4663 } else { 4664 ctrl = false; 4665 } 4666 } else { 4667 ctrl = false; 4668 } 4669 4670 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4671 vmcs_write(EPTP, eptp); 4672 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4673 eptp & EPT_MEM_TYPE_MASK); 4674 if (ctrl) 4675 test_vmx_valid_controls(false); 4676 else 4677 test_vmx_invalid_controls(false); 4678 report_prefix_pop(); 4679 } 4680 4681 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4682 4683 /* 4684 * Page walk length (bits 5:3) 4685 */ 4686 for (i = 0; i < 8; i++) { 4687 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4688 (i << EPTP_PG_WALK_LEN_SHIFT); 4689 if (i == 3) 4690 ctrl = true; 4691 else 4692 ctrl = false; 4693 4694 vmcs_write(EPTP, eptp); 4695 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4696 eptp & EPTP_PG_WALK_LEN_MASK); 4697 if (ctrl) 4698 test_vmx_valid_controls(false); 4699 else 4700 test_vmx_invalid_controls(false); 4701 report_prefix_pop(); 4702 } 4703 4704 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4705 3ul << EPTP_PG_WALK_LEN_SHIFT; 4706 4707 /* 4708 * Accessed and dirty flag (bit 6) 4709 */ 4710 if (msr & EPT_CAP_AD_FLAG) { 4711 report_info("Processor supports accessed and dirty flag"); 4712 eptp &= ~EPTP_AD_FLAG; 4713 test_eptp_ad_bit(eptp, true); 4714 4715 eptp |= EPTP_AD_FLAG; 4716 test_eptp_ad_bit(eptp, true); 4717 } else { 4718 report_info("Processor does not supports accessed and dirty flag"); 4719 eptp &= ~EPTP_AD_FLAG; 4720 test_eptp_ad_bit(eptp, true); 4721 4722 eptp |= EPTP_AD_FLAG; 4723 test_eptp_ad_bit(eptp, false); 4724 } 4725 4726 /* 4727 * Reserved bits [11:7] and [63:N] 4728 */ 4729 for (i = 0; i < 32; i++) { 4730 eptp = (eptp & 4731 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4732 (i << EPTP_RESERV_BITS_SHIFT); 4733 vmcs_write(EPTP, eptp); 4734 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4735 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4736 EPTP_RESERV_BITS_MASK); 4737 if (i == 0) 4738 test_vmx_valid_controls(false); 4739 else 4740 test_vmx_invalid_controls(false); 4741 report_prefix_pop(); 4742 } 4743 4744 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4745 4746 maxphysaddr = cpuid_maxphyaddr(); 4747 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4748 resv_bits_mask |= 1ul << i; 4749 } 4750 4751 for (j = maxphysaddr - 1; j <= 63; j++) { 4752 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4753 (j < maxphysaddr ? 0 : 1ul << j); 4754 vmcs_write(EPTP, eptp); 4755 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4756 (eptp >> maxphysaddr) & resv_bits_mask); 4757 if (j < maxphysaddr) 4758 test_vmx_valid_controls(false); 4759 else 4760 test_vmx_invalid_controls(false); 4761 report_prefix_pop(); 4762 } 4763 4764 secondary &= ~(CPU_EPT | CPU_URG); 4765 vmcs_write(CPU_EXEC_CTRL1, secondary); 4766 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4767 test_vmx_valid_controls(false); 4768 report_prefix_pop(); 4769 4770 secondary |= CPU_URG; 4771 vmcs_write(CPU_EXEC_CTRL1, secondary); 4772 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4773 test_vmx_invalid_controls(false); 4774 report_prefix_pop(); 4775 4776 secondary |= CPU_EPT; 4777 setup_dummy_ept(); 4778 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4779 test_vmx_valid_controls(false); 4780 report_prefix_pop(); 4781 4782 secondary &= ~CPU_URG; 4783 vmcs_write(CPU_EXEC_CTRL1, secondary); 4784 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4785 test_vmx_valid_controls(false); 4786 report_prefix_pop(); 4787 4788 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4789 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4790 vmcs_write(EPTP, eptp_saved); 4791 } 4792 4793 /* 4794 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4795 * VM-execution control must also be 1. In addition, the PML address 4796 * must satisfy the following checks: 4797 * 4798 * * Bits 11:0 of the address must be 0. 4799 * * The address should not set any bits beyond the processor's 4800 * physical-address width. 4801 * 4802 * [Intel SDM] 4803 */ 4804 static void test_pml(void) 4805 { 4806 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4807 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4808 u32 primary = primary_saved; 4809 u32 secondary = secondary_saved; 4810 4811 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4812 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4813 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4814 return; 4815 } 4816 4817 primary |= CPU_SECONDARY; 4818 vmcs_write(CPU_EXEC_CTRL0, primary); 4819 secondary &= ~(CPU_PML | CPU_EPT); 4820 vmcs_write(CPU_EXEC_CTRL1, secondary); 4821 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4822 test_vmx_valid_controls(false); 4823 report_prefix_pop(); 4824 4825 secondary |= CPU_PML; 4826 vmcs_write(CPU_EXEC_CTRL1, secondary); 4827 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4828 test_vmx_invalid_controls(false); 4829 report_prefix_pop(); 4830 4831 secondary |= CPU_EPT; 4832 setup_dummy_ept(); 4833 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4834 test_vmx_valid_controls(false); 4835 report_prefix_pop(); 4836 4837 secondary &= ~CPU_PML; 4838 vmcs_write(CPU_EXEC_CTRL1, secondary); 4839 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4840 test_vmx_valid_controls(false); 4841 report_prefix_pop(); 4842 4843 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4844 PAGE_SIZE, false, false); 4845 4846 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4847 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4848 } 4849 4850 /* 4851 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4852 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4853 * 4854 * [Intel SDM] 4855 */ 4856 static void test_vmx_preemption_timer(void) 4857 { 4858 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4859 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4860 u32 pin = saved_pin; 4861 u32 exit = saved_exit; 4862 4863 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4864 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4865 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4866 return; 4867 } 4868 4869 pin |= PIN_PREEMPT; 4870 vmcs_write(PIN_CONTROLS, pin); 4871 exit &= ~EXI_SAVE_PREEMPT; 4872 vmcs_write(EXI_CONTROLS, exit); 4873 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4874 test_vmx_valid_controls(false); 4875 report_prefix_pop(); 4876 4877 exit |= EXI_SAVE_PREEMPT; 4878 vmcs_write(EXI_CONTROLS, exit); 4879 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4880 test_vmx_valid_controls(false); 4881 report_prefix_pop(); 4882 4883 pin &= ~PIN_PREEMPT; 4884 vmcs_write(PIN_CONTROLS, pin); 4885 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4886 test_vmx_invalid_controls(false); 4887 report_prefix_pop(); 4888 4889 exit &= ~EXI_SAVE_PREEMPT; 4890 vmcs_write(EXI_CONTROLS, exit); 4891 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4892 test_vmx_valid_controls(false); 4893 report_prefix_pop(); 4894 4895 vmcs_write(PIN_CONTROLS, saved_pin); 4896 vmcs_write(EXI_CONTROLS, saved_exit); 4897 } 4898 4899 /* 4900 * Tests for VM-execution control fields 4901 */ 4902 static void test_vm_execution_ctls(void) 4903 { 4904 test_pin_based_ctls(); 4905 test_primary_processor_based_ctls(); 4906 test_secondary_processor_based_ctls(); 4907 test_cr3_targets(); 4908 test_io_bitmaps(); 4909 test_msr_bitmap(); 4910 test_apic_ctls(); 4911 test_tpr_threshold(); 4912 test_nmi_ctrls(); 4913 test_pml(); 4914 test_vpid(); 4915 test_ept_eptp(); 4916 test_vmx_preemption_timer(); 4917 } 4918 4919 /* 4920 * The following checks are performed for the VM-entry MSR-load address if 4921 * the VM-entry MSR-load count field is non-zero: 4922 * 4923 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4924 * The address should not set any bits beyond the processor’s 4925 * physical-address width. 4926 * 4927 * - The address of the last byte in the VM-entry MSR-load area 4928 * should not set any bits beyond the processor’s physical-address 4929 * width. The address of this last byte is VM-entry MSR-load address 4930 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4931 * uses more bits than the processor’s physical-address width.) 4932 * 4933 * 4934 * [Intel SDM] 4935 */ 4936 static void test_entry_msr_load(void) 4937 { 4938 entry_msr_load = alloc_page(); 4939 u64 tmp; 4940 u32 entry_msr_ld_cnt = 1; 4941 int i; 4942 u32 addr_len = 64; 4943 4944 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4945 4946 /* Check first 4 bits of VM-entry MSR-load address */ 4947 for (i = 0; i < 4; i++) { 4948 tmp = (u64)entry_msr_load | 1ull << i; 4949 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4950 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4951 tmp & 0xf); 4952 test_vmx_invalid_controls(false); 4953 report_prefix_pop(); 4954 } 4955 4956 if (basic.val & (1ul << 48)) 4957 addr_len = 32; 4958 4959 test_vmcs_addr_values("VM-entry-MSR-load address", 4960 ENTER_MSR_LD_ADDR, 16, false, false, 4961 4, addr_len - 1); 4962 4963 /* 4964 * Check last byte of VM-entry MSR-load address 4965 */ 4966 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 4967 4968 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4969 i < 64; i++) { 4970 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 4971 1ul << i; 4972 vmcs_write(ENTER_MSR_LD_ADDR, 4973 tmp - (entry_msr_ld_cnt * 16 - 1)); 4974 test_vmx_invalid_controls(false); 4975 } 4976 4977 vmcs_write(ENT_MSR_LD_CNT, 2); 4978 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4979 test_vmx_invalid_controls(false); 4980 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4981 test_vmx_valid_controls(false); 4982 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4983 test_vmx_valid_controls(false); 4984 } 4985 4986 static void guest_pat_main(void) 4987 { 4988 while (1) { 4989 if (vmx_get_test_stage() != 2) 4990 vmcall(); 4991 else 4992 break; 4993 } 4994 4995 asm volatile("fnop"); 4996 } 4997 4998 static void report_guest_pat_test(const char *test, u32 xreason, u64 guest_pat) 4999 { 5000 u32 reason = vmcs_read(EXI_REASON); 5001 u64 guest_rip; 5002 u32 insn_len; 5003 5004 report("%s, GUEST_PAT %lx", reason == xreason, test, guest_pat); 5005 5006 guest_rip = vmcs_read(GUEST_RIP); 5007 insn_len = vmcs_read(EXI_INST_LEN); 5008 if (! (reason & 0x80000021)) 5009 vmcs_write(GUEST_RIP, guest_rip + insn_len); 5010 } 5011 5012 /* 5013 * Tests for VM-entry control fields 5014 */ 5015 static void test_vm_entry_ctls(void) 5016 { 5017 test_invalid_event_injection(); 5018 test_entry_msr_load(); 5019 } 5020 5021 /* 5022 * The following checks are performed for the VM-exit MSR-store address if 5023 * the VM-exit MSR-store count field is non-zero: 5024 * 5025 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5026 * The address should not set any bits beyond the processor’s 5027 * physical-address width. 5028 * 5029 * - The address of the last byte in the VM-exit MSR-store area 5030 * should not set any bits beyond the processor’s physical-address 5031 * width. The address of this last byte is VM-exit MSR-store address 5032 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5033 * uses more bits than the processor’s physical-address width.) 5034 * 5035 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5036 * in the range 63:32. 5037 * 5038 * [Intel SDM] 5039 */ 5040 static void test_exit_msr_store(void) 5041 { 5042 exit_msr_store = alloc_page(); 5043 u64 tmp; 5044 u32 exit_msr_st_cnt = 1; 5045 int i; 5046 u32 addr_len = 64; 5047 5048 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5049 5050 /* Check first 4 bits of VM-exit MSR-store address */ 5051 for (i = 0; i < 4; i++) { 5052 tmp = (u64)exit_msr_store | 1ull << i; 5053 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5054 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5055 tmp & 0xf); 5056 test_vmx_invalid_controls(false); 5057 report_prefix_pop(); 5058 } 5059 5060 if (basic.val & (1ul << 48)) 5061 addr_len = 32; 5062 5063 test_vmcs_addr_values("VM-exit-MSR-store address", 5064 EXIT_MSR_ST_ADDR, 16, false, false, 5065 4, addr_len - 1); 5066 5067 /* 5068 * Check last byte of VM-exit MSR-store address 5069 */ 5070 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5071 5072 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5073 i < 64; i++) { 5074 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5075 1ul << i; 5076 vmcs_write(EXIT_MSR_ST_ADDR, 5077 tmp - (exit_msr_st_cnt * 16 - 1)); 5078 test_vmx_invalid_controls(false); 5079 } 5080 5081 vmcs_write(EXI_MSR_ST_CNT, 2); 5082 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5083 test_vmx_invalid_controls(false); 5084 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5085 test_vmx_valid_controls(false); 5086 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5087 test_vmx_valid_controls(false); 5088 } 5089 5090 /* 5091 * Tests for VM-exit controls 5092 */ 5093 static void test_vm_exit_ctls(void) 5094 { 5095 test_exit_msr_store(); 5096 } 5097 5098 /* 5099 * Check that the virtual CPU checks all of the VMX controls as 5100 * documented in the Intel SDM. 5101 */ 5102 static void vmx_controls_test(void) 5103 { 5104 /* 5105 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5106 * fail due to invalid guest state, should we make it that 5107 * far. 5108 */ 5109 vmcs_write(GUEST_RFLAGS, 0); 5110 5111 test_vm_execution_ctls(); 5112 test_vm_exit_ctls(); 5113 test_vm_entry_ctls(); 5114 } 5115 5116 struct apic_reg_virt_config { 5117 bool apic_register_virtualization; 5118 bool use_tpr_shadow; 5119 bool virtualize_apic_accesses; 5120 bool virtualize_x2apic_mode; 5121 bool activate_secondary_controls; 5122 }; 5123 5124 struct apic_reg_test { 5125 const char *name; 5126 struct apic_reg_virt_config apic_reg_virt_config; 5127 }; 5128 5129 struct apic_reg_virt_expectation { 5130 enum Reason rd_exit_reason; 5131 enum Reason wr_exit_reason; 5132 u32 val; 5133 u32 (*virt_fn)(u32); 5134 5135 /* 5136 * If false, accessing the APIC access address from L2 is treated as a 5137 * normal memory operation, rather than triggering virtualization. 5138 */ 5139 bool virtualize_apic_accesses; 5140 }; 5141 5142 static u32 apic_virt_identity(u32 val) 5143 { 5144 return val; 5145 } 5146 5147 static u32 apic_virt_nibble1(u32 val) 5148 { 5149 return val & 0xf0; 5150 } 5151 5152 static u32 apic_virt_byte3(u32 val) 5153 { 5154 return val & (0xff << 24); 5155 } 5156 5157 static bool apic_reg_virt_exit_expectation( 5158 u32 reg, struct apic_reg_virt_config *config, 5159 struct apic_reg_virt_expectation *expectation) 5160 { 5161 /* Good configs, where some L2 APIC accesses are virtualized. */ 5162 bool virtualize_apic_accesses_only = 5163 config->virtualize_apic_accesses && 5164 !config->use_tpr_shadow && 5165 !config->apic_register_virtualization && 5166 !config->virtualize_x2apic_mode && 5167 config->activate_secondary_controls; 5168 bool virtualize_apic_accesses_and_use_tpr_shadow = 5169 config->virtualize_apic_accesses && 5170 config->use_tpr_shadow && 5171 !config->apic_register_virtualization && 5172 !config->virtualize_x2apic_mode && 5173 config->activate_secondary_controls; 5174 bool apic_register_virtualization = 5175 config->virtualize_apic_accesses && 5176 config->use_tpr_shadow && 5177 config->apic_register_virtualization && 5178 !config->virtualize_x2apic_mode && 5179 config->activate_secondary_controls; 5180 5181 expectation->val = MAGIC_VAL_1; 5182 expectation->virt_fn = apic_virt_identity; 5183 expectation->virtualize_apic_accesses = 5184 config->virtualize_apic_accesses && 5185 config->activate_secondary_controls; 5186 if (virtualize_apic_accesses_only) { 5187 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5188 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5189 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5190 switch (reg) { 5191 case APIC_TASKPRI: 5192 expectation->rd_exit_reason = VMX_VMCALL; 5193 expectation->wr_exit_reason = VMX_VMCALL; 5194 expectation->virt_fn = apic_virt_nibble1; 5195 break; 5196 default: 5197 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5198 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5199 } 5200 } else if (apic_register_virtualization) { 5201 expectation->rd_exit_reason = VMX_VMCALL; 5202 5203 switch (reg) { 5204 case APIC_ID: 5205 case APIC_EOI: 5206 case APIC_LDR: 5207 case APIC_DFR: 5208 case APIC_SPIV: 5209 case APIC_ESR: 5210 case APIC_ICR: 5211 case APIC_LVTT: 5212 case APIC_LVTTHMR: 5213 case APIC_LVTPC: 5214 case APIC_LVT0: 5215 case APIC_LVT1: 5216 case APIC_LVTERR: 5217 case APIC_TMICT: 5218 case APIC_TDCR: 5219 expectation->wr_exit_reason = VMX_APIC_WRITE; 5220 break; 5221 case APIC_LVR: 5222 case APIC_ISR ... APIC_ISR + 0x70: 5223 case APIC_TMR ... APIC_TMR + 0x70: 5224 case APIC_IRR ... APIC_IRR + 0x70: 5225 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5226 break; 5227 case APIC_TASKPRI: 5228 expectation->wr_exit_reason = VMX_VMCALL; 5229 expectation->virt_fn = apic_virt_nibble1; 5230 break; 5231 case APIC_ICR2: 5232 expectation->wr_exit_reason = VMX_VMCALL; 5233 expectation->virt_fn = apic_virt_byte3; 5234 break; 5235 default: 5236 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5237 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5238 } 5239 } else if (!expectation->virtualize_apic_accesses) { 5240 /* 5241 * No APIC registers are directly virtualized. This includes 5242 * VTPR, which can be virtualized through MOV to/from CR8 via 5243 * the use TPR shadow control, but not through directly 5244 * accessing VTPR. 5245 */ 5246 expectation->rd_exit_reason = VMX_VMCALL; 5247 expectation->wr_exit_reason = VMX_VMCALL; 5248 } else { 5249 printf("Cannot parse APIC register virtualization config:\n" 5250 "\tvirtualize_apic_accesses: %d\n" 5251 "\tuse_tpr_shadow: %d\n" 5252 "\tapic_register_virtualization: %d\n" 5253 "\tvirtualize_x2apic_mode: %d\n" 5254 "\tactivate_secondary_controls: %d\n", 5255 config->virtualize_apic_accesses, 5256 config->use_tpr_shadow, 5257 config->apic_register_virtualization, 5258 config->virtualize_x2apic_mode, 5259 config->activate_secondary_controls); 5260 5261 return false; 5262 } 5263 5264 return true; 5265 } 5266 5267 struct apic_reg_test apic_reg_tests[] = { 5268 /* Good configs, where some L2 APIC accesses are virtualized. */ 5269 { 5270 .name = "Virtualize APIC accesses", 5271 .apic_reg_virt_config = { 5272 .virtualize_apic_accesses = true, 5273 .use_tpr_shadow = false, 5274 .apic_register_virtualization = false, 5275 .virtualize_x2apic_mode = false, 5276 .activate_secondary_controls = true, 5277 }, 5278 }, 5279 { 5280 .name = "Virtualize APIC accesses + Use TPR shadow", 5281 .apic_reg_virt_config = { 5282 .virtualize_apic_accesses = true, 5283 .use_tpr_shadow = true, 5284 .apic_register_virtualization = false, 5285 .virtualize_x2apic_mode = false, 5286 .activate_secondary_controls = true, 5287 }, 5288 }, 5289 { 5290 .name = "APIC-register virtualization", 5291 .apic_reg_virt_config = { 5292 .virtualize_apic_accesses = true, 5293 .use_tpr_shadow = true, 5294 .apic_register_virtualization = true, 5295 .virtualize_x2apic_mode = false, 5296 .activate_secondary_controls = true, 5297 }, 5298 }, 5299 5300 /* 5301 * Test that the secondary processor-based VM-execution controls are 5302 * correctly ignored when "activate secondary controls" is disabled. 5303 */ 5304 { 5305 .name = "Activate secondary controls off", 5306 .apic_reg_virt_config = { 5307 .virtualize_apic_accesses = true, 5308 .use_tpr_shadow = false, 5309 .apic_register_virtualization = true, 5310 .virtualize_x2apic_mode = true, 5311 .activate_secondary_controls = false, 5312 }, 5313 }, 5314 { 5315 .name = "Activate secondary controls off + Use TPR shadow", 5316 .apic_reg_virt_config = { 5317 .virtualize_apic_accesses = true, 5318 .use_tpr_shadow = true, 5319 .apic_register_virtualization = true, 5320 .virtualize_x2apic_mode = true, 5321 .activate_secondary_controls = false, 5322 }, 5323 }, 5324 5325 /* 5326 * Test that the APIC access address is treated like an arbitrary memory 5327 * address when "virtualize APIC accesses" is disabled. 5328 */ 5329 { 5330 .name = "Virtualize APIC accesses off + Use TPR shadow", 5331 .apic_reg_virt_config = { 5332 .virtualize_apic_accesses = false, 5333 .use_tpr_shadow = true, 5334 .apic_register_virtualization = true, 5335 .virtualize_x2apic_mode = true, 5336 .activate_secondary_controls = true, 5337 }, 5338 }, 5339 5340 /* 5341 * Test that VM entry fails due to invalid controls when 5342 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5343 * disabled. 5344 */ 5345 { 5346 .name = "APIC-register virtualization + Use TPR shadow off", 5347 .apic_reg_virt_config = { 5348 .virtualize_apic_accesses = true, 5349 .use_tpr_shadow = false, 5350 .apic_register_virtualization = true, 5351 .virtualize_x2apic_mode = false, 5352 .activate_secondary_controls = true, 5353 }, 5354 }, 5355 5356 /* 5357 * Test that VM entry fails due to invalid controls when 5358 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5359 * disabled. 5360 */ 5361 { 5362 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5363 .apic_reg_virt_config = { 5364 .virtualize_apic_accesses = false, 5365 .use_tpr_shadow = false, 5366 .apic_register_virtualization = false, 5367 .virtualize_x2apic_mode = true, 5368 .activate_secondary_controls = true, 5369 }, 5370 }, 5371 { 5372 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5373 .apic_reg_virt_config = { 5374 .virtualize_apic_accesses = false, 5375 .use_tpr_shadow = false, 5376 .apic_register_virtualization = true, 5377 .virtualize_x2apic_mode = true, 5378 .activate_secondary_controls = true, 5379 }, 5380 }, 5381 5382 /* 5383 * Test that VM entry fails due to invalid controls when 5384 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5385 * is enabled. 5386 */ 5387 { 5388 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5389 .apic_reg_virt_config = { 5390 .virtualize_apic_accesses = true, 5391 .use_tpr_shadow = true, 5392 .apic_register_virtualization = false, 5393 .virtualize_x2apic_mode = true, 5394 .activate_secondary_controls = true, 5395 }, 5396 }, 5397 { 5398 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5399 .apic_reg_virt_config = { 5400 .virtualize_apic_accesses = true, 5401 .use_tpr_shadow = true, 5402 .apic_register_virtualization = true, 5403 .virtualize_x2apic_mode = true, 5404 .activate_secondary_controls = true, 5405 }, 5406 }, 5407 }; 5408 5409 enum Apic_op { 5410 APIC_OP_XAPIC_RD, 5411 APIC_OP_XAPIC_WR, 5412 TERMINATE, 5413 }; 5414 5415 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5416 { 5417 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5418 } 5419 5420 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5421 { 5422 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5423 } 5424 5425 struct apic_reg_virt_guest_args { 5426 enum Apic_op op; 5427 u32 *apic_access_address; 5428 u32 reg; 5429 u32 val; 5430 bool check_rd; 5431 u32 (*virt_fn)(u32); 5432 } apic_reg_virt_guest_args; 5433 5434 static void apic_reg_virt_guest(void) 5435 { 5436 volatile struct apic_reg_virt_guest_args *args = 5437 &apic_reg_virt_guest_args; 5438 5439 for (;;) { 5440 enum Apic_op op = args->op; 5441 u32 *apic_access_address = args->apic_access_address; 5442 u32 reg = args->reg; 5443 u32 val = args->val; 5444 bool check_rd = args->check_rd; 5445 u32 (*virt_fn)(u32) = args->virt_fn; 5446 5447 if (op == TERMINATE) 5448 break; 5449 5450 if (op == APIC_OP_XAPIC_RD) { 5451 u32 ret = vmx_xapic_read(apic_access_address, reg); 5452 5453 if (check_rd) { 5454 u32 want = virt_fn(val); 5455 u32 got = virt_fn(ret); 5456 5457 report("read 0x%x, expected 0x%x.", 5458 got == want, got, want); 5459 } 5460 } else if (op == APIC_OP_XAPIC_WR) { 5461 vmx_xapic_write(apic_access_address, reg, val); 5462 } 5463 5464 /* 5465 * The L1 should always execute a vmcall after it's done testing 5466 * an individual APIC operation. This helps to validate that the 5467 * L1 and L2 are in sync with each other, as expected. 5468 */ 5469 vmcall(); 5470 } 5471 } 5472 5473 static void test_xapic_rd( 5474 u32 reg, struct apic_reg_virt_expectation *expectation, 5475 u32 *apic_access_address, u32 *virtual_apic_page) 5476 { 5477 u32 val = expectation->val; 5478 u32 exit_reason_want = expectation->rd_exit_reason; 5479 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5480 5481 report_prefix_pushf("xapic - reading 0x%03x", reg); 5482 5483 /* Configure guest to do an xapic read */ 5484 args->op = APIC_OP_XAPIC_RD; 5485 args->apic_access_address = apic_access_address; 5486 args->reg = reg; 5487 args->val = val; 5488 args->check_rd = exit_reason_want == VMX_VMCALL; 5489 args->virt_fn = expectation->virt_fn; 5490 5491 /* Setup virtual APIC page */ 5492 if (!expectation->virtualize_apic_accesses) { 5493 apic_access_address[apic_reg_index(reg)] = val; 5494 virtual_apic_page[apic_reg_index(reg)] = 0; 5495 } else if (exit_reason_want == VMX_VMCALL) { 5496 apic_access_address[apic_reg_index(reg)] = 0; 5497 virtual_apic_page[apic_reg_index(reg)] = val; 5498 } 5499 5500 /* Enter guest */ 5501 enter_guest(); 5502 5503 /* 5504 * Validate the behavior and 5505 * pass a magic value back to the guest. 5506 */ 5507 if (exit_reason_want == VMX_APIC_ACCESS) { 5508 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5509 5510 assert_exit_reason(exit_reason_want); 5511 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5512 apic_page_offset == reg, apic_page_offset, reg); 5513 skip_exit_insn(); 5514 5515 /* Reenter guest so it can consume/check rcx and exit again. */ 5516 enter_guest(); 5517 } else if (exit_reason_want != VMX_VMCALL) { 5518 report("Oops, bad exit expectation: %u.", false, 5519 exit_reason_want); 5520 } 5521 5522 skip_exit_vmcall(); 5523 report_prefix_pop(); 5524 } 5525 5526 static void test_xapic_wr( 5527 u32 reg, struct apic_reg_virt_expectation *expectation, 5528 u32 *apic_access_address, u32 *virtual_apic_page) 5529 { 5530 u32 val = expectation->val; 5531 u32 exit_reason_want = expectation->wr_exit_reason; 5532 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5533 bool virtualized = 5534 expectation->virtualize_apic_accesses && 5535 (exit_reason_want == VMX_APIC_WRITE || 5536 exit_reason_want == VMX_VMCALL); 5537 bool checked = false; 5538 5539 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5540 5541 /* Configure guest to do an xapic read */ 5542 args->op = APIC_OP_XAPIC_WR; 5543 args->apic_access_address = apic_access_address; 5544 args->reg = reg; 5545 args->val = val; 5546 5547 /* Setup virtual APIC page */ 5548 if (virtualized || !expectation->virtualize_apic_accesses) { 5549 apic_access_address[apic_reg_index(reg)] = 0; 5550 virtual_apic_page[apic_reg_index(reg)] = 0; 5551 } 5552 5553 /* Enter guest */ 5554 enter_guest(); 5555 5556 /* 5557 * Validate the behavior and 5558 * pass a magic value back to the guest. 5559 */ 5560 if (exit_reason_want == VMX_APIC_ACCESS) { 5561 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5562 5563 assert_exit_reason(exit_reason_want); 5564 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5565 apic_page_offset == reg, apic_page_offset, reg); 5566 skip_exit_insn(); 5567 5568 /* Reenter guest so it can consume/check rcx and exit again. */ 5569 enter_guest(); 5570 } else if (exit_reason_want == VMX_APIC_WRITE) { 5571 assert_exit_reason(exit_reason_want); 5572 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5573 virtual_apic_page[apic_reg_index(reg)] == val, 5574 apic_reg_index(reg), 5575 virtual_apic_page[apic_reg_index(reg)], val); 5576 checked = true; 5577 5578 /* Reenter guest so it can consume/check rcx and exit again. */ 5579 enter_guest(); 5580 } else if (exit_reason_want != VMX_VMCALL) { 5581 report("Oops, bad exit expectation: %u.", false, 5582 exit_reason_want); 5583 } 5584 5585 assert_exit_reason(VMX_VMCALL); 5586 if (virtualized && !checked) { 5587 u32 want = expectation->virt_fn(val); 5588 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5589 got = expectation->virt_fn(got); 5590 5591 report("exitless write; val is 0x%x, want 0x%x", 5592 got == want, got, want); 5593 } else if (!expectation->virtualize_apic_accesses && !checked) { 5594 u32 got = apic_access_address[apic_reg_index(reg)]; 5595 5596 report("non-virtualized write; val is 0x%x, want 0x%x", 5597 got == val, got, val); 5598 } else if (!expectation->virtualize_apic_accesses && checked) { 5599 report("Non-virtualized write was prematurely checked!", false); 5600 } 5601 5602 skip_exit_vmcall(); 5603 report_prefix_pop(); 5604 } 5605 5606 enum Config_type { 5607 CONFIG_TYPE_GOOD, 5608 CONFIG_TYPE_UNSUPPORTED, 5609 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5610 }; 5611 5612 static enum Config_type configure_apic_reg_virt_test( 5613 struct apic_reg_virt_config *apic_reg_virt_config) 5614 { 5615 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5616 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5617 /* Configs where L2 entry fails early, due to invalid controls. */ 5618 bool use_tpr_shadow_incorrectly_off = 5619 !apic_reg_virt_config->use_tpr_shadow && 5620 (apic_reg_virt_config->apic_register_virtualization || 5621 apic_reg_virt_config->virtualize_x2apic_mode) && 5622 apic_reg_virt_config->activate_secondary_controls; 5623 bool virtualize_apic_accesses_incorrectly_on = 5624 apic_reg_virt_config->virtualize_apic_accesses && 5625 apic_reg_virt_config->virtualize_x2apic_mode && 5626 apic_reg_virt_config->activate_secondary_controls; 5627 bool vmentry_fails_early = 5628 use_tpr_shadow_incorrectly_off || 5629 virtualize_apic_accesses_incorrectly_on; 5630 5631 if (apic_reg_virt_config->activate_secondary_controls) { 5632 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5633 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5634 return CONFIG_TYPE_UNSUPPORTED; 5635 } 5636 cpu_exec_ctrl0 |= CPU_SECONDARY; 5637 } else { 5638 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5639 } 5640 5641 if (apic_reg_virt_config->virtualize_apic_accesses) { 5642 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5643 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5644 return CONFIG_TYPE_UNSUPPORTED; 5645 } 5646 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5647 } else { 5648 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5649 } 5650 5651 if (apic_reg_virt_config->use_tpr_shadow) { 5652 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5653 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5654 return CONFIG_TYPE_UNSUPPORTED; 5655 } 5656 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5657 } else { 5658 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5659 } 5660 5661 if (apic_reg_virt_config->apic_register_virtualization) { 5662 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5663 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5664 return CONFIG_TYPE_UNSUPPORTED; 5665 } 5666 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5667 } else { 5668 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5669 } 5670 5671 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5672 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5673 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5674 return CONFIG_TYPE_UNSUPPORTED; 5675 } 5676 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5677 } else { 5678 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5679 } 5680 5681 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5682 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5683 5684 if (vmentry_fails_early) 5685 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5686 5687 return CONFIG_TYPE_GOOD; 5688 } 5689 5690 static bool cpu_has_apicv(void) 5691 { 5692 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5693 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5694 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5695 } 5696 5697 /* Validates APIC register access across valid virtualization configurations. */ 5698 static void apic_reg_virt_test(void) 5699 { 5700 u32 *apic_access_address; 5701 u32 *virtual_apic_page; 5702 u64 control; 5703 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5704 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5705 int i; 5706 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5707 5708 if (!cpu_has_apicv()) { 5709 report_skip(__func__); 5710 return; 5711 } 5712 5713 control = cpu_exec_ctrl1; 5714 control &= ~CPU_VINTD; 5715 vmcs_write(CPU_EXEC_CTRL1, control); 5716 5717 test_set_guest(apic_reg_virt_guest); 5718 5719 /* 5720 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5721 * VM-execution is guaranteed to apply only if translations to the 5722 * APIC-access address use a 4-KByte page. 5723 */ 5724 apic_access_address = alloc_page(); 5725 force_4k_page(apic_access_address); 5726 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5727 5728 virtual_apic_page = alloc_page(); 5729 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5730 5731 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5732 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5733 struct apic_reg_virt_config *apic_reg_virt_config = 5734 &apic_reg_test->apic_reg_virt_config; 5735 enum Config_type config_type; 5736 u32 reg; 5737 5738 printf("--- %s test ---\n", apic_reg_test->name); 5739 config_type = 5740 configure_apic_reg_virt_test(apic_reg_virt_config); 5741 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5742 printf("Skip because of missing features.\n"); 5743 continue; 5744 } 5745 5746 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 5747 enter_guest_with_bad_controls(); 5748 continue; 5749 } 5750 5751 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 5752 struct apic_reg_virt_expectation expectation = {}; 5753 bool ok; 5754 5755 ok = apic_reg_virt_exit_expectation( 5756 reg, apic_reg_virt_config, &expectation); 5757 if (!ok) { 5758 report("Malformed test.", false); 5759 break; 5760 } 5761 5762 test_xapic_rd(reg, &expectation, apic_access_address, 5763 virtual_apic_page); 5764 test_xapic_wr(reg, &expectation, apic_access_address, 5765 virtual_apic_page); 5766 } 5767 } 5768 5769 /* Terminate the guest */ 5770 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5771 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5772 args->op = TERMINATE; 5773 enter_guest(); 5774 assert_exit_reason(VMX_VMCALL); 5775 } 5776 5777 struct virt_x2apic_mode_config { 5778 struct apic_reg_virt_config apic_reg_virt_config; 5779 bool virtual_interrupt_delivery; 5780 bool use_msr_bitmaps; 5781 bool disable_x2apic_msr_intercepts; 5782 bool disable_x2apic; 5783 }; 5784 5785 struct virt_x2apic_mode_test_case { 5786 const char *name; 5787 struct virt_x2apic_mode_config virt_x2apic_mode_config; 5788 }; 5789 5790 enum Virt_x2apic_mode_behavior_type { 5791 X2APIC_ACCESS_VIRTUALIZED, 5792 X2APIC_ACCESS_PASSED_THROUGH, 5793 X2APIC_ACCESS_TRIGGERS_GP, 5794 }; 5795 5796 struct virt_x2apic_mode_expectation { 5797 enum Reason rd_exit_reason; 5798 enum Reason wr_exit_reason; 5799 5800 /* 5801 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 5802 * the x2APIC registers are 32 bits. Notice: 5803 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 5804 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 5805 */ 5806 u64 rd_val; 5807 u64 wr_val; 5808 5809 /* 5810 * Compares input to virtualized output; 5811 * 1st arg is pointer to return expected virtualization output. 5812 */ 5813 u64 (*virt_fn)(u64); 5814 5815 enum Virt_x2apic_mode_behavior_type rd_behavior; 5816 enum Virt_x2apic_mode_behavior_type wr_behavior; 5817 bool wr_only; 5818 }; 5819 5820 static u64 virt_x2apic_mode_identity(u64 val) 5821 { 5822 return val; 5823 } 5824 5825 static u64 virt_x2apic_mode_nibble1(u64 val) 5826 { 5827 return val & 0xf0; 5828 } 5829 5830 static void virt_x2apic_mode_rd_expectation( 5831 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5832 bool apic_register_virtualization, bool virtual_interrupt_delivery, 5833 struct virt_x2apic_mode_expectation *expectation) 5834 { 5835 bool readable = 5836 !x2apic_reg_reserved(reg) && 5837 reg != APIC_EOI && 5838 reg != APIC_CMCI; 5839 5840 expectation->rd_exit_reason = VMX_VMCALL; 5841 expectation->virt_fn = virt_x2apic_mode_identity; 5842 if (virt_x2apic_mode_on && apic_register_virtualization) { 5843 expectation->rd_val = MAGIC_VAL_1; 5844 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 5845 expectation->virt_fn = virt_x2apic_mode_nibble1; 5846 else if (reg == APIC_TASKPRI) 5847 expectation->virt_fn = virt_x2apic_mode_nibble1; 5848 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5849 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 5850 reg == APIC_TASKPRI) { 5851 expectation->rd_val = MAGIC_VAL_1; 5852 expectation->virt_fn = virt_x2apic_mode_nibble1; 5853 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5854 } else if (!disable_x2apic && readable) { 5855 expectation->rd_val = apic_read(reg); 5856 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5857 } else { 5858 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5859 } 5860 } 5861 5862 /* 5863 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 5864 * 5865 * For writable registers, get_x2apic_wr_val() deposits the write value into the 5866 * val pointer arg and returns true. For non-writable registers, val is not 5867 * modified and get_x2apic_wr_val() returns false. 5868 * 5869 * CMCI, including the LVT CMCI register, is disabled by default. Thus, 5870 * get_x2apic_wr_val() treats this register as non-writable. 5871 */ 5872 static bool get_x2apic_wr_val(u32 reg, u64 *val) 5873 { 5874 switch (reg) { 5875 case APIC_TASKPRI: 5876 /* Bits 31:8 are reserved. */ 5877 *val &= 0xff; 5878 break; 5879 case APIC_EOI: 5880 case APIC_ESR: 5881 case APIC_TMICT: 5882 /* 5883 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 5884 * TMICT: A write of 0 to the initial-count register effectively 5885 * stops the local APIC timer, in both one-shot and 5886 * periodic mode. 5887 */ 5888 *val = 0; 5889 break; 5890 case APIC_SPIV: 5891 case APIC_LVTT: 5892 case APIC_LVTTHMR: 5893 case APIC_LVTPC: 5894 case APIC_LVT0: 5895 case APIC_LVT1: 5896 case APIC_LVTERR: 5897 case APIC_TDCR: 5898 /* 5899 * To avoid writing a 1 to a reserved bit or causing some other 5900 * unintended side effect, read the current value and use it as 5901 * the write value. 5902 */ 5903 *val = apic_read(reg); 5904 break; 5905 case APIC_ICR: 5906 *val = 0x40000 | 0xf1; 5907 break; 5908 case APIC_SELF_IPI: 5909 /* 5910 * With special processing (i.e., virtualize x2APIC mode + 5911 * virtual interrupt delivery), writing zero causes an 5912 * APIC-write VM exit. We plan to add a test for enabling 5913 * "virtual-interrupt delivery" in VMCS12, and that's where we 5914 * will test a self IPI with special processing. 5915 */ 5916 *val = 0x0; 5917 break; 5918 default: 5919 return false; 5920 } 5921 5922 return true; 5923 } 5924 5925 static bool special_processing_applies(u32 reg, u64 *val, 5926 bool virt_int_delivery) 5927 { 5928 bool special_processing = 5929 (reg == APIC_TASKPRI) || 5930 (virt_int_delivery && 5931 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 5932 5933 if (special_processing) { 5934 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 5935 return true; 5936 } 5937 5938 return false; 5939 } 5940 5941 static void virt_x2apic_mode_wr_expectation( 5942 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5943 bool virt_int_delivery, 5944 struct virt_x2apic_mode_expectation *expectation) 5945 { 5946 expectation->wr_exit_reason = VMX_VMCALL; 5947 expectation->wr_val = MAGIC_VAL_1; 5948 expectation->wr_only = false; 5949 5950 if (virt_x2apic_mode_on && 5951 special_processing_applies(reg, &expectation->wr_val, 5952 virt_int_delivery)) { 5953 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 5954 if (reg == APIC_SELF_IPI) 5955 expectation->wr_exit_reason = VMX_APIC_WRITE; 5956 } else if (!disable_x2apic && 5957 get_x2apic_wr_val(reg, &expectation->wr_val)) { 5958 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5959 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 5960 expectation->wr_only = true; 5961 if (reg == APIC_ICR) 5962 expectation->wr_exit_reason = VMX_EXTINT; 5963 } else { 5964 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5965 /* 5966 * Writing 1 to a reserved bit triggers a #GP. 5967 * Thus, set the write value to 0, which seems 5968 * the most likely to detect a missed #GP. 5969 */ 5970 expectation->wr_val = 0; 5971 } 5972 } 5973 5974 static void virt_x2apic_mode_exit_expectation( 5975 u32 reg, struct virt_x2apic_mode_config *config, 5976 struct virt_x2apic_mode_expectation *expectation) 5977 { 5978 struct apic_reg_virt_config *base_config = 5979 &config->apic_reg_virt_config; 5980 bool virt_x2apic_mode_on = 5981 base_config->virtualize_x2apic_mode && 5982 config->use_msr_bitmaps && 5983 config->disable_x2apic_msr_intercepts && 5984 base_config->activate_secondary_controls; 5985 5986 virt_x2apic_mode_wr_expectation( 5987 reg, virt_x2apic_mode_on, config->disable_x2apic, 5988 config->virtual_interrupt_delivery, expectation); 5989 virt_x2apic_mode_rd_expectation( 5990 reg, virt_x2apic_mode_on, config->disable_x2apic, 5991 base_config->apic_register_virtualization, 5992 config->virtual_interrupt_delivery, expectation); 5993 } 5994 5995 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 5996 /* 5997 * Baseline "virtualize x2APIC mode" configuration: 5998 * - virtualize x2APIC mode 5999 * - virtual-interrupt delivery 6000 * - APIC-register virtualization 6001 * - x2APIC MSR intercepts disabled 6002 * 6003 * Reads come from virtual APIC page, special processing applies to 6004 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6005 * APIC. 6006 */ 6007 { 6008 .name = "Baseline", 6009 .virt_x2apic_mode_config = { 6010 .virtual_interrupt_delivery = true, 6011 .use_msr_bitmaps = true, 6012 .disable_x2apic_msr_intercepts = true, 6013 .disable_x2apic = false, 6014 .apic_reg_virt_config = { 6015 .apic_register_virtualization = true, 6016 .use_tpr_shadow = true, 6017 .virtualize_apic_accesses = false, 6018 .virtualize_x2apic_mode = true, 6019 .activate_secondary_controls = true, 6020 }, 6021 }, 6022 }, 6023 { 6024 .name = "Baseline w/ x2apic disabled", 6025 .virt_x2apic_mode_config = { 6026 .virtual_interrupt_delivery = true, 6027 .use_msr_bitmaps = true, 6028 .disable_x2apic_msr_intercepts = true, 6029 .disable_x2apic = true, 6030 .apic_reg_virt_config = { 6031 .apic_register_virtualization = true, 6032 .use_tpr_shadow = true, 6033 .virtualize_apic_accesses = false, 6034 .virtualize_x2apic_mode = true, 6035 .activate_secondary_controls = true, 6036 }, 6037 }, 6038 }, 6039 6040 /* 6041 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6042 * APIC page, special processing applies to VTPR, and all other writes 6043 * pass through to L1 APIC. 6044 */ 6045 { 6046 .name = "Baseline - virtual interrupt delivery", 6047 .virt_x2apic_mode_config = { 6048 .virtual_interrupt_delivery = false, 6049 .use_msr_bitmaps = true, 6050 .disable_x2apic_msr_intercepts = true, 6051 .disable_x2apic = false, 6052 .apic_reg_virt_config = { 6053 .apic_register_virtualization = true, 6054 .use_tpr_shadow = true, 6055 .virtualize_apic_accesses = false, 6056 .virtualize_x2apic_mode = true, 6057 .activate_secondary_controls = true, 6058 }, 6059 }, 6060 }, 6061 6062 /* 6063 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6064 * through to L1's APIC, unless reading VTPR 6065 */ 6066 { 6067 .name = "Virtualize x2APIC mode, no APIC reg virt", 6068 .virt_x2apic_mode_config = { 6069 .virtual_interrupt_delivery = true, 6070 .use_msr_bitmaps = true, 6071 .disable_x2apic_msr_intercepts = true, 6072 .disable_x2apic = false, 6073 .apic_reg_virt_config = { 6074 .apic_register_virtualization = false, 6075 .use_tpr_shadow = true, 6076 .virtualize_apic_accesses = false, 6077 .virtualize_x2apic_mode = true, 6078 .activate_secondary_controls = true, 6079 }, 6080 }, 6081 }, 6082 { 6083 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6084 .virt_x2apic_mode_config = { 6085 .virtual_interrupt_delivery = true, 6086 .use_msr_bitmaps = true, 6087 .disable_x2apic_msr_intercepts = true, 6088 .disable_x2apic = true, 6089 .apic_reg_virt_config = { 6090 .apic_register_virtualization = false, 6091 .use_tpr_shadow = true, 6092 .virtualize_apic_accesses = false, 6093 .virtualize_x2apic_mode = true, 6094 .activate_secondary_controls = true, 6095 }, 6096 }, 6097 }, 6098 6099 /* 6100 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6101 * and disable intercepts for the x2APIC MSRs, but fail to enable 6102 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6103 * MSRs). 6104 */ 6105 { 6106 .name = "Fail to enable activate secondary controls", 6107 .virt_x2apic_mode_config = { 6108 .virtual_interrupt_delivery = true, 6109 .use_msr_bitmaps = true, 6110 .disable_x2apic_msr_intercepts = true, 6111 .disable_x2apic = false, 6112 .apic_reg_virt_config = { 6113 .apic_register_virtualization = true, 6114 .use_tpr_shadow = true, 6115 .virtualize_apic_accesses = false, 6116 .virtualize_x2apic_mode = true, 6117 .activate_secondary_controls = false, 6118 }, 6119 }, 6120 }, 6121 6122 /* 6123 * Enable "APIC-register virtualization" and enable "activate secondary 6124 * controls" and disable intercepts for the x2APIC MSRs, but do not 6125 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6126 * gets access to L1's x2APIC MSRs). 6127 */ 6128 { 6129 .name = "Fail to enable virtualize x2APIC mode", 6130 .virt_x2apic_mode_config = { 6131 .virtual_interrupt_delivery = true, 6132 .use_msr_bitmaps = true, 6133 .disable_x2apic_msr_intercepts = true, 6134 .disable_x2apic = false, 6135 .apic_reg_virt_config = { 6136 .apic_register_virtualization = true, 6137 .use_tpr_shadow = true, 6138 .virtualize_apic_accesses = false, 6139 .virtualize_x2apic_mode = false, 6140 .activate_secondary_controls = true, 6141 }, 6142 }, 6143 }, 6144 6145 /* 6146 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6147 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6148 */ 6149 { 6150 .name = "Baseline", 6151 .virt_x2apic_mode_config = { 6152 .virtual_interrupt_delivery = true, 6153 .use_msr_bitmaps = true, 6154 .disable_x2apic_msr_intercepts = true, 6155 .disable_x2apic = false, 6156 .apic_reg_virt_config = { 6157 .apic_register_virtualization = true, 6158 .use_tpr_shadow = true, 6159 .virtualize_apic_accesses = false, 6160 .virtualize_x2apic_mode = false, 6161 .activate_secondary_controls = true, 6162 }, 6163 }, 6164 }, 6165 }; 6166 6167 enum X2apic_op { 6168 X2APIC_OP_RD, 6169 X2APIC_OP_WR, 6170 X2APIC_TERMINATE, 6171 }; 6172 6173 static u64 vmx_x2apic_read(u32 reg) 6174 { 6175 u32 msr_addr = x2apic_msr(reg); 6176 u64 val; 6177 6178 val = rdmsr(msr_addr); 6179 6180 return val; 6181 } 6182 6183 static void vmx_x2apic_write(u32 reg, u64 val) 6184 { 6185 u32 msr_addr = x2apic_msr(reg); 6186 6187 wrmsr(msr_addr, val); 6188 } 6189 6190 struct virt_x2apic_mode_guest_args { 6191 enum X2apic_op op; 6192 u32 reg; 6193 u64 val; 6194 bool should_gp; 6195 u64 (*virt_fn)(u64); 6196 } virt_x2apic_mode_guest_args; 6197 6198 static volatile bool handle_x2apic_gp_ran; 6199 static volatile u32 handle_x2apic_gp_insn_len; 6200 static void handle_x2apic_gp(struct ex_regs *regs) 6201 { 6202 handle_x2apic_gp_ran = true; 6203 regs->rip += handle_x2apic_gp_insn_len; 6204 } 6205 6206 static handler setup_x2apic_gp_handler(void) 6207 { 6208 handler old_handler; 6209 6210 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6211 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6212 handle_x2apic_gp_insn_len = 2; 6213 6214 return old_handler; 6215 } 6216 6217 static void teardown_x2apic_gp_handler(handler old_handler) 6218 { 6219 handle_exception(GP_VECTOR, old_handler); 6220 6221 /* 6222 * Defensively reset instruction length, so that if the handler is 6223 * incorrectly used, it will loop infinitely, rather than run off into 6224 * la la land. 6225 */ 6226 handle_x2apic_gp_insn_len = 0; 6227 handle_x2apic_gp_ran = false; 6228 } 6229 6230 static void virt_x2apic_mode_guest(void) 6231 { 6232 volatile struct virt_x2apic_mode_guest_args *args = 6233 &virt_x2apic_mode_guest_args; 6234 6235 for (;;) { 6236 enum X2apic_op op = args->op; 6237 u32 reg = args->reg; 6238 u64 val = args->val; 6239 bool should_gp = args->should_gp; 6240 u64 (*virt_fn)(u64) = args->virt_fn; 6241 handler old_handler; 6242 6243 if (op == X2APIC_TERMINATE) 6244 break; 6245 6246 if (should_gp) { 6247 TEST_ASSERT(!handle_x2apic_gp_ran); 6248 old_handler = setup_x2apic_gp_handler(); 6249 } 6250 6251 if (op == X2APIC_OP_RD) { 6252 u64 ret = vmx_x2apic_read(reg); 6253 6254 if (!should_gp) { 6255 u64 want = virt_fn(val); 6256 u64 got = virt_fn(ret); 6257 6258 report("APIC read; got 0x%lx, want 0x%lx.", 6259 got == want, got, want); 6260 } 6261 } else if (op == X2APIC_OP_WR) { 6262 vmx_x2apic_write(reg, val); 6263 } 6264 6265 if (should_gp) { 6266 report("x2APIC op triggered GP.", 6267 handle_x2apic_gp_ran); 6268 teardown_x2apic_gp_handler(old_handler); 6269 } 6270 6271 /* 6272 * The L1 should always execute a vmcall after it's done testing 6273 * an individual APIC operation. This helps to validate that the 6274 * L1 and L2 are in sync with each other, as expected. 6275 */ 6276 vmcall(); 6277 } 6278 } 6279 6280 static void test_x2apic_rd( 6281 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6282 u32 *virtual_apic_page) 6283 { 6284 u64 val = expectation->rd_val; 6285 u32 exit_reason_want = expectation->rd_exit_reason; 6286 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6287 6288 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6289 6290 /* Configure guest to do an x2apic read */ 6291 args->op = X2APIC_OP_RD; 6292 args->reg = reg; 6293 args->val = val; 6294 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6295 args->virt_fn = expectation->virt_fn; 6296 6297 /* Setup virtual APIC page */ 6298 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6299 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6300 6301 /* Enter guest */ 6302 enter_guest(); 6303 6304 if (exit_reason_want != VMX_VMCALL) { 6305 report("Oops, bad exit expectation: %u.", false, 6306 exit_reason_want); 6307 } 6308 6309 skip_exit_vmcall(); 6310 report_prefix_pop(); 6311 } 6312 6313 static volatile bool handle_x2apic_ipi_ran; 6314 static void handle_x2apic_ipi(isr_regs_t *regs) 6315 { 6316 handle_x2apic_ipi_ran = true; 6317 eoi(); 6318 } 6319 6320 static void test_x2apic_wr( 6321 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6322 u32 *virtual_apic_page) 6323 { 6324 u64 val = expectation->wr_val; 6325 u32 exit_reason_want = expectation->wr_exit_reason; 6326 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6327 int ipi_vector = 0xf1; 6328 u32 restore_val = 0; 6329 6330 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6331 6332 /* Configure guest to do an x2apic read */ 6333 args->op = X2APIC_OP_WR; 6334 args->reg = reg; 6335 args->val = val; 6336 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6337 6338 /* Setup virtual APIC page */ 6339 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6340 virtual_apic_page[apic_reg_index(reg)] = 0; 6341 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6342 restore_val = apic_read(reg); 6343 6344 /* Setup IPI handler */ 6345 handle_x2apic_ipi_ran = false; 6346 handle_irq(ipi_vector, handle_x2apic_ipi); 6347 6348 /* Enter guest */ 6349 enter_guest(); 6350 6351 /* 6352 * Validate the behavior and 6353 * pass a magic value back to the guest. 6354 */ 6355 if (exit_reason_want == VMX_EXTINT) { 6356 assert_exit_reason(exit_reason_want); 6357 6358 /* Clear the external interrupt. */ 6359 irq_enable(); 6360 asm volatile ("nop"); 6361 irq_disable(); 6362 report("Got pending interrupt after IRQ enabled.", 6363 handle_x2apic_ipi_ran); 6364 6365 enter_guest(); 6366 } else if (exit_reason_want == VMX_APIC_WRITE) { 6367 assert_exit_reason(exit_reason_want); 6368 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6369 virtual_apic_page[apic_reg_index(reg)] == val, 6370 apic_reg_index(reg), 6371 virtual_apic_page[apic_reg_index(reg)], val); 6372 6373 /* Reenter guest so it can consume/check rcx and exit again. */ 6374 enter_guest(); 6375 } else if (exit_reason_want != VMX_VMCALL) { 6376 report("Oops, bad exit expectation: %u.", false, 6377 exit_reason_want); 6378 } 6379 6380 assert_exit_reason(VMX_VMCALL); 6381 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6382 u64 want = val; 6383 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6384 6385 report("x2APIC write; got 0x%x, want 0x%lx", 6386 got == want, got, want); 6387 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6388 if (!expectation->wr_only) { 6389 u32 got = apic_read(reg); 6390 bool ok; 6391 6392 /* 6393 * When L1's TPR is passed through to L2, the lower 6394 * nibble can be lost. For example, if L2 executes 6395 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6396 * 6397 * Here's how the lower nibble can get lost: 6398 * 1. L2 executes WRMSR(0x808, 0x78). 6399 * 2. L2 exits to L0 with a WRMSR exit. 6400 * 3. L0 emulates WRMSR, by writing L1's TPR. 6401 * 4. L0 re-enters L2. 6402 * 5. L2 exits to L0 (reason doesn't matter). 6403 * 6. L0 reflects L2's exit to L1. 6404 * 7. Before entering L1, L0 exits to user-space 6405 * (e.g., to satisfy TPR access reporting). 6406 * 8. User-space executes KVM_SET_REGS ioctl, which 6407 * clears the lower nibble of L1's TPR. 6408 */ 6409 if (reg == APIC_TASKPRI) { 6410 got = apic_virt_nibble1(got); 6411 val = apic_virt_nibble1(val); 6412 } 6413 6414 ok = got == val; 6415 report("non-virtualized write; val is 0x%x, want 0x%lx", 6416 ok, got, val); 6417 apic_write(reg, restore_val); 6418 } else { 6419 report("non-virtualized and write-only OK", true); 6420 } 6421 } 6422 skip_exit_insn(); 6423 6424 report_prefix_pop(); 6425 } 6426 6427 static enum Config_type configure_virt_x2apic_mode_test( 6428 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6429 u8 *msr_bitmap_page) 6430 { 6431 int msr; 6432 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6433 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6434 6435 /* x2apic-specific VMCS config */ 6436 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6437 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6438 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6439 } else { 6440 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6441 } 6442 6443 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6444 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6445 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6446 return CONFIG_TYPE_UNSUPPORTED; 6447 } 6448 cpu_exec_ctrl1 |= CPU_VINTD; 6449 } else { 6450 cpu_exec_ctrl1 &= ~CPU_VINTD; 6451 } 6452 6453 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6454 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6455 6456 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6457 for (msr = 0x800; msr <= 0x8ff; msr++) { 6458 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6459 clear_bit(msr, msr_bitmap_page + 0x000); 6460 clear_bit(msr, msr_bitmap_page + 0x800); 6461 } else { 6462 set_bit(msr, msr_bitmap_page + 0x000); 6463 set_bit(msr, msr_bitmap_page + 0x800); 6464 } 6465 } 6466 6467 /* x2APIC mode can impact virtualization */ 6468 reset_apic(); 6469 if (!virt_x2apic_mode_config->disable_x2apic) 6470 enable_x2apic(); 6471 6472 return configure_apic_reg_virt_test( 6473 &virt_x2apic_mode_config->apic_reg_virt_config); 6474 } 6475 6476 static void virt_x2apic_mode_test(void) 6477 { 6478 u32 *virtual_apic_page; 6479 u8 *msr_bitmap_page; 6480 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6481 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6482 int i; 6483 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6484 6485 if (!cpu_has_apicv()) { 6486 report_skip(__func__); 6487 return; 6488 } 6489 6490 /* 6491 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6492 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6493 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6494 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6495 * "Virtualize x2APIC mod" control set, even when it didn't. 6496 */ 6497 if (has_spec_ctrl()) 6498 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6499 6500 /* 6501 * Check that VMCS12 supports: 6502 * - "Virtual-APIC address", indicated by "use TPR shadow" 6503 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6504 */ 6505 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6506 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6507 return; 6508 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6509 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6510 return; 6511 } 6512 6513 test_set_guest(virt_x2apic_mode_guest); 6514 6515 virtual_apic_page = alloc_page(); 6516 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6517 6518 msr_bitmap_page = alloc_page(); 6519 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6520 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6521 6522 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6523 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6524 &virt_x2apic_mode_tests[i]; 6525 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6526 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6527 enum Config_type config_type; 6528 u32 reg; 6529 6530 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6531 config_type = 6532 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6533 msr_bitmap_page); 6534 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6535 report_skip("Skip because of missing features.\n"); 6536 continue; 6537 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6538 enter_guest_with_bad_controls(); 6539 continue; 6540 } 6541 6542 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6543 struct virt_x2apic_mode_expectation expectation; 6544 6545 virt_x2apic_mode_exit_expectation( 6546 reg, virt_x2apic_mode_config, &expectation); 6547 6548 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6549 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6550 } 6551 } 6552 6553 6554 /* Terminate the guest */ 6555 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6556 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6557 args->op = X2APIC_TERMINATE; 6558 enter_guest(); 6559 assert_exit_reason(VMX_VMCALL); 6560 } 6561 6562 /* 6563 * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP 6564 * field and the IA32_SYSENTER_EIP field must each contain a canonical 6565 * address. 6566 * 6567 * [Intel SDM] 6568 */ 6569 static void test_sysenter_field(u32 field, const char *name) 6570 { 6571 u64 addr_saved = vmcs_read(field); 6572 6573 vmcs_write(field, NONCANONICAL); 6574 report_prefix_pushf("%s non-canonical", name); 6575 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 6576 report_prefix_pop(); 6577 6578 vmcs_write(field, 0xffffffff); 6579 report_prefix_pushf("%s canonical", name); 6580 test_vmx_vmlaunch(0, false); 6581 report_prefix_pop(); 6582 6583 vmcs_write(field, addr_saved); 6584 } 6585 6586 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6587 { 6588 u64 val; 6589 u64 cr_saved = vmcs_read(cr); 6590 int i; 6591 6592 val = fixed0 & fixed1; 6593 if (cr == HOST_CR4) 6594 vmcs_write(cr, val | X86_CR4_PAE); 6595 else 6596 vmcs_write(cr, val); 6597 report_prefix_pushf("%s %lx", cr_name, val); 6598 if (val == fixed0) 6599 test_vmx_vmlaunch(0, false); 6600 else 6601 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6602 false); 6603 report_prefix_pop(); 6604 6605 for (i = 0; i < 64; i++) { 6606 6607 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6608 if ((fixed1 & (1ull << i)) == 0) { 6609 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6610 (1ull << i) & X86_CR4_SMAP)) 6611 continue; 6612 6613 vmcs_write(cr, cr_saved | (1ull << i)); 6614 report_prefix_pushf("%s %llx", cr_name, 6615 cr_saved | (1ull << i)); 6616 test_vmx_vmlaunch( 6617 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6618 false); 6619 report_prefix_pop(); 6620 } 6621 6622 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6623 if (fixed0 & (1ull << i)) { 6624 vmcs_write(cr, cr_saved & ~(1ull << i)); 6625 report_prefix_pushf("%s %llx", cr_name, 6626 cr_saved & ~(1ull << i)); 6627 test_vmx_vmlaunch( 6628 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6629 false); 6630 report_prefix_pop(); 6631 } 6632 } 6633 6634 vmcs_write(cr, cr_saved); 6635 } 6636 6637 /* 6638 * 1. The CR0 field must not set any bit to a value not supported in VMX 6639 * operation. 6640 * 2. The CR4 field must not set any bit to a value not supported in VMX 6641 * operation. 6642 * 3. On processors that support Intel 64 architecture, the CR3 field must 6643 * be such that bits 63:52 and bits in the range 51:32 beyond the 6644 * processor’s physical-address width must be 0. 6645 * 6646 * [Intel SDM] 6647 */ 6648 static void test_host_ctl_regs(void) 6649 { 6650 u64 fixed0, fixed1, cr3, cr3_saved; 6651 int i; 6652 6653 /* Test CR0 */ 6654 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6655 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6656 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6657 6658 /* Test CR4 */ 6659 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6660 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6661 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6662 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6663 6664 /* Test CR3 */ 6665 cr3_saved = vmcs_read(HOST_CR3); 6666 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6667 cr3 = cr3_saved | (1ul << i); 6668 vmcs_write(HOST_CR3, cr3); 6669 report_prefix_pushf("HOST_CR3 %lx", cr3); 6670 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6671 false); 6672 report_prefix_pop(); 6673 } 6674 6675 vmcs_write(HOST_CR3, cr3_saved); 6676 } 6677 6678 /* 6679 * PAT values higher than 8 are uninteresting since they're likely lumped 6680 * in with "8". We only test values above 8 one bit at a time, 6681 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 6682 */ 6683 #define PAT_VAL_LIMIT 8 6684 6685 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 6686 u64 ctrl_bit) 6687 { 6688 u32 ctrl_saved = vmcs_read(ctrl_field); 6689 u64 pat_saved = vmcs_read(field); 6690 u64 i, val; 6691 u32 j; 6692 int error; 6693 6694 vmcs_clear_bits(ctrl_field, ctrl_bit); 6695 if (field == GUEST_PAT) { 6696 vmx_set_test_stage(1); 6697 test_set_guest(guest_pat_main); 6698 } 6699 6700 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6701 /* Test PAT0..PAT7 fields */ 6702 for (j = 0; j < (i ? 8 : 1); j++) { 6703 val = i << j * 8; 6704 vmcs_write(field, val); 6705 if (field == HOST_PAT) { 6706 report_prefix_pushf("%s %lx", field_name, val); 6707 test_vmx_vmlaunch(0, false); 6708 report_prefix_pop(); 6709 6710 } else { // GUEST_PAT 6711 enter_guest_with_invalid_guest_state(); 6712 report_guest_pat_test("ENT_LOAD_PAT enabled", 6713 VMX_VMCALL, val); 6714 } 6715 } 6716 } 6717 6718 vmcs_set_bits(ctrl_field, ctrl_bit); 6719 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6720 /* Test PAT0..PAT7 fields */ 6721 for (j = 0; j < (i ? 8 : 1); j++) { 6722 val = i << j * 8; 6723 vmcs_write(field, val); 6724 6725 if (field == HOST_PAT) { 6726 report_prefix_pushf("%s %lx", field_name, val); 6727 if (i == 0x2 || i == 0x3 || i >= 0x8) 6728 error = 6729 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 6730 else 6731 error = 0; 6732 6733 test_vmx_vmlaunch(error, false); 6734 report_prefix_pop(); 6735 6736 } else { // GUEST_PAT 6737 if (i == 0x2 || i == 0x3 || i >= 0x8) { 6738 enter_guest_with_invalid_guest_state(); 6739 report_guest_pat_test("ENT_LOAD_PAT " 6740 "enabled", 6741 VMX_FAIL_STATE | 6742 VMX_ENTRY_FAILURE, 6743 val); 6744 } else { 6745 enter_guest(); 6746 report_guest_pat_test("ENT_LOAD_PAT " 6747 "enabled", 6748 VMX_VMCALL, 6749 val); 6750 } 6751 } 6752 6753 } 6754 } 6755 6756 if (field == GUEST_PAT) { 6757 /* 6758 * Let the guest finish execution 6759 */ 6760 vmx_set_test_stage(2); 6761 vmcs_write(field, pat_saved); 6762 enter_guest(); 6763 } 6764 6765 vmcs_write(ctrl_field, ctrl_saved); 6766 vmcs_write(field, pat_saved); 6767 } 6768 6769 /* 6770 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 6771 * for the IA32_PAT MSR must be one that could be written by WRMSR 6772 * without fault at CPL 0. Specifically, each of the 8 bytes in the 6773 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6774 * 6 (WB), or 7 (UC-). 6775 * 6776 * [Intel SDM] 6777 */ 6778 static void test_load_host_pat(void) 6779 { 6780 /* 6781 * "load IA32_PAT" VM-exit control 6782 */ 6783 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 6784 printf("\"Load-IA32-PAT\" exit control not supported\n"); 6785 return; 6786 } 6787 6788 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 6789 } 6790 6791 /* 6792 * Check that the virtual CPU checks the VMX Host State Area as 6793 * documented in the Intel SDM. 6794 */ 6795 static void vmx_host_state_area_test(void) 6796 { 6797 /* 6798 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 6799 * fail due to invalid guest state, should we make it that 6800 * far. 6801 */ 6802 vmcs_write(GUEST_RFLAGS, 0); 6803 6804 test_host_ctl_regs(); 6805 6806 test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); 6807 test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); 6808 6809 test_load_host_pat(); 6810 } 6811 6812 /* 6813 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 6814 * for the IA32_PAT MSR must be one that could be written by WRMSR 6815 * without fault at CPL 0. Specifically, each of the 8 bytes in the 6816 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6817 * 6 (WB), or 7 (UC-). 6818 * 6819 * [Intel SDM] 6820 */ 6821 static void test_load_guest_pat(void) 6822 { 6823 /* 6824 * "load IA32_PAT" VM-entry control 6825 */ 6826 if (!(ctrl_exit_rev.clr & ENT_LOAD_PAT)) { 6827 printf("\"Load-IA32-PAT\" entry control not supported\n"); 6828 return; 6829 } 6830 6831 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 6832 } 6833 6834 /* 6835 * Check that the virtual CPU checks the VMX Guest State Area as 6836 * documented in the Intel SDM. 6837 */ 6838 static void vmx_guest_state_area_test(void) 6839 { 6840 test_load_guest_pat(); 6841 } 6842 6843 static bool valid_vmcs_for_vmentry(void) 6844 { 6845 struct vmcs *current_vmcs = NULL; 6846 6847 if (vmcs_save(¤t_vmcs)) 6848 return false; 6849 6850 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 6851 } 6852 6853 static void try_vmentry_in_movss_shadow(void) 6854 { 6855 u32 vm_inst_err; 6856 u32 flags; 6857 bool early_failure = false; 6858 u32 expected_flags = X86_EFLAGS_FIXED; 6859 bool valid_vmcs = valid_vmcs_for_vmentry(); 6860 6861 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 6862 6863 /* 6864 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 6865 * unsupported VMCS component"). 6866 */ 6867 vmcs_write(~0u, 0); 6868 6869 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 6870 "vmwrite %%rsp, %%rdx;" 6871 "mov 0f, %%rax;" 6872 "mov %[host_rip], %%edx;" 6873 "vmwrite %%rax, %%rdx;" 6874 "mov $-1, %%ah;" 6875 "sahf;" 6876 "mov %%ss, %%ax;" 6877 "mov %%ax, %%ss;" 6878 "vmlaunch;" 6879 "mov $1, %[early_failure];" 6880 "0: lahf;" 6881 "movzbl %%ah, %[flags]" 6882 : [early_failure] "+r" (early_failure), 6883 [flags] "=&a" (flags) 6884 : [host_rsp] "i" (HOST_RSP), 6885 [host_rip] "i" (HOST_RIP) 6886 : "rdx", "cc", "memory"); 6887 vm_inst_err = vmcs_read(VMX_INST_ERROR); 6888 6889 report("Early VM-entry failure", early_failure); 6890 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 6891 expected_flags, flags); 6892 if (valid_vmcs) 6893 report("VM-instruction error is %d (actual %d)", 6894 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 6895 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 6896 } 6897 6898 static void vmentry_movss_shadow_test(void) 6899 { 6900 struct vmcs *orig_vmcs; 6901 6902 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 6903 6904 /* 6905 * Set the launched flag on the current VMCS to verify the correct 6906 * error priority, below. 6907 */ 6908 test_set_guest(v2_null_test_guest); 6909 enter_guest(); 6910 6911 /* 6912 * With bit 1 of the guest's RFLAGS clear, VM-entry should 6913 * fail due to invalid guest state (if we make it that far). 6914 */ 6915 vmcs_write(GUEST_RFLAGS, 0); 6916 6917 /* 6918 * "VM entry with events blocked by MOV SS" takes precedence over 6919 * "VMLAUNCH with non-clear VMCS." 6920 */ 6921 report_prefix_push("valid current-VMCS"); 6922 try_vmentry_in_movss_shadow(); 6923 report_prefix_pop(); 6924 6925 /* 6926 * VMfailInvalid takes precedence over "VM entry with events 6927 * blocked by MOV SS." 6928 */ 6929 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 6930 report_prefix_push("no current-VMCS"); 6931 try_vmentry_in_movss_shadow(); 6932 report_prefix_pop(); 6933 6934 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 6935 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 6936 } 6937 6938 #define X86_FEATURE_PCID (1 << 17) 6939 #define X86_FEATURE_MCE (1 << 7) 6940 6941 static int write_cr4_checking(unsigned long val) 6942 { 6943 asm volatile(ASM_TRY("1f") 6944 "mov %0, %%cr4\n\t" 6945 "1:": : "r" (val)); 6946 return exception_vector(); 6947 } 6948 6949 static void vmx_cr_load_test(void) 6950 { 6951 struct cpuid _cpuid = cpuid(1); 6952 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 6953 6954 if (!(_cpuid.c & X86_FEATURE_PCID)) { 6955 report_skip("PCID not detected"); 6956 return; 6957 } 6958 if (!(_cpuid.d & X86_FEATURE_MCE)) { 6959 report_skip("MCE not detected"); 6960 return; 6961 } 6962 6963 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 6964 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 6965 6966 /* Enable PCID for L1. */ 6967 cr4 |= X86_CR4_PCIDE; 6968 cr3 |= 0x1; 6969 TEST_ASSERT(!write_cr4_checking(cr4)); 6970 write_cr3(cr3); 6971 6972 test_set_guest(v2_null_test_guest); 6973 vmcs_write(HOST_CR4, cr4); 6974 vmcs_write(HOST_CR3, cr3); 6975 enter_guest(); 6976 6977 /* 6978 * No exception is expected. 6979 * 6980 * NB. KVM loads the last guest write to CR4 into CR4 read 6981 * shadow. In order to trigger an exit to KVM, we can set a 6982 * bit that was zero in the above CR4 write and is owned by 6983 * KVM. We choose to set CR4.MCE, which shall have no side 6984 * effect because normally no guest MCE (e.g., as the result 6985 * of bad memory) would happen during this test. 6986 */ 6987 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 6988 6989 /* Cleanup L1 state: disable PCID. */ 6990 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 6991 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 6992 } 6993 6994 static void vmx_nm_test_guest(void) 6995 { 6996 write_cr0(read_cr0() | X86_CR0_TS); 6997 asm volatile("fnop"); 6998 } 6999 7000 static void check_nm_exit(const char *test) 7001 { 7002 u32 reason = vmcs_read(EXI_REASON); 7003 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7004 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7005 NM_VECTOR; 7006 7007 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 7008 } 7009 7010 /* 7011 * This test checks that: 7012 * 7013 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7014 * a subsequent #NM VM-exit is reflected to L1. 7015 * 7016 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7017 * subsequent #NM VM-exit is reflected to L1. 7018 */ 7019 static void vmx_nm_test(void) 7020 { 7021 unsigned long cr0 = read_cr0(); 7022 7023 test_set_guest(vmx_nm_test_guest); 7024 7025 /* 7026 * L1 wants to intercept #NM exceptions encountered in L2. 7027 */ 7028 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7029 7030 /* 7031 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7032 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7033 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7034 */ 7035 vmcs_write(CR0_MASK, 0); 7036 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7037 enter_guest(); 7038 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7039 7040 /* 7041 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7042 * CR0.EM set. The fnop will still raise #NM, and L0 should 7043 * reflect the #NM VM-exit to L1. 7044 */ 7045 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7046 enter_guest(); 7047 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7048 7049 /* 7050 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7051 * CR0.EM clear. There will be no #NM, and the L2 guest should 7052 * exit normally. 7053 */ 7054 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7055 enter_guest(); 7056 } 7057 7058 bool vmx_pending_event_ipi_fired; 7059 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7060 { 7061 vmx_pending_event_ipi_fired = true; 7062 eoi(); 7063 } 7064 7065 bool vmx_pending_event_guest_run; 7066 static void vmx_pending_event_guest(void) 7067 { 7068 vmcall(); 7069 vmx_pending_event_guest_run = true; 7070 } 7071 7072 static void vmx_pending_event_test_core(bool guest_hlt) 7073 { 7074 int ipi_vector = 0xf1; 7075 7076 vmx_pending_event_ipi_fired = false; 7077 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7078 7079 vmx_pending_event_guest_run = false; 7080 test_set_guest(vmx_pending_event_guest); 7081 7082 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7083 7084 enter_guest(); 7085 skip_exit_vmcall(); 7086 7087 if (guest_hlt) 7088 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7089 7090 irq_disable(); 7091 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7092 APIC_DM_FIXED | ipi_vector, 7093 0); 7094 7095 enter_guest(); 7096 7097 assert_exit_reason(VMX_EXTINT); 7098 report("Guest did not run before host received IPI", 7099 !vmx_pending_event_guest_run); 7100 7101 irq_enable(); 7102 asm volatile ("nop"); 7103 irq_disable(); 7104 report("Got pending interrupt after IRQ enabled", 7105 vmx_pending_event_ipi_fired); 7106 7107 if (guest_hlt) 7108 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7109 7110 enter_guest(); 7111 report("Guest finished running when no interrupt", 7112 vmx_pending_event_guest_run); 7113 } 7114 7115 static void vmx_pending_event_test(void) 7116 { 7117 vmx_pending_event_test_core(false); 7118 } 7119 7120 static void vmx_pending_event_hlt_test(void) 7121 { 7122 vmx_pending_event_test_core(true); 7123 } 7124 7125 static int vmx_window_test_ud_count; 7126 7127 static void vmx_window_test_ud_handler(struct ex_regs *regs) 7128 { 7129 vmx_window_test_ud_count++; 7130 } 7131 7132 static void vmx_nmi_window_test_guest(void) 7133 { 7134 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 7135 7136 asm volatile("vmcall\n\t" 7137 "nop\n\t"); 7138 7139 handle_exception(UD_VECTOR, NULL); 7140 } 7141 7142 static void verify_nmi_window_exit(u64 rip) 7143 { 7144 u32 exit_reason = vmcs_read(EXI_REASON); 7145 7146 report("Exit reason (%d) is 'NMI window'", 7147 exit_reason == VMX_NMI_WINDOW, exit_reason); 7148 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7149 vmcs_read(GUEST_RIP), rip); 7150 report("Activity state (%ld) is 'ACTIVE'", 7151 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 7152 vmcs_read(GUEST_ACTV_STATE)); 7153 } 7154 7155 static void vmx_nmi_window_test(void) 7156 { 7157 u64 nop_addr; 7158 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 7159 7160 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 7161 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 7162 return; 7163 } 7164 7165 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 7166 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 7167 return; 7168 } 7169 7170 vmx_window_test_ud_count = 0; 7171 7172 report_prefix_push("NMI-window"); 7173 test_set_guest(vmx_nmi_window_test_guest); 7174 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 7175 enter_guest(); 7176 skip_exit_vmcall(); 7177 nop_addr = vmcs_read(GUEST_RIP); 7178 7179 /* 7180 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 7181 * RIP will not advance. 7182 */ 7183 report_prefix_push("active, no blocking"); 7184 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7185 enter_guest(); 7186 verify_nmi_window_exit(nop_addr); 7187 report_prefix_pop(); 7188 7189 /* 7190 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 7191 * a VM-exit on the next instruction after the nop. (The nop 7192 * is one byte.) 7193 */ 7194 report_prefix_push("active, blocking by MOV-SS"); 7195 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7196 enter_guest(); 7197 verify_nmi_window_exit(nop_addr + 1); 7198 report_prefix_pop(); 7199 7200 /* 7201 * Ask for "NMI-window exiting" (with event injection), and 7202 * expect a VM-exit after the event is injected. (RIP should 7203 * be at the address specified in the IDT entry for #UD.) 7204 */ 7205 report_prefix_push("active, no blocking, injecting #UD"); 7206 vmcs_write(ENT_INTR_INFO, 7207 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 7208 enter_guest(); 7209 verify_nmi_window_exit((u64)ud_fault_addr); 7210 report_prefix_pop(); 7211 7212 /* 7213 * Ask for "NMI-window exiting" with NMI blocking, and expect 7214 * a VM-exit after the next IRET (i.e. after the #UD handler 7215 * returns). So, RIP should be back at one byte past the nop. 7216 */ 7217 report_prefix_push("active, blocking by NMI"); 7218 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 7219 enter_guest(); 7220 verify_nmi_window_exit(nop_addr + 1); 7221 report("#UD handler executed once (actual %d times)", 7222 vmx_window_test_ud_count == 1, 7223 vmx_window_test_ud_count); 7224 report_prefix_pop(); 7225 7226 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7227 report_skip("CPU does not support activity state HLT."); 7228 } else { 7229 /* 7230 * Ask for "NMI-window exiting" when entering activity 7231 * state HLT, and expect an immediate VM-exit. RIP is 7232 * still one byte past the nop. 7233 */ 7234 report_prefix_push("halted, no blocking"); 7235 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7236 enter_guest(); 7237 verify_nmi_window_exit(nop_addr + 1); 7238 report_prefix_pop(); 7239 7240 /* 7241 * Ask for "NMI-window exiting" when entering activity 7242 * state HLT (with event injection), and expect a 7243 * VM-exit after the event is injected. (RIP should be 7244 * at the address specified in the IDT entry for #UD.) 7245 */ 7246 report_prefix_push("halted, no blocking, injecting #UD"); 7247 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7248 vmcs_write(ENT_INTR_INFO, 7249 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7250 UD_VECTOR); 7251 enter_guest(); 7252 verify_nmi_window_exit((u64)ud_fault_addr); 7253 report_prefix_pop(); 7254 } 7255 7256 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7257 enter_guest(); 7258 report_prefix_pop(); 7259 } 7260 7261 static void vmx_intr_window_test_guest(void) 7262 { 7263 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 7264 7265 /* 7266 * The two consecutive STIs are to ensure that only the first 7267 * one has a shadow. Note that NOP and STI are one byte 7268 * instructions. 7269 */ 7270 asm volatile("vmcall\n\t" 7271 "nop\n\t" 7272 "sti\n\t" 7273 "sti\n\t"); 7274 7275 handle_exception(UD_VECTOR, NULL); 7276 } 7277 7278 static void verify_intr_window_exit(u64 rip) 7279 { 7280 u32 exit_reason = vmcs_read(EXI_REASON); 7281 7282 report("Exit reason (%d) is 'interrupt window'", 7283 exit_reason == VMX_INTR_WINDOW, exit_reason); 7284 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7285 vmcs_read(GUEST_RIP), rip); 7286 report("Activity state (%ld) is 'ACTIVE'", 7287 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 7288 vmcs_read(GUEST_ACTV_STATE)); 7289 } 7290 7291 static void vmx_intr_window_test(void) 7292 { 7293 u64 vmcall_addr; 7294 u64 nop_addr; 7295 unsigned int orig_ud_gate_type; 7296 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 7297 7298 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 7299 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 7300 return; 7301 } 7302 7303 /* 7304 * Change the IDT entry for #UD from interrupt gate to trap gate, 7305 * so that it won't clear RFLAGS.IF. We don't want interrupts to 7306 * be disabled after vectoring a #UD. 7307 */ 7308 orig_ud_gate_type = boot_idt[UD_VECTOR].type; 7309 boot_idt[UD_VECTOR].type = 15; 7310 7311 report_prefix_push("interrupt-window"); 7312 test_set_guest(vmx_intr_window_test_guest); 7313 enter_guest(); 7314 assert_exit_reason(VMX_VMCALL); 7315 vmcall_addr = vmcs_read(GUEST_RIP); 7316 7317 /* 7318 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 7319 * no blocking; expect an immediate VM-exit. Note that we have 7320 * not advanced past the vmcall instruction yet, so RIP should 7321 * point to the vmcall instruction. 7322 */ 7323 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 7324 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7325 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 7326 enter_guest(); 7327 verify_intr_window_exit(vmcall_addr); 7328 report_prefix_pop(); 7329 7330 /* 7331 * Ask for "interrupt-window exiting" (with event injection) 7332 * with RFLAGS.IF set and no blocking; expect a VM-exit after 7333 * the event is injected. That is, RIP should should be at the 7334 * address specified in the IDT entry for #UD. 7335 */ 7336 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #UD"); 7337 vmcs_write(ENT_INTR_INFO, 7338 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 7339 vmcall_addr = vmcs_read(GUEST_RIP); 7340 enter_guest(); 7341 verify_intr_window_exit((u64)ud_fault_addr); 7342 report_prefix_pop(); 7343 7344 /* 7345 * Let the L2 guest run through the IRET, back to the VMCALL. 7346 * We have to clear the "interrupt-window exiting" 7347 * VM-execution control, or it would just keep causing 7348 * VM-exits. Then, advance past the VMCALL and set the 7349 * "interrupt-window exiting" VM-execution control again. 7350 */ 7351 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7352 enter_guest(); 7353 skip_exit_vmcall(); 7354 nop_addr = vmcs_read(GUEST_RIP); 7355 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7356 7357 /* 7358 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 7359 * RFLAGS.IF set, and expect a VM-exit on the next 7360 * instruction. (NOP is one byte.) 7361 */ 7362 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 7363 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7364 enter_guest(); 7365 verify_intr_window_exit(nop_addr + 1); 7366 report_prefix_pop(); 7367 7368 /* 7369 * Back up to the NOP and ask for "interrupt-window exiting" 7370 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 7371 * on the next instruction. (NOP is one byte.) 7372 */ 7373 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 7374 vmcs_write(GUEST_RIP, nop_addr); 7375 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 7376 enter_guest(); 7377 verify_intr_window_exit(nop_addr + 1); 7378 report_prefix_pop(); 7379 7380 /* 7381 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 7382 * and expect a VM-exit on the instruction following the STI 7383 * shadow. Only the first STI (which is one byte past the NOP) 7384 * should have a shadow. The second STI (which is two bytes 7385 * past the NOP) has no shadow. Therefore, the interrupt 7386 * window opens at three bytes past the NOP. 7387 */ 7388 report_prefix_push("active, RFLAGS.IF = 0"); 7389 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7390 enter_guest(); 7391 verify_intr_window_exit(nop_addr + 3); 7392 report_prefix_pop(); 7393 7394 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7395 report_skip("CPU does not support activity state HLT."); 7396 } else { 7397 /* 7398 * Ask for "interrupt-window exiting" when entering 7399 * activity state HLT, and expect an immediate 7400 * VM-exit. RIP is still three bytes past the nop. 7401 */ 7402 report_prefix_push("halted, no blocking"); 7403 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7404 enter_guest(); 7405 verify_intr_window_exit(nop_addr + 3); 7406 report_prefix_pop(); 7407 7408 /* 7409 * Ask for "interrupt-window exiting" when entering 7410 * activity state HLT (with event injection), and 7411 * expect a VM-exit after the event is injected. That 7412 * is, RIP should should be at the address specified 7413 * in the IDT entry for #UD. 7414 */ 7415 report_prefix_push("halted, no blocking, injecting #UD"); 7416 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7417 vmcs_write(ENT_INTR_INFO, 7418 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7419 UD_VECTOR); 7420 enter_guest(); 7421 verify_intr_window_exit((u64)ud_fault_addr); 7422 report_prefix_pop(); 7423 } 7424 7425 boot_idt[UD_VECTOR].type = orig_ud_gate_type; 7426 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7427 enter_guest(); 7428 report_prefix_pop(); 7429 } 7430 7431 #define GUEST_TSC_OFFSET (1u << 30) 7432 7433 static u64 guest_tsc; 7434 7435 static void vmx_store_tsc_test_guest(void) 7436 { 7437 guest_tsc = rdtsc(); 7438 } 7439 7440 /* 7441 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 7442 * list, the value saved is not subject to the TSC offset that is 7443 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 7444 */ 7445 static void vmx_store_tsc_test(void) 7446 { 7447 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 7448 u64 low, high; 7449 7450 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 7451 report_skip("'Use TSC offsetting' not supported"); 7452 return; 7453 } 7454 7455 test_set_guest(vmx_store_tsc_test_guest); 7456 7457 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 7458 vmcs_write(EXI_MSR_ST_CNT, 1); 7459 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 7460 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 7461 7462 low = rdtsc(); 7463 enter_guest(); 7464 high = rdtsc(); 7465 7466 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 7467 low + GUEST_TSC_OFFSET <= guest_tsc && 7468 guest_tsc <= high + GUEST_TSC_OFFSET, 7469 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 7470 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 7471 low <= msr_entry.value && msr_entry.value <= high, 7472 msr_entry.value, low, high); 7473 } 7474 7475 static void vmx_db_test_guest(void) 7476 { 7477 /* 7478 * For a hardware generated single-step #DB. 7479 */ 7480 asm volatile("vmcall;" 7481 "nop;" 7482 ".Lpost_nop:"); 7483 /* 7484 * ...in a MOVSS shadow, with pending debug exceptions. 7485 */ 7486 asm volatile("vmcall;" 7487 "nop;" 7488 ".Lpost_movss_nop:"); 7489 /* 7490 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 7491 * emulates it in software.) 7492 */ 7493 asm volatile("vmcall;" 7494 "wbinvd;" 7495 ".Lpost_wbinvd:"); 7496 /* 7497 * ...in a MOVSS shadow, with pending debug exceptions. 7498 */ 7499 asm volatile("vmcall;" 7500 "wbinvd;" 7501 ".Lpost_movss_wbinvd:"); 7502 /* 7503 * For a hardware generated single-step #DB in a transactional region. 7504 */ 7505 asm volatile("vmcall;" 7506 ".Lxbegin: xbegin .Lskip_rtm;" 7507 "xend;" 7508 ".Lskip_rtm:"); 7509 } 7510 7511 /* 7512 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 7513 * L2. No #DB is delivered and L2 continues to the next point of 7514 * interest. 7515 */ 7516 static void dismiss_db(void) 7517 { 7518 vmcs_write(GUEST_PENDING_DEBUG, 0); 7519 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7520 enter_guest(); 7521 } 7522 7523 /* 7524 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 7525 * Then throw away the #DB exception and resume L2. 7526 */ 7527 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 7528 void *expected_rip, u64 expected_exit_qual, 7529 u64 expected_dr6) 7530 { 7531 u32 reason = vmcs_read(EXI_REASON); 7532 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7533 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 7534 u64 guest_rip = vmcs_read(GUEST_RIP); 7535 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 7536 u64 dr6 = read_dr6(); 7537 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 7538 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 7539 7540 report("Expected #DB VM-exit", 7541 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 7542 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 7543 expected_rip, guest_rip); 7544 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 7545 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 7546 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 7547 expected_exit_qual == exit_qual, 7548 expected_exit_qual, exit_qual); 7549 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 7550 expected_dr6 == dr6, expected_dr6, dr6); 7551 dismiss_db(); 7552 } 7553 7554 /* 7555 * Assuming the guest has just exited on a VMCALL instruction, skip 7556 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 7557 * pending debug exceptions are non-zero, set the VMCS up as if the 7558 * previous instruction was a MOVSS that generated the indicated 7559 * pending debug exceptions. Then enter L2. 7560 */ 7561 static void single_step_guest(const char *test_name, u64 starting_dr6, 7562 u64 pending_debug_exceptions) 7563 { 7564 printf("\n%s\n", test_name); 7565 skip_exit_vmcall(); 7566 write_dr6(starting_dr6); 7567 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 7568 if (pending_debug_exceptions) { 7569 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 7570 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7571 } 7572 enter_guest(); 7573 } 7574 7575 /* 7576 * When L1 intercepts #DB, verify that a single-step trap clears 7577 * pending debug exceptions, populates the exit qualification field 7578 * properly, and that DR6 is not prematurely clobbered. In a 7579 * (simulated) MOVSS shadow, make sure that the pending debug 7580 * exception bits are properly accumulated into the exit qualification 7581 * field. 7582 */ 7583 static void vmx_db_test(void) 7584 { 7585 /* 7586 * We are going to set a few arbitrary bits in DR6 to verify that 7587 * (a) DR6 is not modified by an intercepted #DB, and 7588 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 7589 * the exit qualification field for a subsequent #DB exception. 7590 */ 7591 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 7592 extern char post_nop asm(".Lpost_nop"); 7593 extern char post_movss_nop asm(".Lpost_movss_nop"); 7594 extern char post_wbinvd asm(".Lpost_wbinvd"); 7595 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 7596 extern char xbegin asm(".Lxbegin"); 7597 extern char skip_rtm asm(".Lskip_rtm"); 7598 7599 /* 7600 * L1 wants to intercept #DB exceptions encountered in L2. 7601 */ 7602 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 7603 7604 /* 7605 * Start L2 and run it up to the first point of interest. 7606 */ 7607 test_set_guest(vmx_db_test_guest); 7608 enter_guest(); 7609 7610 /* 7611 * Hardware-delivered #DB trap for single-step sets the 7612 * standard that L0 has to follow for emulated instructions. 7613 */ 7614 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 7615 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 7616 7617 /* 7618 * Hardware-delivered #DB trap for single-step in MOVSS shadow 7619 * also sets the standard that L0 has to follow for emulated 7620 * instructions. Here, we establish the VMCS pending debug 7621 * exceptions to indicate that the simulated MOVSS triggered a 7622 * data breakpoint as well as the single-step trap. 7623 */ 7624 single_step_guest("Hardware delivered single-step in MOVSS shadow", 7625 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 7626 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 7627 starting_dr6); 7628 7629 /* 7630 * L0 synthesized #DB trap for single-step is buggy, because 7631 * kvm (a) clobbers DR6 too early, and (b) tries its best to 7632 * reconstitute the exit qualification from the prematurely 7633 * modified DR6, but fails miserably. 7634 */ 7635 single_step_guest("Software synthesized single-step", starting_dr6, 0); 7636 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 7637 7638 /* 7639 * L0 synthesized #DB trap for single-step in MOVSS shadow is 7640 * even worse, because L0 also leaves the pending debug 7641 * exceptions in the VMCS instead of accumulating them into 7642 * the exit qualification field for the #DB exception. 7643 */ 7644 single_step_guest("Software synthesized single-step in MOVSS shadow", 7645 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 7646 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 7647 starting_dr6); 7648 7649 /* 7650 * Optional RTM test for hardware that supports RTM, to 7651 * demonstrate that the current volume 3 of the SDM 7652 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 7653 * qualification for debug exceptions is not reserved. It is 7654 * set to 1 if a debug exception (#DB) or a breakpoint 7655 * exception (#BP) occurs inside an RTM region while advanced 7656 * debugging of RTM transactional regions is enabled. 7657 */ 7658 if (cpuid(7).b & BIT(11)) { 7659 vmcs_write(ENT_CONTROLS, 7660 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 7661 /* 7662 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 7663 * in the guest to enable advanced debugging of RTM 7664 * transactional regions. 7665 */ 7666 vmcs_write(GUEST_DR7, BIT(11)); 7667 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 7668 single_step_guest("Hardware delivered single-step in " 7669 "transactional region", starting_dr6, 0); 7670 check_db_exit(false, false, false, &xbegin, BIT(16), 7671 starting_dr6); 7672 } else { 7673 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 7674 enter_guest(); 7675 } 7676 } 7677 7678 static void enable_vid(void) 7679 { 7680 void *virtual_apic_page; 7681 7682 assert(cpu_has_apicv()); 7683 7684 disable_intercept_for_x2apic_msrs(); 7685 7686 virtual_apic_page = alloc_page(); 7687 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 7688 7689 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7690 7691 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 7692 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 7693 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 7694 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 7695 7696 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 7697 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 7698 } 7699 7700 static void trigger_ioapic_scan_thread(void *data) 7701 { 7702 /* Wait until other CPU entered L2 */ 7703 while (vmx_get_test_stage() != 1) 7704 ; 7705 7706 /* Trigger ioapic scan */ 7707 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 7708 vmx_set_test_stage(2); 7709 } 7710 7711 static void irq_79_handler_guest(isr_regs_t *regs) 7712 { 7713 eoi(); 7714 7715 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 7716 vmcall(); 7717 } 7718 7719 /* 7720 * Constant for num of busy-loop iterations after which 7721 * a timer interrupt should have happened in host 7722 */ 7723 #define TIMER_INTERRUPT_DELAY 100000000 7724 7725 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 7726 { 7727 handle_irq(0x79, irq_79_handler_guest); 7728 irq_enable(); 7729 7730 /* Signal to L1 CPU to trigger ioapic scan */ 7731 vmx_set_test_stage(1); 7732 /* Wait until L1 CPU to trigger ioapic scan */ 7733 while (vmx_get_test_stage() != 2) 7734 ; 7735 7736 /* 7737 * Wait for L0 timer interrupt to be raised while we run in L2 7738 * such that L0 will process the IOAPIC scan request before 7739 * resuming L2 7740 */ 7741 delay(TIMER_INTERRUPT_DELAY); 7742 7743 asm volatile ("int $0x79"); 7744 } 7745 7746 static void vmx_eoi_bitmap_ioapic_scan_test(void) 7747 { 7748 if (!cpu_has_apicv() || (cpu_count() < 2)) { 7749 report_skip(__func__); 7750 return; 7751 } 7752 7753 enable_vid(); 7754 7755 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 7756 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 7757 7758 /* 7759 * Launch L2. 7760 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 7761 * In case the reason isn't VMX_VMCALL, the asserion inside 7762 * skip_exit_vmcall() will fail. 7763 */ 7764 enter_guest(); 7765 skip_exit_vmcall(); 7766 7767 /* Let L2 finish */ 7768 enter_guest(); 7769 report(__func__, 1); 7770 } 7771 7772 #define HLT_WITH_RVI_VECTOR (0xf1) 7773 7774 bool vmx_hlt_with_rvi_guest_isr_fired; 7775 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 7776 { 7777 vmx_hlt_with_rvi_guest_isr_fired = true; 7778 eoi(); 7779 } 7780 7781 static void vmx_hlt_with_rvi_guest(void) 7782 { 7783 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 7784 7785 irq_enable(); 7786 asm volatile ("nop"); 7787 7788 vmcall(); 7789 } 7790 7791 static void vmx_hlt_with_rvi_test(void) 7792 { 7793 if (!cpu_has_apicv()) { 7794 report_skip(__func__); 7795 return; 7796 } 7797 7798 enable_vid(); 7799 7800 vmx_hlt_with_rvi_guest_isr_fired = false; 7801 test_set_guest(vmx_hlt_with_rvi_guest); 7802 7803 enter_guest(); 7804 skip_exit_vmcall(); 7805 7806 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7807 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 7808 enter_guest(); 7809 7810 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 7811 } 7812 7813 static void set_irq_line_thread(void *data) 7814 { 7815 /* Wait until other CPU entered L2 */ 7816 while (vmx_get_test_stage() != 1) 7817 ; 7818 7819 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 7820 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 7821 vmx_set_test_stage(2); 7822 } 7823 7824 static bool irq_78_handler_vmcall_before_eoi; 7825 static void irq_78_handler_guest(isr_regs_t *regs) 7826 { 7827 set_irq_line(0xf, 0); 7828 if (irq_78_handler_vmcall_before_eoi) 7829 vmcall(); 7830 eoi(); 7831 vmcall(); 7832 } 7833 7834 static void vmx_apic_passthrough_guest(void) 7835 { 7836 handle_irq(0x78, irq_78_handler_guest); 7837 irq_enable(); 7838 7839 /* If requested, wait for other CPU to trigger ioapic scan */ 7840 if (vmx_get_test_stage() < 1) { 7841 vmx_set_test_stage(1); 7842 while (vmx_get_test_stage() != 2) 7843 ; 7844 } 7845 7846 set_irq_line(0xf, 1); 7847 } 7848 7849 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 7850 { 7851 if (set_irq_line_from_thread && (cpu_count() < 2)) { 7852 report_skip(__func__); 7853 return; 7854 } 7855 7856 u64 cpu_ctrl_0 = CPU_SECONDARY; 7857 u64 cpu_ctrl_1 = 0; 7858 7859 disable_intercept_for_x2apic_msrs(); 7860 7861 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 7862 7863 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 7864 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 7865 7866 if (set_irq_line_from_thread) { 7867 irq_78_handler_vmcall_before_eoi = false; 7868 on_cpu_async(1, set_irq_line_thread, NULL); 7869 } else { 7870 irq_78_handler_vmcall_before_eoi = true; 7871 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 7872 vmx_set_test_stage(2); 7873 } 7874 test_set_guest(vmx_apic_passthrough_guest); 7875 7876 if (irq_78_handler_vmcall_before_eoi) { 7877 /* Before EOI remote_irr should still be set */ 7878 enter_guest(); 7879 skip_exit_vmcall(); 7880 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 7881 "IOAPIC pass-through: remote_irr=1 before EOI"); 7882 } 7883 7884 /* After EOI remote_irr should be cleared */ 7885 enter_guest(); 7886 skip_exit_vmcall(); 7887 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 7888 "IOAPIC pass-through: remote_irr=0 after EOI"); 7889 7890 /* Let L2 finish */ 7891 enter_guest(); 7892 report(__func__, 1); 7893 } 7894 7895 static void vmx_apic_passthrough_test(void) 7896 { 7897 vmx_apic_passthrough(false); 7898 } 7899 7900 static void vmx_apic_passthrough_thread_test(void) 7901 { 7902 vmx_apic_passthrough(true); 7903 } 7904 7905 enum vmcs_access { 7906 ACCESS_VMREAD, 7907 ACCESS_VMWRITE, 7908 ACCESS_NONE, 7909 }; 7910 7911 struct vmcs_shadow_test_common { 7912 enum vmcs_access op; 7913 enum Reason reason; 7914 u64 field; 7915 u64 value; 7916 u64 flags; 7917 u64 time; 7918 } l1_l2_common; 7919 7920 static inline u64 vmread_flags(u64 field, u64 *val) 7921 { 7922 u64 flags; 7923 7924 asm volatile ("vmread %2, %1; pushf; pop %0" 7925 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 7926 return flags & X86_EFLAGS_ALU; 7927 } 7928 7929 static inline u64 vmwrite_flags(u64 field, u64 val) 7930 { 7931 u64 flags; 7932 7933 asm volatile ("vmwrite %1, %2; pushf; pop %0" 7934 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 7935 return flags & X86_EFLAGS_ALU; 7936 } 7937 7938 static void vmx_vmcs_shadow_test_guest(void) 7939 { 7940 struct vmcs_shadow_test_common *c = &l1_l2_common; 7941 u64 start; 7942 7943 while (c->op != ACCESS_NONE) { 7944 start = rdtsc(); 7945 switch (c->op) { 7946 default: 7947 c->flags = -1ull; 7948 break; 7949 case ACCESS_VMREAD: 7950 c->flags = vmread_flags(c->field, &c->value); 7951 break; 7952 case ACCESS_VMWRITE: 7953 c->flags = vmwrite_flags(c->field, 0); 7954 break; 7955 } 7956 c->time = rdtsc() - start; 7957 vmcall(); 7958 } 7959 } 7960 7961 static u64 vmread_from_shadow(u64 field) 7962 { 7963 struct vmcs *primary; 7964 struct vmcs *shadow; 7965 u64 value; 7966 7967 TEST_ASSERT(!vmcs_save(&primary)); 7968 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 7969 TEST_ASSERT(!make_vmcs_current(shadow)); 7970 value = vmcs_read(field); 7971 TEST_ASSERT(!make_vmcs_current(primary)); 7972 return value; 7973 } 7974 7975 static u64 vmwrite_to_shadow(u64 field, u64 value) 7976 { 7977 struct vmcs *primary; 7978 struct vmcs *shadow; 7979 7980 TEST_ASSERT(!vmcs_save(&primary)); 7981 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 7982 TEST_ASSERT(!make_vmcs_current(shadow)); 7983 vmcs_write(field, value); 7984 value = vmcs_read(field); 7985 TEST_ASSERT(!make_vmcs_current(primary)); 7986 return value; 7987 } 7988 7989 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 7990 { 7991 struct vmcs_shadow_test_common *c = &l1_l2_common; 7992 7993 c->op = access; 7994 vmcs_write(VMX_INST_ERROR, 0); 7995 enter_guest(); 7996 c->reason = vmcs_read(EXI_REASON) & 0xffff; 7997 if (c->reason != VMX_VMCALL) { 7998 skip_exit_insn(); 7999 enter_guest(); 8000 } 8001 skip_exit_vmcall(); 8002 } 8003 8004 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 8005 { 8006 struct vmcs_shadow_test_common *c = &l1_l2_common; 8007 struct vmcs *shadow; 8008 u64 value; 8009 uintptr_t flags[2]; 8010 bool good_shadow; 8011 u32 vmx_inst_error; 8012 8013 report_prefix_pushf("field %lx", field); 8014 c->field = field; 8015 8016 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8017 if (shadow != (struct vmcs *)-1ull) { 8018 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 8019 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 8020 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 8021 } else { 8022 /* 8023 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 8024 * shadowed-fields should fail with setting RFLAGS.CF. 8025 */ 8026 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 8027 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 8028 good_shadow = false; 8029 } 8030 8031 /* Intercept both VMREAD and VMWRITE. */ 8032 report_prefix_push("no VMREAD/VMWRITE permission"); 8033 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 8034 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 8035 set_bit(field, bitmap[ACCESS_VMREAD]); 8036 set_bit(field, bitmap[ACCESS_VMWRITE]); 8037 } 8038 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8039 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8040 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8041 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8042 report_prefix_pop(); 8043 8044 if (field >> VMCS_FIELD_RESERVED_SHIFT) 8045 goto out; 8046 8047 /* Permit shadowed VMREAD. */ 8048 report_prefix_push("VMREAD permission only"); 8049 clear_bit(field, bitmap[ACCESS_VMREAD]); 8050 set_bit(field, bitmap[ACCESS_VMWRITE]); 8051 if (good_shadow) 8052 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8053 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8054 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8055 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8056 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8057 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8058 c->time); 8059 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8060 c->flags == flags[ACCESS_VMREAD], 8061 c->flags, flags[ACCESS_VMREAD]); 8062 if (good_shadow) 8063 report("value read from shadow (%lx) is as expected (%lx)", 8064 c->value == value, c->value, value); 8065 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8066 report("VMX_INST_ERROR (%d) is as expected (%d)", 8067 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8068 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8069 report_prefix_pop(); 8070 8071 /* Permit shadowed VMWRITE. */ 8072 report_prefix_push("VMWRITE permission only"); 8073 set_bit(field, bitmap[ACCESS_VMREAD]); 8074 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8075 if (good_shadow) 8076 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8077 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8078 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8079 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8080 c->time); 8081 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8082 c->flags == flags[ACCESS_VMREAD], 8083 c->flags, flags[ACCESS_VMREAD]); 8084 if (good_shadow) { 8085 value = vmread_from_shadow(field); 8086 report("shadow VMCS value (%lx) is as expected (%lx)", 8087 value == 0, value, 0ul); 8088 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8089 report("VMX_INST_ERROR (%d) is as expected (%d)", 8090 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8091 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8092 } 8093 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8094 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8095 report_prefix_pop(); 8096 8097 /* Permit shadowed VMREAD and VMWRITE. */ 8098 report_prefix_push("VMREAD and VMWRITE permission"); 8099 clear_bit(field, bitmap[ACCESS_VMREAD]); 8100 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8101 if (good_shadow) 8102 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8103 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8104 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8105 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8106 c->time); 8107 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8108 c->flags == flags[ACCESS_VMREAD], 8109 c->flags, flags[ACCESS_VMREAD]); 8110 if (good_shadow) { 8111 value = vmread_from_shadow(field); 8112 report("shadow VMCS value (%lx) is as expected (%lx)", 8113 value == 0, value, 0ul); 8114 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8115 report("VMX_INST_ERROR (%d) is as expected (%d)", 8116 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8117 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8118 } 8119 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8120 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8121 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8122 c->time); 8123 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8124 c->flags == flags[ACCESS_VMREAD], 8125 c->flags, flags[ACCESS_VMREAD]); 8126 if (good_shadow) 8127 report("value read from shadow (%lx) is as expected (%lx)", 8128 c->value == 0, c->value, 0ul); 8129 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8130 report("VMX_INST_ERROR (%d) is as expected (%d)", 8131 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8132 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8133 report_prefix_pop(); 8134 8135 out: 8136 report_prefix_pop(); 8137 } 8138 8139 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 8140 { 8141 unsigned base; 8142 unsigned index; 8143 unsigned bit; 8144 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 8145 8146 /* Run test on all possible valid VMCS fields */ 8147 for (base = 0; 8148 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 8149 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 8150 for (index = 0; index <= highest_index; index++) 8151 vmcs_shadow_test_field(bitmap, base + index); 8152 8153 /* 8154 * Run tests on some invalid VMCS fields 8155 * (Have reserved bit set). 8156 */ 8157 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 8158 vmcs_shadow_test_field(bitmap, (1ull << bit)); 8159 } 8160 8161 static void vmx_vmcs_shadow_test(void) 8162 { 8163 u8 *bitmap[2]; 8164 struct vmcs *shadow; 8165 8166 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 8167 printf("\t'Activate secondary controls' not supported.\n"); 8168 return; 8169 } 8170 8171 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 8172 printf("\t'VMCS shadowing' not supported.\n"); 8173 return; 8174 } 8175 8176 if (!(rdmsr(MSR_IA32_VMX_MISC) & 8177 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 8178 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 8179 return; 8180 } 8181 8182 test_set_guest(vmx_vmcs_shadow_test_guest); 8183 8184 bitmap[ACCESS_VMREAD] = alloc_page(); 8185 bitmap[ACCESS_VMWRITE] = alloc_page(); 8186 8187 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 8188 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 8189 8190 shadow = alloc_page(); 8191 shadow->hdr.revision_id = basic.revision; 8192 shadow->hdr.shadow_vmcs = 1; 8193 TEST_ASSERT(!vmcs_clear(shadow)); 8194 8195 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 8196 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 8197 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 8198 8199 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 8200 report_prefix_push("valid link pointer"); 8201 vmx_vmcs_shadow_test_body(bitmap); 8202 report_prefix_pop(); 8203 8204 vmcs_write(VMCS_LINK_PTR, -1ull); 8205 report_prefix_push("invalid link pointer"); 8206 vmx_vmcs_shadow_test_body(bitmap); 8207 report_prefix_pop(); 8208 8209 l1_l2_common.op = ACCESS_NONE; 8210 enter_guest(); 8211 } 8212 8213 8214 8215 static int invalid_msr_init(struct vmcs *vmcs) 8216 { 8217 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8218 printf("\tPreemption timer is not supported\n"); 8219 return VMX_TEST_EXIT; 8220 } 8221 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 8222 preempt_val = 10000000; 8223 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 8224 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 8225 8226 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 8227 printf("\tSave preemption value is not supported\n"); 8228 8229 vmcs_write(ENT_MSR_LD_CNT, 1); 8230 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 8231 8232 return VMX_TEST_START; 8233 } 8234 8235 8236 static void invalid_msr_main(void) 8237 { 8238 report("Invalid MSR load", 0); 8239 } 8240 8241 static int invalid_msr_exit_handler(void) 8242 { 8243 report("Invalid MSR load", 0); 8244 print_vmexit_info(); 8245 return VMX_TEST_EXIT; 8246 } 8247 8248 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 8249 { 8250 ulong reason; 8251 8252 reason = vmcs_read(EXI_REASON); 8253 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 8254 return VMX_TEST_VMEXIT; 8255 } 8256 8257 8258 #define TEST(name) { #name, .v2 = name } 8259 8260 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 8261 struct vmx_test vmx_tests[] = { 8262 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 8263 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 8264 { "preemption timer", preemption_timer_init, preemption_timer_main, 8265 preemption_timer_exit_handler, NULL, {0} }, 8266 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 8267 test_ctrl_pat_exit_handler, NULL, {0} }, 8268 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 8269 test_ctrl_efer_exit_handler, NULL, {0} }, 8270 { "CR shadowing", NULL, cr_shadowing_main, 8271 cr_shadowing_exit_handler, NULL, {0} }, 8272 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 8273 NULL, {0} }, 8274 { "instruction intercept", insn_intercept_init, insn_intercept_main, 8275 insn_intercept_exit_handler, NULL, {0} }, 8276 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 8277 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 8278 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 8279 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 8280 { "interrupt", interrupt_init, interrupt_main, 8281 interrupt_exit_handler, NULL, {0} }, 8282 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 8283 NULL, {0} }, 8284 { "MSR switch", msr_switch_init, msr_switch_main, 8285 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 8286 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 8287 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 8288 disable_rdtscp_exit_handler, NULL, {0} }, 8289 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 8290 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 8291 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 8292 exit_monitor_from_l2_handler, NULL, {0} }, 8293 { "invalid_msr", invalid_msr_init, invalid_msr_main, 8294 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 8295 /* Basic V2 tests. */ 8296 TEST(v2_null_test), 8297 TEST(v2_multiple_entries_test), 8298 TEST(fixture_test_case1), 8299 TEST(fixture_test_case2), 8300 /* Opcode tests. */ 8301 TEST(invvpid_test_v2), 8302 /* VM-entry tests */ 8303 TEST(vmx_controls_test), 8304 TEST(vmx_host_state_area_test), 8305 TEST(vmx_guest_state_area_test), 8306 TEST(vmentry_movss_shadow_test), 8307 /* APICv tests */ 8308 TEST(vmx_eoi_bitmap_ioapic_scan_test), 8309 TEST(vmx_hlt_with_rvi_test), 8310 TEST(apic_reg_virt_test), 8311 TEST(virt_x2apic_mode_test), 8312 /* APIC pass-through tests */ 8313 TEST(vmx_apic_passthrough_test), 8314 TEST(vmx_apic_passthrough_thread_test), 8315 /* VMCS Shadowing tests */ 8316 TEST(vmx_vmcs_shadow_test), 8317 /* Regression tests */ 8318 TEST(vmx_cr_load_test), 8319 TEST(vmx_nm_test), 8320 TEST(vmx_db_test), 8321 TEST(vmx_nmi_window_test), 8322 TEST(vmx_intr_window_test), 8323 TEST(vmx_pending_event_test), 8324 TEST(vmx_pending_event_hlt_test), 8325 TEST(vmx_store_tsc_test), 8326 /* EPT access tests. */ 8327 TEST(ept_access_test_not_present), 8328 TEST(ept_access_test_read_only), 8329 TEST(ept_access_test_write_only), 8330 TEST(ept_access_test_read_write), 8331 TEST(ept_access_test_execute_only), 8332 TEST(ept_access_test_read_execute), 8333 TEST(ept_access_test_write_execute), 8334 TEST(ept_access_test_read_write_execute), 8335 TEST(ept_access_test_reserved_bits), 8336 TEST(ept_access_test_ignored_bits), 8337 TEST(ept_access_test_paddr_not_present_ad_disabled), 8338 TEST(ept_access_test_paddr_not_present_ad_enabled), 8339 TEST(ept_access_test_paddr_read_only_ad_disabled), 8340 TEST(ept_access_test_paddr_read_only_ad_enabled), 8341 TEST(ept_access_test_paddr_read_write), 8342 TEST(ept_access_test_paddr_read_write_execute), 8343 TEST(ept_access_test_paddr_read_execute_ad_disabled), 8344 TEST(ept_access_test_paddr_read_execute_ad_enabled), 8345 TEST(ept_access_test_paddr_not_present_page_fault), 8346 TEST(ept_access_test_force_2m_page), 8347 { NULL, NULL, NULL, NULL, NULL, {0} }, 8348 }; 8349