1 #ifndef CFLAT_APIC_H 2 #define CFLAT_APIC_H 3 4 #include <stdint.h> 5 #include "apic-defs.h" 6 7 extern void *g_apic; 8 extern void *g_ioapic; 9 10 typedef struct { 11 uint8_t vector; 12 uint8_t delivery_mode:3; 13 uint8_t dest_mode:1; 14 uint8_t delivery_status:1; 15 uint8_t polarity:1; 16 uint8_t remote_irr:1; 17 uint8_t trig_mode:1; 18 uint8_t mask:1; 19 uint8_t reserve:7; 20 uint8_t reserved[4]; 21 uint8_t dest_id; 22 } ioapic_redir_entry_t; 23 24 typedef enum trigger_mode { 25 TRIGGER_EDGE = 0, 26 TRIGGER_LEVEL, 27 TRIGGER_MAX, 28 } trigger_mode_t; 29 30 void mask_pic_interrupts(void); 31 32 void eoi(void); 33 uint8_t apic_get_tpr(void); 34 void apic_set_tpr(uint8_t tpr); 35 36 void ioapic_write_redir(unsigned line, ioapic_redir_entry_t e); 37 void ioapic_write_reg(unsigned reg, uint32_t value); 38 ioapic_redir_entry_t ioapic_read_redir(unsigned line); 39 uint32_t ioapic_read_reg(unsigned reg); 40 41 void ioapic_set_redir(unsigned line, unsigned vec, 42 trigger_mode_t trig_mode); 43 44 void set_mask(unsigned line, int mask); 45 46 void set_irq_line(unsigned line, int val); 47 48 void enable_apic(void); 49 uint32_t apic_read(unsigned reg); 50 bool apic_read_bit(unsigned reg, int n); 51 void apic_write(unsigned reg, uint32_t val); 52 void apic_icr_write(uint32_t val, uint32_t dest); 53 uint32_t apic_id(void); 54 55 int enable_x2apic(void); 56 void disable_apic(void); 57 void reset_apic(void); 58 59 /* Converts byte-addressable APIC register offset to 4-byte offset. */ 60 static inline u32 apic_reg_index(u32 reg) 61 { 62 return reg >> 2; 63 } 64 65 static inline u32 x2apic_msr(u32 reg) 66 { 67 return APIC_BASE_MSR + (reg >> 4); 68 } 69 70 static inline bool x2apic_reg_reserved(u32 reg) 71 { 72 switch (reg) { 73 case 0x000 ... 0x010: 74 case 0x040 ... 0x070: 75 case 0x0c0: 76 case 0x0e0: 77 case 0x290 ... 0x2e0: 78 case 0x310: 79 case 0x3a0 ... 0x3d0: 80 case 0x3f0: 81 return true; 82 default: 83 return false; 84 } 85 } 86 87 #endif 88