Merge tag 'kvm-x86-2025.02.21' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

KVM-Unit-Tests x86 changes:

- Expand the per-CPU data+stack area to 12KiB per CPU to reduce the
probability

Merge tag 'kvm-x86-2025.02.21' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

KVM-Unit-Tests x86 changes:

- Expand the per-CPU data+stack area to 12KiB per CPU to reduce the
probability of tests overflowing their stack and clobbering pre-CPU
data.

- Add testcases for LA57 canonical checks.

- Add testcases for LAM.

- Add a smoke test to make sure KVM doesn't bleed split-lock #AC/#DB into
the guest.

- Fix many warts and bugs in the PMU test, and prepare it for PMU version 5
and beyond.

- Many misc fixes and cleanups.

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x86: Move SMP #defines from apic-defs.h to smp.h

Now that the __ASSEMBLY__ versus __ASSEMBLER_ mess is sorted out, move
the SMP related #defines from apic-defs.h to smp.h, and drop the comment
that

x86: Move SMP #defines from apic-defs.h to smp.h

Now that the __ASSEMBLY__ versus __ASSEMBLER_ mess is sorted out, move
the SMP related #defines from apic-defs.h to smp.h, and drop the comment
that explains the hackery.

Opportunistically make REALMODE_GDT_LOWMEM visible to assembly code as
well, and drop efistart64.S's local copy.

Link: https://lore.kernel.org/r/20250221233832.2251456-1-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

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Merge tag 'kvm-x86-2024.06.14' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new testcases:

- Add a testcase to verify that KVM doesn't inject a triple fault (or

Merge tag 'kvm-x86-2024.06.14' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new testcases:

- Add a testcase to verify that KVM doesn't inject a triple fault (or any
other "error") if a nested VM is run with an EP4TA pointing MMIO.

- Play nice with CR4.CET in test_vmxon_bad_cr()

- Force emulation when testing MSR_IA32_FLUSH_CMD to workaround an issue where
Skylake CPUs don't follow the architecturally defined behavior, and so that
the test doesn't break if/when new bits are supported by future CPUs.

- Rework the async #PF test to support IRQ-based page-ready notifications.

- Fix a variety of issues related to adaptive PEBS.

- Add several nested VMX tests for virtual interrupt delivery and posted
interrupts.

- Ensure PAT is loaded with the default value after the nVMX PAT tests
(failure to do so was causing tests to fail due to all memory being UC).

- Misc cleanups.

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nVMX: test nested "virtual-interrupt delivery"

Add test coverage for recognizing and delivering virtual interrupts via
VMX's "virtual-interrupt delivery" feature, in the following two scenarios:

nVMX: test nested "virtual-interrupt delivery"

Add test coverage for recognizing and delivering virtual interrupts via
VMX's "virtual-interrupt delivery" feature, in the following two scenarios:

1. There's a pending interrupt at VM-entry.
2. There's a pending interrupt during TPR virtualization.

Signed-off-by: Marc Orr (Google) <marc.orr@gmail.com>
Co-developed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Co-developed-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Jim Mattson <jmattson@google.com>
Link: https://lore.kernel.org/r/20231211185552.3856862-3-jmattson@google.com
[sean: omit from base 'vmx' test]
Signed-off-by: Sean Christopherson <seanjc@google.com>

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Merge tag 'kvm-x86-2023.09.01' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new testcases, and a few generic changes

- Fix a bug in runtime.bash that caused it t

Merge tag 'kvm-x86-2023.09.01' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new testcases, and a few generic changes

- Fix a bug in runtime.bash that caused it to mishandle "check" strings with
multiple entries, e.g. a test that depends on multiple module params
- Make the PMU tests depend on vPMU support being enabled in KVM
- Fix PMU's forced emulation test on CPUs with full-width writes
- Add a PMU testcase for measuring TSX transactional cycles
- Nested SVM testcase for virtual NMIs
- Move a pile of code to ASM_TRY() and "safe" helpers
- Set up the guest stack in the LBRV tests so that the tests don't fail if the
compiler decides to generate function calls in guest code
- Ignore the "mispredict" flag in nSVM's LBRV tests to fix false failures
- Clean up usage of helpers that disable interrupts, e.g. stop inserting
unnecessary nops
- Add helpers to dedup code for programming the APIC timer
- Fix a variety of bugs in nVMX testcases related to being a 64-bit host

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x86: add few helper functions for apic local timer

Add a few functions to apic.c to make it easier to enable and disable
the local apic timer.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Li

x86: add few helper functions for apic local timer

Add a few functions to apic.c to make it easier to enable and disable
the local apic timer.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Link: https://lore.kernel.org/r/20221122161152.293072-4-mlevitsk@redhat.com
[sean: massage comments, use C-style]
Signed-off-by: Sean Christopherson <seanjc@google.com>

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x86/apic: Refactor x2APIC reg helper to provide exact semantics

Refactor x2apic_reg_reserved() into get_x2apic_reg_semantics() and have
it provide the semantics for all registers. The full semantic

x86/apic: Refactor x2APIC reg helper to provide exact semantics

Refactor x2apic_reg_reserved() into get_x2apic_reg_semantics() and have
it provide the semantics for all registers. The full semantics will be
used by the MSR test to verify KVM correctly emulates all x2APIC MSRs.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20230107011737.577244-3-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86/apic: Refactor x2APIC reg helper to provide exact semantics

Refactor x2apic_reg_reserved() into get_x2apic_reg_semantics() and have
it provide the semantics for all registers. The full semantic

x86/apic: Refactor x2APIC reg helper to provide exact semantics

Refactor x2apic_reg_reserved() into get_x2apic_reg_semantics() and have
it provide the semantics for all registers. The full semantics will be
used by the MSR test to verify KVM correctly emulates all x2APIC MSRs.

No functional change intended.

Link: https://lore.kernel.org/r/20230107011737.577244-3-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

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x86: apic: Make xAPIC and I/O APIC pointers static

Make the pointers to the xAPIC and I/O APIC static as there are no users
outside of apic.c. Opportunistically use #defines for the default values

x86: apic: Make xAPIC and I/O APIC pointers static

Make the pointers to the xAPIC and I/O APIC static as there are no users
outside of apic.c. Opportunistically use #defines for the default values
instead of open coding magic numbers.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-9-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Always use legacy xAPIC to get APIC ID during TSS setup

Force use of xAPIC to retrieve the APIC ID during TSS setup to fix an
issue where an AP can switch apic_ops to point at x2apic_ops before

x86: Always use legacy xAPIC to get APIC ID during TSS setup

Force use of xAPIC to retrieve the APIC ID during TSS setup to fix an
issue where an AP can switch apic_ops to point at x2apic_ops before
setup_tss() completes, leading to a #GP and triple fault due to trying
to read an x2APIC MSR without x2APIC being enabled.

A future patch will make apic_ops a per-cpu pointer, but that's not of
any help for 32-bit, which uses the APIC ID to determine the GS selector,
i.e. 32-bit KUT has a chicken-and-egg problem. All setup_tss() callers
ensure the local APIC is in xAPIC mode, so just force use of xAPIC in
this case.

Fixes: 7e33895 ("x86: Move 32-bit GDT and TSS to desc.c")
Fixes: dbd3800 ("x86: Move 64-bit GDT and TSS to desc.c")
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: unify header guards

Standardize header guards to _ASMX86_HEADER_H_, _X86_HEADER_H_,
and X86_HEADER_H.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: David Hildenbrand <david@red

x86: unify header guards

Standardize header guards to _ASMX86_HEADER_H_, _X86_HEADER_H_,
and X86_HEADER_H.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210609143712.60933-8-cohuck@redhat.com>

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x86: vmx: Fix the check whether CMCI is supported

The logic of figuring out whether CMCI is supported is broken, causing
the CMCI accessing tests to fail on Skylake bare-metal.

Determine whether CM

x86: vmx: Fix the check whether CMCI is supported

The logic of figuring out whether CMCI is supported is broken, causing
the CMCI accessing tests to fail on Skylake bare-metal.

Determine whether CMCI is supported according to the maximum entries in
the LVT as encoded in the APIC version register.

Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Nadav Amit <namit@vmware.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Mark APR as reserved in x2APIC

Cc: Marc Orr <marcorr@google.com>
Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: APIC IDs might not be consecutive

APIC IDs do not have to be consecutive. Crease a map between logical CPU
identifiers and the physical APIC IDs for this matter and add a level of
indirection.

x86: APIC IDs might not be consecutive

APIC IDs do not have to be consecutive. Crease a map between logical CPU
identifiers and the physical APIC IDs for this matter and add a level of
indirection.

During boot, save in a bitmap the APIC IDs of the enabled CPU and use it
later when sending IPIs.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Test VMX's virtualize x2APIC mode w/ nested

This patch extends x86/vmx_tests.c to test enabling virtualize x2APIC
mode for nested VMX. The basic premises of the test is to pass values
between L1 and

Test VMX's virtualize x2APIC mode w/ nested

This patch extends x86/vmx_tests.c to test enabling virtualize x2APIC
mode for nested VMX. The basic premises of the test is to pass values
between L1 and L2 via the virtual APIC page. Emphasis is placed on
validating that L2 can never read/write L0's APIC registers, which would
be disastrous.

Note, this test was used to detect and fix the issue described in the
KVM patch titled "KVM: x86: nVMX: fix x2APIC VTPR read intercept".

Signed-off-by: Marc Orr <marcorr@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Test nested APIC-register virtualization

This patch adds a test to validate the APIC-register virtualization
execution control with nested virtualization. Specific test cases
include: APIC-access vi

Test nested APIC-register virtualization

This patch adds a test to validate the APIC-register virtualization
execution control with nested virtualization. Specific test cases
include: APIC-access virtualization, APIC-access virtualization with Use
TPR Shadow, and APIC-register virtualization.

Signed-off-by: Marc Orr <marcorr@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Enhance test of disabled APIC

The test now checks to see that the memory "behind" the APIC has
either bus error semantics (writes ignored, reads return all 1s) or
memory semantics, and that this mem

Enhance test of disabled APIC

The test now checks to see that the memory "behind" the APIC has
either bus error semantics (writes ignored, reads return all 1s) or
memory semantics, and that this memory is exposed when the APIC is
either disabled or in x2APIC mode. The test also checks to see that
scribbling on the memory "behind" the APIC has no effect on CR8 when
MMIO access to the APIC is disabled.

Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: lib: Rename set_ioapic_redir() to ioapic_set_redir()

This is consistent with the naming scheme of rest of ioapic utils.

Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sad

x86: lib: Rename set_ioapic_redir() to ioapic_set_redir()

This is consistent with the naming scheme of rest of ioapic utils.

Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-4-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: lib: Expose IOAPIC/APIC globals and utils to lib

Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhuk

x86: lib: Expose IOAPIC/APIC globals and utils to lib

Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-3-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: ioapic: generalize trigger mode

Move it out of x86/ioapic.c since it can be further re-used. Also,
renaming into TRIGGER_*.

Signed-off-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Paolo Bon

x86: ioapic: generalize trigger mode

Move it out of x86/ioapic.c since it can be further re-used. Also,
renaming into TRIGGER_*.

Signed-off-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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vmexit: add self-ipi speed tests

These are designed to test APICv and optimizations of KVM_REQ_EVENT.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: apic: APIC ID tests

KVM commit 49bd29ba1dbd ("KVM: x86: reset APIC ID when enabling LAPIC",
2016-07-12) fixed xAPIC ID value after reset.

QEMU commit 5232d00a041c ("target-i386: Implement CPUI

x86: apic: APIC ID tests

KVM commit 49bd29ba1dbd ("KVM: x86: reset APIC ID when enabling LAPIC",
2016-07-12) fixed xAPIC ID value after reset.

QEMU commit 5232d00a041c ("target-i386: Implement CPUID[0xB] (Extended
Topology Enumeration)", 2016-05-12) added initial x2APIC to CPUID.

KVM commit a92e2543d6a8 ("KVM: x86: use hardware-compatible format
for APIC ID register", 2016-07-12) changed internal format of APIC ID
register, so make sure that guest-visible APIC ID was not been affected.

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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ioapic: test TMR behavior

Test that TMR works right even if the virtual-APIC page is modified
by another processor. Either x2apic or xapic accesses are tested,
depending on whether x2apic is availa

ioapic: test TMR behavior

Test that TMR works right even if the virtual-APIC page is modified
by another processor. Either x2apic or xapic accesses are tested,
depending on whether x2apic is available.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Split APIC tests into IOAPIC/APIC tests

Split apart the APIC tests into constituent parts (IOAPIC and APIC tests).

Signed-off-by: Steve Rutherford <srutherford@google.com>
Message-Id: <1431482

x86: Split APIC tests into IOAPIC/APIC tests

Split apart the APIC tests into constituent parts (IOAPIC and APIC tests).

Signed-off-by: Steve Rutherford <srutherford@google.com>
Message-Id: <1431482143-28018-1-git-send-email-srutherford@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Initial commit from qemu-kvm.git kvm/test/

Signed-off-by: Avi Kivity <avi@redhat.com>