1 #ifndef _ASM_X86_MSR_INDEX_H 2 #define _ASM_X86_MSR_INDEX_H 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_SPEC_CTRL 0x00000048 36 #define MSR_IA32_PRED_CMD 0x00000049 37 38 #define MSR_IA32_PERFCTR0 0x000000c1 39 #define MSR_IA32_PERFCTR1 0x000000c2 40 #define MSR_FSB_FREQ 0x000000cd 41 42 #define MSR_MTRRcap 0x000000fe 43 #define MSR_IA32_BBL_CR_CTL 0x00000119 44 45 #define MSR_IA32_SYSENTER_CS 0x00000174 46 #define MSR_IA32_SYSENTER_ESP 0x00000175 47 #define MSR_IA32_SYSENTER_EIP 0x00000176 48 49 #define MSR_IA32_MCG_CAP 0x00000179 50 #define MSR_IA32_MCG_STATUS 0x0000017a 51 #define MSR_IA32_MCG_CTL 0x0000017b 52 53 #define MSR_IA32_PEBS_ENABLE 0x000003f1 54 #define MSR_IA32_DS_AREA 0x00000600 55 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 56 57 #define MSR_MTRRfix64K_00000 0x00000250 58 #define MSR_MTRRfix16K_80000 0x00000258 59 #define MSR_MTRRfix16K_A0000 0x00000259 60 #define MSR_MTRRfix4K_C0000 0x00000268 61 #define MSR_MTRRfix4K_C8000 0x00000269 62 #define MSR_MTRRfix4K_D0000 0x0000026a 63 #define MSR_MTRRfix4K_D8000 0x0000026b 64 #define MSR_MTRRfix4K_E0000 0x0000026c 65 #define MSR_MTRRfix4K_E8000 0x0000026d 66 #define MSR_MTRRfix4K_F0000 0x0000026e 67 #define MSR_MTRRfix4K_F8000 0x0000026f 68 #define MSR_MTRRdefType 0x000002ff 69 70 #define MSR_IA32_CR_PAT 0x00000277 71 72 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 73 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 74 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 75 #define MSR_IA32_LASTINTFROMIP 0x000001dd 76 #define MSR_IA32_LASTINTTOIP 0x000001de 77 78 /* DEBUGCTLMSR bits (others vary by model): */ 79 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 80 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 81 #define DEBUGCTLMSR_TR (1UL << 6) 82 #define DEBUGCTLMSR_BTS (1UL << 7) 83 #define DEBUGCTLMSR_BTINT (1UL << 8) 84 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 85 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 86 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 87 88 #define MSR_IA32_MC0_CTL 0x00000400 89 #define MSR_IA32_MC0_STATUS 0x00000401 90 #define MSR_IA32_MC0_ADDR 0x00000402 91 #define MSR_IA32_MC0_MISC 0x00000403 92 93 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 94 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 95 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 96 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 97 98 /* These are consecutive and not in the normal 4er MCE bank block */ 99 #define MSR_IA32_MC0_CTL2 0x00000280 100 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 101 102 #define CMCI_EN (1ULL << 30) 103 #define CMCI_THRESHOLD_MASK 0xffffULL 104 105 #define MSR_P6_PERFCTR0 0x000000c1 106 #define MSR_P6_PERFCTR1 0x000000c2 107 #define MSR_P6_EVNTSEL0 0x00000186 108 #define MSR_P6_EVNTSEL1 0x00000187 109 110 /* AMD64 MSRs. Not complete. See the architecture manual for a more 111 complete list. */ 112 113 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 114 #define MSR_AMD64_NB_CFG 0xc001001f 115 #define MSR_AMD64_PATCH_LOADER 0xc0010020 116 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 117 #define MSR_AMD64_OSVW_STATUS 0xc0010141 118 #define MSR_AMD64_DC_CFG 0xc0011022 119 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 120 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 121 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 122 #define MSR_AMD64_IBSOPCTL 0xc0011033 123 #define MSR_AMD64_IBSOPRIP 0xc0011034 124 #define MSR_AMD64_IBSOPDATA 0xc0011035 125 #define MSR_AMD64_IBSOPDATA2 0xc0011036 126 #define MSR_AMD64_IBSOPDATA3 0xc0011037 127 #define MSR_AMD64_IBSDCLINAD 0xc0011038 128 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 129 #define MSR_AMD64_IBSCTL 0xc001103a 130 131 /* Fam 10h MSRs */ 132 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 133 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 134 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 135 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 136 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 137 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 138 #define MSR_FAM10H_NODE_ID 0xc001100c 139 140 /* K8 MSRs */ 141 #define MSR_K8_TOP_MEM1 0xc001001a 142 #define MSR_K8_TOP_MEM2 0xc001001d 143 #define MSR_K8_SYSCFG 0xc0010010 144 #define MSR_K8_INT_PENDING_MSG 0xc0010055 145 /* C1E active bits in int pending message */ 146 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 147 #define MSR_K8_TSEG_ADDR 0xc0010112 148 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 149 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 150 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 151 152 /* K7 MSRs */ 153 #define MSR_K7_EVNTSEL0 0xc0010000 154 #define MSR_K7_PERFCTR0 0xc0010004 155 #define MSR_K7_EVNTSEL1 0xc0010001 156 #define MSR_K7_PERFCTR1 0xc0010005 157 #define MSR_K7_EVNTSEL2 0xc0010002 158 #define MSR_K7_PERFCTR2 0xc0010006 159 #define MSR_K7_EVNTSEL3 0xc0010003 160 #define MSR_K7_PERFCTR3 0xc0010007 161 #define MSR_K7_CLK_CTL 0xc001001b 162 #define MSR_K7_HWCR 0xc0010015 163 #define MSR_K7_FID_VID_CTL 0xc0010041 164 #define MSR_K7_FID_VID_STATUS 0xc0010042 165 166 /* K6 MSRs */ 167 #define MSR_K6_EFER 0xc0000080 168 #define MSR_K6_STAR 0xc0000081 169 #define MSR_K6_WHCR 0xc0000082 170 #define MSR_K6_UWCCR 0xc0000085 171 #define MSR_K6_EPMR 0xc0000086 172 #define MSR_K6_PSOR 0xc0000087 173 #define MSR_K6_PFIR 0xc0000088 174 175 /* Centaur-Hauls/IDT defined MSRs. */ 176 #define MSR_IDT_FCR1 0x00000107 177 #define MSR_IDT_FCR2 0x00000108 178 #define MSR_IDT_FCR3 0x00000109 179 #define MSR_IDT_FCR4 0x0000010a 180 181 #define MSR_IDT_MCR0 0x00000110 182 #define MSR_IDT_MCR1 0x00000111 183 #define MSR_IDT_MCR2 0x00000112 184 #define MSR_IDT_MCR3 0x00000113 185 #define MSR_IDT_MCR4 0x00000114 186 #define MSR_IDT_MCR5 0x00000115 187 #define MSR_IDT_MCR6 0x00000116 188 #define MSR_IDT_MCR7 0x00000117 189 #define MSR_IDT_MCR_CTRL 0x00000120 190 191 /* VIA Cyrix defined MSRs*/ 192 #define MSR_VIA_FCR 0x00001107 193 #define MSR_VIA_LONGHAUL 0x0000110a 194 #define MSR_VIA_RNG 0x0000110b 195 #define MSR_VIA_BCR2 0x00001147 196 197 /* Transmeta defined MSRs */ 198 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 199 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 200 #define MSR_TMTA_LRTI_READOUT 0x80868018 201 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 202 203 /* Intel defined MSRs. */ 204 #define MSR_IA32_P5_MC_ADDR 0x00000000 205 #define MSR_IA32_P5_MC_TYPE 0x00000001 206 #define MSR_IA32_TSC 0x00000010 207 #define MSR_IA32_PLATFORM_ID 0x00000017 208 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 209 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 210 #define MSR_IA32_TSC_ADJUST 0x0000003b 211 212 #define FEATURE_CONTROL_LOCKED (1<<0) 213 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 214 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 215 216 #define MSR_IA32_APICBASE 0x0000001b 217 #define MSR_IA32_APICBASE_BSP (1<<8) 218 #define MSR_IA32_APICBASE_ENABLE (1<<11) 219 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 220 221 #define MSR_IA32_UCODE_WRITE 0x00000079 222 #define MSR_IA32_UCODE_REV 0x0000008b 223 224 #define MSR_IA32_PERF_STATUS 0x00000198 225 #define MSR_IA32_PERF_CTL 0x00000199 226 227 #define MSR_IA32_MPERF 0x000000e7 228 #define MSR_IA32_APERF 0x000000e8 229 230 #define MSR_IA32_THERM_CONTROL 0x0000019a 231 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 232 233 #define THERM_INT_LOW_ENABLE (1 << 0) 234 #define THERM_INT_HIGH_ENABLE (1 << 1) 235 236 #define MSR_IA32_THERM_STATUS 0x0000019c 237 238 #define THERM_STATUS_PROCHOT (1 << 0) 239 240 #define MSR_THERM2_CTL 0x0000019d 241 242 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 243 244 #define MSR_IA32_MISC_ENABLE 0x000001a0 245 246 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 247 248 /* MISC_ENABLE bits: architectural */ 249 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 250 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 251 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 252 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 253 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 254 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 255 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 256 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 257 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 258 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 259 260 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 261 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 262 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 263 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 264 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 265 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 266 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 267 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 268 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 269 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 270 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 271 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 272 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 273 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 274 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 275 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 276 277 /* P4/Xeon+ specific */ 278 #define MSR_IA32_MCG_EAX 0x00000180 279 #define MSR_IA32_MCG_EBX 0x00000181 280 #define MSR_IA32_MCG_ECX 0x00000182 281 #define MSR_IA32_MCG_EDX 0x00000183 282 #define MSR_IA32_MCG_ESI 0x00000184 283 #define MSR_IA32_MCG_EDI 0x00000185 284 #define MSR_IA32_MCG_EBP 0x00000186 285 #define MSR_IA32_MCG_ESP 0x00000187 286 #define MSR_IA32_MCG_EFLAGS 0x00000188 287 #define MSR_IA32_MCG_EIP 0x00000189 288 #define MSR_IA32_MCG_RESERVED 0x0000018a 289 290 /* Pentium IV performance counter MSRs */ 291 #define MSR_P4_BPU_PERFCTR0 0x00000300 292 #define MSR_P4_BPU_PERFCTR1 0x00000301 293 #define MSR_P4_BPU_PERFCTR2 0x00000302 294 #define MSR_P4_BPU_PERFCTR3 0x00000303 295 #define MSR_P4_MS_PERFCTR0 0x00000304 296 #define MSR_P4_MS_PERFCTR1 0x00000305 297 #define MSR_P4_MS_PERFCTR2 0x00000306 298 #define MSR_P4_MS_PERFCTR3 0x00000307 299 #define MSR_P4_FLAME_PERFCTR0 0x00000308 300 #define MSR_P4_FLAME_PERFCTR1 0x00000309 301 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 302 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 303 #define MSR_P4_IQ_PERFCTR0 0x0000030c 304 #define MSR_P4_IQ_PERFCTR1 0x0000030d 305 #define MSR_P4_IQ_PERFCTR2 0x0000030e 306 #define MSR_P4_IQ_PERFCTR3 0x0000030f 307 #define MSR_P4_IQ_PERFCTR4 0x00000310 308 #define MSR_P4_IQ_PERFCTR5 0x00000311 309 #define MSR_P4_BPU_CCCR0 0x00000360 310 #define MSR_P4_BPU_CCCR1 0x00000361 311 #define MSR_P4_BPU_CCCR2 0x00000362 312 #define MSR_P4_BPU_CCCR3 0x00000363 313 #define MSR_P4_MS_CCCR0 0x00000364 314 #define MSR_P4_MS_CCCR1 0x00000365 315 #define MSR_P4_MS_CCCR2 0x00000366 316 #define MSR_P4_MS_CCCR3 0x00000367 317 #define MSR_P4_FLAME_CCCR0 0x00000368 318 #define MSR_P4_FLAME_CCCR1 0x00000369 319 #define MSR_P4_FLAME_CCCR2 0x0000036a 320 #define MSR_P4_FLAME_CCCR3 0x0000036b 321 #define MSR_P4_IQ_CCCR0 0x0000036c 322 #define MSR_P4_IQ_CCCR1 0x0000036d 323 #define MSR_P4_IQ_CCCR2 0x0000036e 324 #define MSR_P4_IQ_CCCR3 0x0000036f 325 #define MSR_P4_IQ_CCCR4 0x00000370 326 #define MSR_P4_IQ_CCCR5 0x00000371 327 #define MSR_P4_ALF_ESCR0 0x000003ca 328 #define MSR_P4_ALF_ESCR1 0x000003cb 329 #define MSR_P4_BPU_ESCR0 0x000003b2 330 #define MSR_P4_BPU_ESCR1 0x000003b3 331 #define MSR_P4_BSU_ESCR0 0x000003a0 332 #define MSR_P4_BSU_ESCR1 0x000003a1 333 #define MSR_P4_CRU_ESCR0 0x000003b8 334 #define MSR_P4_CRU_ESCR1 0x000003b9 335 #define MSR_P4_CRU_ESCR2 0x000003cc 336 #define MSR_P4_CRU_ESCR3 0x000003cd 337 #define MSR_P4_CRU_ESCR4 0x000003e0 338 #define MSR_P4_CRU_ESCR5 0x000003e1 339 #define MSR_P4_DAC_ESCR0 0x000003a8 340 #define MSR_P4_DAC_ESCR1 0x000003a9 341 #define MSR_P4_FIRM_ESCR0 0x000003a4 342 #define MSR_P4_FIRM_ESCR1 0x000003a5 343 #define MSR_P4_FLAME_ESCR0 0x000003a6 344 #define MSR_P4_FLAME_ESCR1 0x000003a7 345 #define MSR_P4_FSB_ESCR0 0x000003a2 346 #define MSR_P4_FSB_ESCR1 0x000003a3 347 #define MSR_P4_IQ_ESCR0 0x000003ba 348 #define MSR_P4_IQ_ESCR1 0x000003bb 349 #define MSR_P4_IS_ESCR0 0x000003b4 350 #define MSR_P4_IS_ESCR1 0x000003b5 351 #define MSR_P4_ITLB_ESCR0 0x000003b6 352 #define MSR_P4_ITLB_ESCR1 0x000003b7 353 #define MSR_P4_IX_ESCR0 0x000003c8 354 #define MSR_P4_IX_ESCR1 0x000003c9 355 #define MSR_P4_MOB_ESCR0 0x000003aa 356 #define MSR_P4_MOB_ESCR1 0x000003ab 357 #define MSR_P4_MS_ESCR0 0x000003c0 358 #define MSR_P4_MS_ESCR1 0x000003c1 359 #define MSR_P4_PMH_ESCR0 0x000003ac 360 #define MSR_P4_PMH_ESCR1 0x000003ad 361 #define MSR_P4_RAT_ESCR0 0x000003bc 362 #define MSR_P4_RAT_ESCR1 0x000003bd 363 #define MSR_P4_SAAT_ESCR0 0x000003ae 364 #define MSR_P4_SAAT_ESCR1 0x000003af 365 #define MSR_P4_SSU_ESCR0 0x000003be 366 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 367 368 #define MSR_P4_TBPU_ESCR0 0x000003c2 369 #define MSR_P4_TBPU_ESCR1 0x000003c3 370 #define MSR_P4_TC_ESCR0 0x000003c4 371 #define MSR_P4_TC_ESCR1 0x000003c5 372 #define MSR_P4_U2L_ESCR0 0x000003b0 373 #define MSR_P4_U2L_ESCR1 0x000003b1 374 375 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 376 377 /* Intel Core-based CPU performance counters */ 378 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 379 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 380 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 381 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 382 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 383 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 384 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 385 386 /* Geode defined MSRs */ 387 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 388 389 /* Intel VT MSRs */ 390 #define MSR_IA32_VMX_BASIC 0x00000480 391 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 392 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 393 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 394 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 395 #define MSR_IA32_VMX_MISC 0x00000485 396 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 397 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 398 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 399 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 400 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 401 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 402 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 403 #define MSR_IA32_VMX_TRUE_PIN 0x0000048d 404 #define MSR_IA32_VMX_TRUE_PROC 0x0000048e 405 #define MSR_IA32_VMX_TRUE_EXIT 0x0000048f 406 #define MSR_IA32_VMX_TRUE_ENTRY 0x00000490 407 408 /* MSR_IA32_VMX_MISC bits */ 409 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 410 411 #define MSR_IA32_TSCDEADLINE 0x000006e0 412 413 /* AMD-V MSRs */ 414 415 #define MSR_VM_CR 0xc0010114 416 #define MSR_VM_IGNNE 0xc0010115 417 #define MSR_VM_HSAVE_PA 0xc0010117 418 419 #endif /* _ASM_X86_MSR_INDEX_H */ 420