1 #ifndef __VMX_H 2 #define __VMX_H 3 4 #include "libcflat.h" 5 #include "processor.h" 6 #include "bitops.h" 7 #include "asm/page.h" 8 #include "asm/io.h" 9 10 struct vmcs { 11 u32 revision_id; /* vmcs revision identifier */ 12 u32 abort; /* VMX-abort indicator */ 13 /* VMCS data */ 14 char data[0]; 15 }; 16 17 struct invvpid_operand { 18 u64 vpid; 19 u64 gla; 20 }; 21 22 struct regs { 23 u64 rax; 24 u64 rcx; 25 u64 rdx; 26 u64 rbx; 27 u64 cr2; 28 u64 rbp; 29 u64 rsi; 30 u64 rdi; 31 u64 r8; 32 u64 r9; 33 u64 r10; 34 u64 r11; 35 u64 r12; 36 u64 r13; 37 u64 r14; 38 u64 r15; 39 u64 rflags; 40 }; 41 42 struct vmentry_failure { 43 /* Did a vmlaunch or vmresume fail? */ 44 bool vmlaunch; 45 /* Instruction mnemonic (for convenience). */ 46 const char *instr; 47 /* Did the instruction return right away, or did we jump to HOST_RIP? */ 48 bool early; 49 /* Contents of [re]flags after failed entry. */ 50 unsigned long flags; 51 }; 52 53 struct vmx_test { 54 const char *name; 55 int (*init)(struct vmcs *vmcs); 56 void (*guest_main)(void); 57 int (*exit_handler)(void); 58 void (*syscall_handler)(u64 syscall_no); 59 struct regs guest_regs; 60 int (*entry_failure_handler)(struct vmentry_failure *failure); 61 struct vmcs *vmcs; 62 int exits; 63 /* Alternative test interface. */ 64 void (*v2)(void); 65 }; 66 67 union vmx_basic { 68 u64 val; 69 struct { 70 u32 revision; 71 u32 size:13, 72 reserved1: 3, 73 width:1, 74 dual:1, 75 type:4, 76 insouts:1, 77 ctrl:1, 78 reserved2:8; 79 }; 80 }; 81 82 union vmx_ctrl_msr { 83 u64 val; 84 struct { 85 u32 set, clr; 86 }; 87 }; 88 89 union vmx_ept_vpid { 90 u64 val; 91 struct { 92 u32:16, 93 super:2, 94 : 2, 95 invept:1, 96 : 11; 97 u32 invvpid:1; 98 }; 99 }; 100 101 enum Encoding { 102 /* 16-Bit Control Fields */ 103 VPID = 0x0000ul, 104 /* Posted-interrupt notification vector */ 105 PINV = 0x0002ul, 106 /* EPTP index */ 107 EPTP_IDX = 0x0004ul, 108 109 /* 16-Bit Guest State Fields */ 110 GUEST_SEL_ES = 0x0800ul, 111 GUEST_SEL_CS = 0x0802ul, 112 GUEST_SEL_SS = 0x0804ul, 113 GUEST_SEL_DS = 0x0806ul, 114 GUEST_SEL_FS = 0x0808ul, 115 GUEST_SEL_GS = 0x080aul, 116 GUEST_SEL_LDTR = 0x080cul, 117 GUEST_SEL_TR = 0x080eul, 118 GUEST_INT_STATUS = 0x0810ul, 119 GUEST_PML_INDEX = 0x0812ul, 120 121 /* 16-Bit Host State Fields */ 122 HOST_SEL_ES = 0x0c00ul, 123 HOST_SEL_CS = 0x0c02ul, 124 HOST_SEL_SS = 0x0c04ul, 125 HOST_SEL_DS = 0x0c06ul, 126 HOST_SEL_FS = 0x0c08ul, 127 HOST_SEL_GS = 0x0c0aul, 128 HOST_SEL_TR = 0x0c0cul, 129 130 /* 64-Bit Control Fields */ 131 IO_BITMAP_A = 0x2000ul, 132 IO_BITMAP_B = 0x2002ul, 133 MSR_BITMAP = 0x2004ul, 134 EXIT_MSR_ST_ADDR = 0x2006ul, 135 EXIT_MSR_LD_ADDR = 0x2008ul, 136 ENTER_MSR_LD_ADDR = 0x200aul, 137 VMCS_EXEC_PTR = 0x200cul, 138 TSC_OFFSET = 0x2010ul, 139 TSC_OFFSET_HI = 0x2011ul, 140 APIC_VIRT_ADDR = 0x2012ul, 141 APIC_ACCS_ADDR = 0x2014ul, 142 EPTP = 0x201aul, 143 EPTP_HI = 0x201bul, 144 EOI_EXIT_BITMAP0 = 0x201cul, 145 EOI_EXIT_BITMAP1 = 0x201eul, 146 EOI_EXIT_BITMAP2 = 0x2020ul, 147 EOI_EXIT_BITMAP3 = 0x2022ul, 148 PMLADDR = 0x200eul, 149 PMLADDR_HI = 0x200ful, 150 151 152 /* 64-Bit Readonly Data Field */ 153 INFO_PHYS_ADDR = 0x2400ul, 154 155 /* 64-Bit Guest State */ 156 VMCS_LINK_PTR = 0x2800ul, 157 VMCS_LINK_PTR_HI = 0x2801ul, 158 GUEST_DEBUGCTL = 0x2802ul, 159 GUEST_DEBUGCTL_HI = 0x2803ul, 160 GUEST_EFER = 0x2806ul, 161 GUEST_PAT = 0x2804ul, 162 GUEST_PERF_GLOBAL_CTRL = 0x2808ul, 163 GUEST_PDPTE = 0x280aul, 164 165 /* 64-Bit Host State */ 166 HOST_PAT = 0x2c00ul, 167 HOST_EFER = 0x2c02ul, 168 HOST_PERF_GLOBAL_CTRL = 0x2c04ul, 169 170 /* 32-Bit Control Fields */ 171 PIN_CONTROLS = 0x4000ul, 172 CPU_EXEC_CTRL0 = 0x4002ul, 173 EXC_BITMAP = 0x4004ul, 174 PF_ERROR_MASK = 0x4006ul, 175 PF_ERROR_MATCH = 0x4008ul, 176 CR3_TARGET_COUNT = 0x400aul, 177 EXI_CONTROLS = 0x400cul, 178 EXI_MSR_ST_CNT = 0x400eul, 179 EXI_MSR_LD_CNT = 0x4010ul, 180 ENT_CONTROLS = 0x4012ul, 181 ENT_MSR_LD_CNT = 0x4014ul, 182 ENT_INTR_INFO = 0x4016ul, 183 ENT_INTR_ERROR = 0x4018ul, 184 ENT_INST_LEN = 0x401aul, 185 TPR_THRESHOLD = 0x401cul, 186 CPU_EXEC_CTRL1 = 0x401eul, 187 188 /* 32-Bit R/O Data Fields */ 189 VMX_INST_ERROR = 0x4400ul, 190 EXI_REASON = 0x4402ul, 191 EXI_INTR_INFO = 0x4404ul, 192 EXI_INTR_ERROR = 0x4406ul, 193 IDT_VECT_INFO = 0x4408ul, 194 IDT_VECT_ERROR = 0x440aul, 195 EXI_INST_LEN = 0x440cul, 196 EXI_INST_INFO = 0x440eul, 197 198 /* 32-Bit Guest State Fields */ 199 GUEST_LIMIT_ES = 0x4800ul, 200 GUEST_LIMIT_CS = 0x4802ul, 201 GUEST_LIMIT_SS = 0x4804ul, 202 GUEST_LIMIT_DS = 0x4806ul, 203 GUEST_LIMIT_FS = 0x4808ul, 204 GUEST_LIMIT_GS = 0x480aul, 205 GUEST_LIMIT_LDTR = 0x480cul, 206 GUEST_LIMIT_TR = 0x480eul, 207 GUEST_LIMIT_GDTR = 0x4810ul, 208 GUEST_LIMIT_IDTR = 0x4812ul, 209 GUEST_AR_ES = 0x4814ul, 210 GUEST_AR_CS = 0x4816ul, 211 GUEST_AR_SS = 0x4818ul, 212 GUEST_AR_DS = 0x481aul, 213 GUEST_AR_FS = 0x481cul, 214 GUEST_AR_GS = 0x481eul, 215 GUEST_AR_LDTR = 0x4820ul, 216 GUEST_AR_TR = 0x4822ul, 217 GUEST_INTR_STATE = 0x4824ul, 218 GUEST_ACTV_STATE = 0x4826ul, 219 GUEST_SMBASE = 0x4828ul, 220 GUEST_SYSENTER_CS = 0x482aul, 221 PREEMPT_TIMER_VALUE = 0x482eul, 222 223 /* 32-Bit Host State Fields */ 224 HOST_SYSENTER_CS = 0x4c00ul, 225 226 /* Natural-Width Control Fields */ 227 CR0_MASK = 0x6000ul, 228 CR4_MASK = 0x6002ul, 229 CR0_READ_SHADOW = 0x6004ul, 230 CR4_READ_SHADOW = 0x6006ul, 231 CR3_TARGET_0 = 0x6008ul, 232 CR3_TARGET_1 = 0x600aul, 233 CR3_TARGET_2 = 0x600cul, 234 CR3_TARGET_3 = 0x600eul, 235 236 /* Natural-Width R/O Data Fields */ 237 EXI_QUALIFICATION = 0x6400ul, 238 IO_RCX = 0x6402ul, 239 IO_RSI = 0x6404ul, 240 IO_RDI = 0x6406ul, 241 IO_RIP = 0x6408ul, 242 GUEST_LINEAR_ADDRESS = 0x640aul, 243 244 /* Natural-Width Guest State Fields */ 245 GUEST_CR0 = 0x6800ul, 246 GUEST_CR3 = 0x6802ul, 247 GUEST_CR4 = 0x6804ul, 248 GUEST_BASE_ES = 0x6806ul, 249 GUEST_BASE_CS = 0x6808ul, 250 GUEST_BASE_SS = 0x680aul, 251 GUEST_BASE_DS = 0x680cul, 252 GUEST_BASE_FS = 0x680eul, 253 GUEST_BASE_GS = 0x6810ul, 254 GUEST_BASE_LDTR = 0x6812ul, 255 GUEST_BASE_TR = 0x6814ul, 256 GUEST_BASE_GDTR = 0x6816ul, 257 GUEST_BASE_IDTR = 0x6818ul, 258 GUEST_DR7 = 0x681aul, 259 GUEST_RSP = 0x681cul, 260 GUEST_RIP = 0x681eul, 261 GUEST_RFLAGS = 0x6820ul, 262 GUEST_PENDING_DEBUG = 0x6822ul, 263 GUEST_SYSENTER_ESP = 0x6824ul, 264 GUEST_SYSENTER_EIP = 0x6826ul, 265 266 /* Natural-Width Host State Fields */ 267 HOST_CR0 = 0x6c00ul, 268 HOST_CR3 = 0x6c02ul, 269 HOST_CR4 = 0x6c04ul, 270 HOST_BASE_FS = 0x6c06ul, 271 HOST_BASE_GS = 0x6c08ul, 272 HOST_BASE_TR = 0x6c0aul, 273 HOST_BASE_GDTR = 0x6c0cul, 274 HOST_BASE_IDTR = 0x6c0eul, 275 HOST_SYSENTER_ESP = 0x6c10ul, 276 HOST_SYSENTER_EIP = 0x6c12ul, 277 HOST_RSP = 0x6c14ul, 278 HOST_RIP = 0x6c16ul 279 }; 280 281 #define VMX_ENTRY_FAILURE (1ul << 31) 282 #define VMX_ENTRY_FLAGS (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 283 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 284 285 enum Reason { 286 VMX_EXC_NMI = 0, 287 VMX_EXTINT = 1, 288 VMX_TRIPLE_FAULT = 2, 289 VMX_INIT = 3, 290 VMX_SIPI = 4, 291 VMX_SMI_IO = 5, 292 VMX_SMI_OTHER = 6, 293 VMX_INTR_WINDOW = 7, 294 VMX_NMI_WINDOW = 8, 295 VMX_TASK_SWITCH = 9, 296 VMX_CPUID = 10, 297 VMX_GETSEC = 11, 298 VMX_HLT = 12, 299 VMX_INVD = 13, 300 VMX_INVLPG = 14, 301 VMX_RDPMC = 15, 302 VMX_RDTSC = 16, 303 VMX_RSM = 17, 304 VMX_VMCALL = 18, 305 VMX_VMCLEAR = 19, 306 VMX_VMLAUNCH = 20, 307 VMX_VMPTRLD = 21, 308 VMX_VMPTRST = 22, 309 VMX_VMREAD = 23, 310 VMX_VMRESUME = 24, 311 VMX_VMWRITE = 25, 312 VMX_VMXOFF = 26, 313 VMX_VMXON = 27, 314 VMX_CR = 28, 315 VMX_DR = 29, 316 VMX_IO = 30, 317 VMX_RDMSR = 31, 318 VMX_WRMSR = 32, 319 VMX_FAIL_STATE = 33, 320 VMX_FAIL_MSR = 34, 321 VMX_MWAIT = 36, 322 VMX_MTF = 37, 323 VMX_MONITOR = 39, 324 VMX_PAUSE = 40, 325 VMX_FAIL_MCHECK = 41, 326 VMX_TPR_THRESHOLD = 43, 327 VMX_APIC_ACCESS = 44, 328 VMX_EOI_INDUCED = 45, 329 VMX_GDTR_IDTR = 46, 330 VMX_LDTR_TR = 47, 331 VMX_EPT_VIOLATION = 48, 332 VMX_EPT_MISCONFIG = 49, 333 VMX_INVEPT = 50, 334 VMX_PREEMPT = 52, 335 VMX_INVVPID = 53, 336 VMX_WBINVD = 54, 337 VMX_XSETBV = 55, 338 VMX_APIC_WRITE = 56, 339 VMX_RDRAND = 57, 340 VMX_INVPCID = 58, 341 VMX_VMFUNC = 59, 342 VMX_RDSEED = 61, 343 VMX_PML_FULL = 62, 344 VMX_XSAVES = 63, 345 VMX_XRSTORS = 64, 346 }; 347 348 enum Ctrl_exi { 349 EXI_SAVE_DBGCTLS = 1UL << 2, 350 EXI_HOST_64 = 1UL << 9, 351 EXI_LOAD_PERF = 1UL << 12, 352 EXI_INTA = 1UL << 15, 353 EXI_SAVE_PAT = 1UL << 18, 354 EXI_LOAD_PAT = 1UL << 19, 355 EXI_SAVE_EFER = 1UL << 20, 356 EXI_LOAD_EFER = 1UL << 21, 357 EXI_SAVE_PREEMPT = 1UL << 22, 358 }; 359 360 enum Ctrl_ent { 361 ENT_LOAD_DBGCTLS = 1UL << 2, 362 ENT_GUEST_64 = 1UL << 9, 363 ENT_LOAD_PAT = 1UL << 14, 364 ENT_LOAD_EFER = 1UL << 15, 365 }; 366 367 enum Ctrl_pin { 368 PIN_EXTINT = 1ul << 0, 369 PIN_NMI = 1ul << 3, 370 PIN_VIRT_NMI = 1ul << 5, 371 PIN_PREEMPT = 1ul << 6, 372 PIN_POST_INTR = 1ul << 7, 373 }; 374 375 enum Ctrl0 { 376 CPU_INTR_WINDOW = 1ul << 2, 377 CPU_HLT = 1ul << 7, 378 CPU_INVLPG = 1ul << 9, 379 CPU_MWAIT = 1ul << 10, 380 CPU_RDPMC = 1ul << 11, 381 CPU_RDTSC = 1ul << 12, 382 CPU_CR3_LOAD = 1ul << 15, 383 CPU_CR3_STORE = 1ul << 16, 384 CPU_CR8_LOAD = 1ul << 19, 385 CPU_CR8_STORE = 1ul << 20, 386 CPU_TPR_SHADOW = 1ul << 21, 387 CPU_NMI_WINDOW = 1ul << 22, 388 CPU_IO = 1ul << 24, 389 CPU_IO_BITMAP = 1ul << 25, 390 CPU_MSR_BITMAP = 1ul << 28, 391 CPU_MONITOR = 1ul << 29, 392 CPU_PAUSE = 1ul << 30, 393 CPU_SECONDARY = 1ul << 31, 394 }; 395 396 enum Ctrl1 { 397 CPU_VIRT_APIC_ACCESSES = 1ul << 0, 398 CPU_EPT = 1ul << 1, 399 CPU_DESC_TABLE = 1ul << 2, 400 CPU_RDTSCP = 1ul << 3, 401 CPU_VIRT_X2APIC = 1ul << 4, 402 CPU_VPID = 1ul << 5, 403 CPU_WBINVD = 1ul << 6, 404 CPU_URG = 1ul << 7, 405 CPU_APIC_REG_VIRT = 1ul << 8, 406 CPU_VINTD = 1ul << 9, 407 CPU_RDRAND = 1ul << 11, 408 CPU_RDSEED = 1ul << 16, 409 CPU_PML = 1ul << 17, 410 }; 411 412 enum Intr_type { 413 VMX_INTR_TYPE_EXT_INTR = 0, 414 VMX_INTR_TYPE_NMI_INTR = 2, 415 VMX_INTR_TYPE_HARD_EXCEPTION = 3, 416 VMX_INTR_TYPE_SOFT_INTR = 4, 417 VMX_INTR_TYPE_SOFT_EXCEPTION = 6, 418 }; 419 420 /* 421 * Interruption-information format 422 */ 423 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 424 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 425 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 426 #define INTR_INFO_UNBLOCK_NMI_MASK 0x1000 /* 12 */ 427 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 428 429 #define INTR_INFO_INTR_TYPE_SHIFT 8 430 431 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 432 #define INTR_TYPE_RESERVED (1 << 8) /* reserved */ 433 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 434 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 435 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 436 #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* priv. software exception */ 437 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 438 #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ 439 440 /* 441 * VM-instruction error numbers 442 */ 443 enum vm_instruction_error_number { 444 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 445 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 446 VMXERR_VMCLEAR_VMXON_POINTER = 3, 447 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 448 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 449 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 450 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 451 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 452 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 453 VMXERR_VMPTRLD_VMXON_POINTER = 10, 454 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 455 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 456 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 457 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 458 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 459 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 460 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 461 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 462 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 463 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 464 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 465 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 466 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 467 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 468 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 469 }; 470 471 #define SAVE_GPR \ 472 "xchg %rax, regs\n\t" \ 473 "xchg %rbx, regs+0x8\n\t" \ 474 "xchg %rcx, regs+0x10\n\t" \ 475 "xchg %rdx, regs+0x18\n\t" \ 476 "xchg %rbp, regs+0x28\n\t" \ 477 "xchg %rsi, regs+0x30\n\t" \ 478 "xchg %rdi, regs+0x38\n\t" \ 479 "xchg %r8, regs+0x40\n\t" \ 480 "xchg %r9, regs+0x48\n\t" \ 481 "xchg %r10, regs+0x50\n\t" \ 482 "xchg %r11, regs+0x58\n\t" \ 483 "xchg %r12, regs+0x60\n\t" \ 484 "xchg %r13, regs+0x68\n\t" \ 485 "xchg %r14, regs+0x70\n\t" \ 486 "xchg %r15, regs+0x78\n\t" 487 488 #define LOAD_GPR SAVE_GPR 489 490 #define SAVE_GPR_C \ 491 "xchg %%rax, regs\n\t" \ 492 "xchg %%rbx, regs+0x8\n\t" \ 493 "xchg %%rcx, regs+0x10\n\t" \ 494 "xchg %%rdx, regs+0x18\n\t" \ 495 "xchg %%rbp, regs+0x28\n\t" \ 496 "xchg %%rsi, regs+0x30\n\t" \ 497 "xchg %%rdi, regs+0x38\n\t" \ 498 "xchg %%r8, regs+0x40\n\t" \ 499 "xchg %%r9, regs+0x48\n\t" \ 500 "xchg %%r10, regs+0x50\n\t" \ 501 "xchg %%r11, regs+0x58\n\t" \ 502 "xchg %%r12, regs+0x60\n\t" \ 503 "xchg %%r13, regs+0x68\n\t" \ 504 "xchg %%r14, regs+0x70\n\t" \ 505 "xchg %%r15, regs+0x78\n\t" 506 507 #define LOAD_GPR_C SAVE_GPR_C 508 509 #define VMX_IO_SIZE_MASK 0x7 510 #define _VMX_IO_BYTE 0 511 #define _VMX_IO_WORD 1 512 #define _VMX_IO_LONG 3 513 #define VMX_IO_DIRECTION_MASK (1ul << 3) 514 #define VMX_IO_IN (1ul << 3) 515 #define VMX_IO_OUT 0 516 #define VMX_IO_STRING (1ul << 4) 517 #define VMX_IO_REP (1ul << 5) 518 #define VMX_IO_OPRAND_IMM (1ul << 6) 519 #define VMX_IO_PORT_MASK 0xFFFF0000 520 #define VMX_IO_PORT_SHIFT 16 521 522 #define VMX_TEST_START 0 523 #define VMX_TEST_VMEXIT 1 524 #define VMX_TEST_EXIT 2 525 #define VMX_TEST_RESUME 3 526 #define VMX_TEST_VMABORT 4 527 #define VMX_TEST_VMSKIP 5 528 529 #define HYPERCALL_BIT (1ul << 12) 530 #define HYPERCALL_MASK 0xFFF 531 #define HYPERCALL_VMEXIT 0x1 532 #define HYPERCALL_VMABORT 0x2 533 #define HYPERCALL_VMSKIP 0x3 534 535 #define EPTP_PG_WALK_LEN_SHIFT 3ul 536 #define EPTP_AD_FLAG (1ul << 6) 537 538 #define EPT_MEM_TYPE_UC 0ul 539 #define EPT_MEM_TYPE_WC 1ul 540 #define EPT_MEM_TYPE_WT 4ul 541 #define EPT_MEM_TYPE_WP 5ul 542 #define EPT_MEM_TYPE_WB 6ul 543 544 #define EPT_RA 1ul 545 #define EPT_WA 2ul 546 #define EPT_EA 4ul 547 #define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) 548 #define EPT_ACCESS_FLAG (1ul << 8) 549 #define EPT_DIRTY_FLAG (1ul << 9) 550 #define EPT_LARGE_PAGE (1ul << 7) 551 #define EPT_MEM_TYPE_SHIFT 3ul 552 #define EPT_IGNORE_PAT (1ul << 6) 553 #define EPT_SUPPRESS_VE (1ull << 63) 554 555 #define EPT_CAP_WT 1ull 556 #define EPT_CAP_PWL4 (1ull << 6) 557 #define EPT_CAP_UC (1ull << 8) 558 #define EPT_CAP_WB (1ull << 14) 559 #define EPT_CAP_2M_PAGE (1ull << 16) 560 #define EPT_CAP_1G_PAGE (1ull << 17) 561 #define EPT_CAP_INVEPT (1ull << 20) 562 #define EPT_CAP_INVEPT_SINGLE (1ull << 25) 563 #define EPT_CAP_INVEPT_ALL (1ull << 26) 564 #define EPT_CAP_AD_FLAG (1ull << 21) 565 #define VPID_CAP_INVVPID (1ull << 32) 566 #define VPID_CAP_INVVPID_ADDR (1ull << 40) 567 #define VPID_CAP_INVVPID_CXTGLB (1ull << 41) 568 #define VPID_CAP_INVVPID_ALL (1ull << 42) 569 #define VPID_CAP_INVVPID_CXTLOC (1ull << 43) 570 571 #define PAGE_SIZE_2M (512 * PAGE_SIZE) 572 #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) 573 #define EPT_PAGE_LEVEL 4 574 #define EPT_PGDIR_WIDTH 9 575 #define EPT_PGDIR_MASK 511 576 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH) 577 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12) 578 #define EPT_ADDR_MASK GENMASK_ULL(51, 12) 579 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) 580 581 #define EPT_VLT_RD 1 582 #define EPT_VLT_WR (1 << 1) 583 #define EPT_VLT_FETCH (1 << 2) 584 #define EPT_VLT_PERM_RD (1 << 3) 585 #define EPT_VLT_PERM_WR (1 << 4) 586 #define EPT_VLT_PERM_EX (1 << 5) 587 #define EPT_VLT_PERMS (EPT_VLT_PERM_RD | EPT_VLT_PERM_WR | \ 588 EPT_VLT_PERM_EX) 589 #define EPT_VLT_LADDR_VLD (1 << 7) 590 #define EPT_VLT_PADDR (1 << 8) 591 592 #define MAGIC_VAL_1 0x12345678ul 593 #define MAGIC_VAL_2 0x87654321ul 594 #define MAGIC_VAL_3 0xfffffffful 595 #define MAGIC_VAL_4 0xdeadbeeful 596 597 #define INVEPT_SINGLE 1 598 #define INVEPT_GLOBAL 2 599 600 #define INVVPID_ADDR 0 601 #define INVVPID_CONTEXT_GLOBAL 1 602 #define INVVPID_ALL 2 603 #define INVVPID_CONTEXT_LOCAL 3 604 605 #define ACTV_ACTIVE 0 606 #define ACTV_HLT 1 607 608 extern struct regs regs; 609 610 extern union vmx_basic basic; 611 extern union vmx_ctrl_msr ctrl_pin_rev; 612 extern union vmx_ctrl_msr ctrl_cpu_rev[2]; 613 extern union vmx_ctrl_msr ctrl_exit_rev; 614 extern union vmx_ctrl_msr ctrl_enter_rev; 615 extern union vmx_ept_vpid ept_vpid; 616 617 extern u64 *vmxon_region; 618 619 void vmx_set_test_stage(u32 s); 620 u32 vmx_get_test_stage(void); 621 void vmx_inc_test_stage(void); 622 623 static int vmx_on(void) 624 { 625 bool ret; 626 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 627 asm volatile ("push %1; popf; vmxon %2; setbe %0\n\t" 628 : "=q" (ret) : "q" (rflags), "m" (vmxon_region) : "cc"); 629 return ret; 630 } 631 632 static int vmx_off(void) 633 { 634 bool ret; 635 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 636 637 asm volatile("push %1; popf; vmxoff; setbe %0\n\t" 638 : "=q"(ret) : "q" (rflags) : "cc"); 639 return ret; 640 } 641 642 static inline int make_vmcs_current(struct vmcs *vmcs) 643 { 644 bool ret; 645 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 646 647 asm volatile ("push %1; popf; vmptrld %2; setbe %0" 648 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 649 return ret; 650 } 651 652 static inline int vmcs_clear(struct vmcs *vmcs) 653 { 654 bool ret; 655 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 656 657 asm volatile ("push %1; popf; vmclear %2; setbe %0" 658 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 659 return ret; 660 } 661 662 static inline u64 vmcs_read(enum Encoding enc) 663 { 664 u64 val; 665 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); 666 return val; 667 } 668 669 static inline int vmcs_read_checking(enum Encoding enc, u64 *value) 670 { 671 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 672 u64 encoding = enc; 673 u64 val; 674 675 asm volatile ("shl $8, %%rax;" 676 "sahf;" 677 "vmread %[encoding], %[val];" 678 "lahf;" 679 "shr $8, %%rax" 680 : /* output */ [val]"=rm"(val), "+a"(rflags) 681 : /* input */ [encoding]"r"(encoding) 682 : /* clobber */ "cc"); 683 684 *value = val; 685 return rflags & (X86_EFLAGS_CF | X86_EFLAGS_ZF); 686 } 687 688 static inline int vmcs_write(enum Encoding enc, u64 val) 689 { 690 bool ret; 691 asm volatile ("vmwrite %1, %2; setbe %0" 692 : "=q"(ret) : "rm" (val), "r" ((u64)enc) : "cc"); 693 return ret; 694 } 695 696 static inline int vmcs_save(struct vmcs **vmcs) 697 { 698 bool ret; 699 unsigned long pa; 700 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 701 702 asm volatile ("push %2; popf; vmptrst %1; setbe %0" 703 : "=q" (ret), "=m" (pa) : "r" (rflags) : "cc"); 704 *vmcs = (pa == -1ull) ? NULL : phys_to_virt(pa); 705 return ret; 706 } 707 708 static inline bool invept(unsigned long type, u64 eptp) 709 { 710 bool ret; 711 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 712 713 struct { 714 u64 eptp, gpa; 715 } operand = {eptp, 0}; 716 asm volatile("push %1; popf; invept %2, %3; setbe %0" 717 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 718 return ret; 719 } 720 721 static inline bool invvpid(unsigned long type, u64 vpid, u64 gla) 722 { 723 bool ret; 724 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 725 726 struct invvpid_operand operand = {vpid, gla}; 727 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" 728 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 729 return ret; 730 } 731 732 static inline int enable_unrestricted_guest(void) 733 { 734 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 735 return -1; 736 737 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 738 return -1; 739 740 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 741 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 742 return 0; 743 } 744 745 static inline void disable_unrestricted_guest(void) 746 { 747 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 748 } 749 750 const char *exit_reason_description(u64 reason); 751 void print_vmexit_info(void); 752 void print_vmentry_failure_info(struct vmentry_failure *failure); 753 void ept_sync(int type, u64 eptp); 754 void vpid_sync(int type, u16 vpid); 755 void install_ept_entry(unsigned long *pml4, int pte_level, 756 unsigned long guest_addr, unsigned long pte, 757 unsigned long *pt_page); 758 void install_1g_ept(unsigned long *pml4, unsigned long phys, 759 unsigned long guest_addr, u64 perm); 760 void install_2m_ept(unsigned long *pml4, unsigned long phys, 761 unsigned long guest_addr, u64 perm); 762 void install_ept(unsigned long *pml4, unsigned long phys, 763 unsigned long guest_addr, u64 perm); 764 void setup_ept_range(unsigned long *pml4, unsigned long start, 765 unsigned long len, int map_1g, int map_2m, u64 perm); 766 bool get_ept_pte(unsigned long *pml4, unsigned long guest_addr, int level, 767 unsigned long *pte); 768 void set_ept_pte(unsigned long *pml4, unsigned long guest_addr, 769 int level, u64 pte_val); 770 void check_ept_ad(unsigned long *pml4, u64 guest_cr3, 771 unsigned long guest_addr, int expected_gpa_ad, 772 int expected_pt_ad); 773 void clear_ept_ad(unsigned long *pml4, u64 guest_cr3, 774 unsigned long guest_addr); 775 776 bool ept_2m_supported(void); 777 bool ept_1g_supported(void); 778 bool ept_huge_pages_supported(int level); 779 bool ept_execute_only_supported(void); 780 bool ept_ad_bits_supported(void); 781 782 void enter_guest(void); 783 784 typedef void (*test_guest_func)(void); 785 typedef void (*test_teardown_func)(void *data); 786 void test_set_guest(test_guest_func func); 787 void test_add_teardown(test_teardown_func func, void *data); 788 void test_skip(const char *msg); 789 790 void __abort_test(void); 791 792 #define TEST_ASSERT(cond) \ 793 do { \ 794 if (!(cond)) { \ 795 report("%s:%d: Assertion failed: %s", 0, \ 796 __FILE__, __LINE__, #cond); \ 797 dump_stack(); \ 798 __abort_test(); \ 799 } \ 800 report_pass(); \ 801 } while (0) 802 803 #define TEST_ASSERT_MSG(cond, fmt, args...) \ 804 do { \ 805 if (!(cond)) { \ 806 report("%s:%d: Assertion failed: %s\n" fmt, 0, \ 807 __FILE__, __LINE__, #cond, ##args); \ 808 dump_stack(); \ 809 __abort_test(); \ 810 } \ 811 report_pass(); \ 812 } while (0) 813 814 #define __TEST_EQ(a, b, a_str, b_str, assertion, fmt, args...) \ 815 do { \ 816 typeof(a) _a = a; \ 817 typeof(b) _b = b; \ 818 if (_a != _b) { \ 819 char _bin_a[BINSTR_SZ]; \ 820 char _bin_b[BINSTR_SZ]; \ 821 binstr(_a, _bin_a); \ 822 binstr(_b, _bin_b); \ 823 report("%s:%d: %s failed: (%s) == (%s)\n" \ 824 "\tLHS: %#018lx - %s - %lu\n" \ 825 "\tRHS: %#018lx - %s - %lu%s" fmt, 0, \ 826 __FILE__, __LINE__, \ 827 assertion ? "Assertion" : "Expectation", a_str, b_str, \ 828 (unsigned long) _a, _bin_a, (unsigned long) _a, \ 829 (unsigned long) _b, _bin_b, (unsigned long) _b, \ 830 fmt[0] == '\0' ? "" : "\n", ## args); \ 831 dump_stack(); \ 832 if (assertion) \ 833 __abort_test(); \ 834 } \ 835 report_pass(); \ 836 } while (0) 837 838 #define TEST_ASSERT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 1, "") 839 #define TEST_ASSERT_EQ_MSG(a, b, fmt, args...) \ 840 __TEST_EQ(a, b, #a, #b, 1, fmt, ## args) 841 #define TEST_EXPECT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 0, "") 842 #define TEST_EXPECT_EQ_MSG(a, b, fmt, args...) \ 843 __TEST_EQ(a, b, #a, #b, 0, fmt, ## args) 844 845 #endif 846