1/* 2 * s390x startup code 3 * 4 * Copyright (c) 2017 Red Hat Inc 5 * 6 * Authors: 7 * Thomas Huth <thuth@redhat.com> 8 * David Hildenbrand <david@redhat.com> 9 * 10 * This code is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU Library General Public License version 2. 12 */ 13#include <asm/asm-offsets.h> 14 15.section .init 16 17/* entry point - for KVM + TCG we directly start in 64 bit mode */ 18 .globl start 19start: 20 /* setup stack */ 21 larl %r15, stackptr 22 /* setup initial PSW mask + control registers*/ 23 larl %r1, initital_psw 24 lpswe 0(%r1) 25init_psw_cont: 26 /* setup pgm interrupt handler */ 27 larl %r1, pgm_int_psw 28 mvc GEN_LC_PGM_NEW_PSW(16), 0(%r1) 29 /* setup ext interrupt handler */ 30 larl %r1, ext_int_psw 31 mvc GEN_LC_EXT_NEW_PSW(16), 0(%r1) 32 /* setup mcck interrupt handler */ 33 larl %r1, mcck_int_psw 34 mvc GEN_LC_MCCK_NEW_PSW(16), 0(%r1) 35 /* setup io interrupt handler */ 36 larl %r1, ext_int_psw 37 mvc GEN_LC_IO_NEW_PSW(16), 0(%r1) 38 /* setup svc interrupt handler */ 39 larl %r1, mcck_int_psw 40 mvc GEN_LC_SVC_NEW_PSW(16), 0(%r1) 41 /* setup cr0, enabling e.g. AFP-register control */ 42 larl %r1, initital_cr0 43 lctlg %c0, %c0, 0(%r1) 44 /* call setup() */ 45 brasl %r14, setup 46 /* forward test parameter */ 47 larl %r2, __argc 48 llgf %r2, 0(%r2) 49 larl %r3, __argv 50 /* call to main() */ 51 brasl %r14, main 52 /* forward exit code */ 53 lgr %r3, %r2 54 /* call exit() */ 55 j exit 56 57 .macro SAVE_REGS 58 /* save grs 0-15 */ 59 stmg %r0, %r15, GEN_LC_SW_INT_GRS 60 /* save fprs 0-15 + fpc */ 61 larl %r1, GEN_LC_SW_INT_FPRS 62 std %f0, 0(%r1) 63 std %f1, 8(%r1) 64 std %f2, 16(%r1) 65 std %f3, 24(%r1) 66 std %f4, 32(%r1) 67 std %f5, 40(%r1) 68 std %f6, 48(%r1) 69 std %f7, 56(%r1) 70 std %f8, 64(%r1) 71 std %f9, 72(%r1) 72 std %f10, 80(%r1) 73 std %f11, 88(%r1) 74 std %f12, 96(%r1) 75 std %f13, 104(%r1) 76 std %f14, 112(%r1) 77 std %f15, 120(%r1) 78 stfpc GEN_LC_SW_INT_FPC 79 .endm 80 81 .macro RESTORE_REGS 82 /* restore fprs 0-15 + fpc */ 83 larl %r1, GEN_LC_SW_INT_FPRS 84 ld %f0, 0(%r1) 85 ld %f1, 8(%r1) 86 ld %f2, 16(%r1) 87 ld %f3, 24(%r1) 88 ld %f4, 32(%r1) 89 ld %f5, 40(%r1) 90 ld %f6, 48(%r1) 91 ld %f7, 56(%r1) 92 ld %f8, 64(%r1) 93 ld %f9, 72(%r1) 94 ld %f10, 80(%r1) 95 ld %f11, 88(%r1) 96 ld %f12, 96(%r1) 97 ld %f13, 104(%r1) 98 ld %f14, 112(%r1) 99 ld %f15, 120(%r1) 100 lfpc GEN_LC_SW_INT_FPC 101 /* restore grs 0-15 */ 102 lmg %r0, %r15, GEN_LC_SW_INT_GRS 103 .endm 104 105.section .text 106pgm_int: 107 SAVE_REGS 108 brasl %r14, handle_pgm_int 109 RESTORE_REGS 110 lpswe GEN_LC_PGM_OLD_PSW 111 112ext_int: 113 SAVE_REGS 114 brasl %r14, handle_ext_int 115 RESTORE_REGS 116 lpswe GEN_LC_EXT_OLD_PSW 117 118mcck_int: 119 SAVE_REGS 120 brasl %r14, handle_mcck_int 121 RESTORE_REGS 122 lpswe GEN_LC_MCCK_OLD_PSW 123 124io_int: 125 SAVE_REGS 126 brasl %r14, handle_io_int 127 RESTORE_REGS 128 lpswe GEN_LC_IO_OLD_PSW 129 130svc_int: 131 SAVE_REGS 132 brasl %r14, handle_svc_int 133 RESTORE_REGS 134 lpswe GEN_LC_SVC_OLD_PSW 135 136 .align 8 137initital_psw: 138 .quad 0x0000000180000000, init_psw_cont 139pgm_int_psw: 140 .quad 0x0000000180000000, pgm_int 141ext_int_psw: 142 .quad 0x0000000180000000, ext_int 143mcck_int_psw: 144 .quad 0x0000000180000000, mcck_int 145io_int_psw: 146 .quad 0x0000000180000000, io_int 147svc_int_psw: 148 .quad 0x0000000180000000, svc_int 149initital_cr0: 150 /* enable AFP-register control, so FP regs (+BFP instr) can be used */ 151 .quad 0x0000000000040000 152