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/linux-3.3/drivers/net/ethernet/i825xx/
Dether1.h17 /* use 0 for production, 1 for verification, >2 for debug */
19 #define NET_DEBUG 0
25 #define REG_PAGE (priv(dev)->base + 0x0000)
28 #define REG_CONTROL (priv(dev)->base + 0x0004)
29 #define CTRL_RST 0x01
30 #define CTRL_LOOPBACK 0x02
31 #define CTRL_CA 0x04
32 #define CTRL_ACK 0x08
34 #define ETHER1_RAM (priv(dev)->base + 0x2000)
37 #define IDPROM_ADDRESS (priv(dev)->base + 0x0024)
[all …]
/linux-3.3/drivers/net/wireless/p54/
Dp54spi.h32 #define SPI_ADRS_READ_BIT_15 0x8000
34 #define SPI_ADRS_ARM_INTERRUPTS 0x00
35 #define SPI_ADRS_ARM_INT_EN 0x04
37 #define SPI_ADRS_HOST_INTERRUPTS 0x08
38 #define SPI_ADRS_HOST_INT_EN 0x0c
39 #define SPI_ADRS_HOST_INT_ACK 0x10
41 #define SPI_ADRS_GEN_PURP_1 0x14
42 #define SPI_ADRS_GEN_PURP_2 0x18
44 #define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */
46 #define SPI_ADRS_DMA_DATA 0x28
[all …]
/linux-3.3/arch/x86/include/asm/visws/
Dpiix4.h8 #define PIIX_PM_START 0x0F80
10 #define SIO_GPIO_START 0x0FC0
12 #define SIO_PM_START 0x0FC8
15 #define GPIREG0 (PMBASE+0x30)
31 #define SIO_INDEX 0x2e
32 #define SIO_DATA 0x2f
34 #define SIO_DEV_SEL 0x7
35 #define SIO_DEV_ENB 0x30
36 #define SIO_DEV_MSB 0x60
37 #define SIO_DEV_LSB 0x61
[all …]
/linux-3.3/arch/powerpc/boot/dts/fsl/
Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec4.4", "fsl,sec4.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <58 2 0 0>;
43 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
44 reg = <0x1000 0x1000>;
45 interrupts = <45 2 0 0>;
49 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
50 reg = <0x2000 0x1000>;
51 interrupts = <45 2 0 0>;
[all …]
/linux-3.3/arch/h8300/platform/h8300h/generic/
Dcrt0_rom.S27 ldc #0x80,ccr
68 ldc #0x90,ccr /* running kernel */
70 add.l #0x2000,sp
85 .byte 0x00,0x00
87 .byte 0x00,0x00
89 .byte 0x00,0x00
91 .byte 0x00,0x00
93 .byte 0x00,0x00
95 .byte 0x00,0x00
97 .byte 0x00,0x00
[all …]
/linux-3.3/include/linux/
Dnfs_mount.h50 #define NFS_MOUNT_SOFT 0x0001 /* 1 */
51 #define NFS_MOUNT_INTR 0x0002 /* 1 */ /* now unused, but ABI */
52 #define NFS_MOUNT_SECURE 0x0004 /* 1 */
53 #define NFS_MOUNT_POSIX 0x0008 /* 1 */
54 #define NFS_MOUNT_NOCTO 0x0010 /* 1 */
55 #define NFS_MOUNT_NOAC 0x0020 /* 1 */
56 #define NFS_MOUNT_TCP 0x0040 /* 2 */
57 #define NFS_MOUNT_VER3 0x0080 /* 3 */
58 #define NFS_MOUNT_KERBEROS 0x0100 /* 3 */
59 #define NFS_MOUNT_NONLM 0x0200 /* 3 */
[all …]
/linux-3.3/arch/mn10300/include/asm/
Dintctl-regs.h23 __SYSREG(0xd4000000 + (X) * 4 + \
24 (((X) >= 64) && ((X) < 192)) * 0xf00, u16)
27 __SYSREG(0xd4000000 + (X) * 4 + \
28 (((X) >= 64) && ((X) < 192)) * 0xf00, u8)
32 #define XIRQ_TRIGGER_LOWLEVEL 0
38 #define NMIIRQ 0
40 #define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
41 #define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */
42 #define NMICR_ABUSERR 0x0008 /* async bus error flag */
45 #define GxICR_DETECT 0x0001 /* interrupt detect flag */
[all …]
Dserial-regs.h20 /* serial port 0 */
21 #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
22 #define SC01CTR_CK 0x0007 /* clock source select */
23 #define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
24 #define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
25 #define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
26 #define SC01CTR_CK_EXTERN 0x0007 /* - external closk */
28 #define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
29 #define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
30 #define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
[all …]
/linux-3.3/arch/mips/include/asm/mach-db1x00/
Ddb1200.h32 #define BCSR_INT_IDE 0x0001
33 #define BCSR_INT_ETH 0x0002
34 #define BCSR_INT_PC0 0x0004
35 #define BCSR_INT_PC0STSCHG 0x0008
36 #define BCSR_INT_PC1 0x0010
37 #define BCSR_INT_PC1STSCHG 0x0020
38 #define BCSR_INT_DC 0x0040
39 #define BCSR_INT_FLASHBUSY 0x0080
40 #define BCSR_INT_PC0INSERT 0x0100
41 #define BCSR_INT_PC0EJECT 0x0200
[all …]
/linux-3.3/include/linux/mfd/wm8994/
Dregisters.h21 #define WM8994_SOFTWARE_RESET 0x00
22 #define WM8994_POWER_MANAGEMENT_1 0x01
23 #define WM8994_POWER_MANAGEMENT_2 0x02
24 #define WM8994_POWER_MANAGEMENT_3 0x03
25 #define WM8994_POWER_MANAGEMENT_4 0x04
26 #define WM8994_POWER_MANAGEMENT_5 0x05
27 #define WM8994_POWER_MANAGEMENT_6 0x06
28 #define WM8994_INPUT_MIXER_1 0x15
29 #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
30 #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
[all …]
/linux-3.3/arch/arm/include/asm/hardware/
Dep7212.h31 #define EP7212_PHYS_BASE (0x80000000)
41 #define DAIR 0x2000
42 #define DAIR0 0x2040
43 #define DAIDR1 0x2080
44 #define DAIDR2 0x20c0
45 #define DAISR 0x2100
46 #define SYSCON3 0x2200
47 #define INTSR3 0x2240
48 #define INTMR3 0x2280
49 #define LEDFLSH 0x22c0
[all …]
/linux-3.3/arch/powerpc/platforms/iseries/
Drelease_data.h41 #define HVREL_TAGSINACTIVE 0x8000
42 #define HVREL_32BIT 0x4000
43 #define HVREL_NOSHAREDPROCS 0x2000
44 #define HVREL_NOHMT 0x1000
/linux-3.3/arch/score/kernel/
Dvmlinux.lds.S37 . = CONFIG_MEMORY_START + 0x2000;
87 BSS_SECTION(0, 0, 0)
/linux-3.3/drivers/net/fddi/skfp/h/
Dsupern_2.h39 #define MB 0xff
40 #define MW 0xffff
41 #define MD 0xffffffff
48 #define FS_CI (1<<0)
62 #define FS_ERFBB0 (1<<0) /* - " - */
67 #define FRM_SMT (0) /* asynchr. frames */
85 #define RX_FS_SMT ((long)0<<16) /* SMT frame */
128 #define RD_S_ERFBB 0x00030000L /* received frame byte boundary */
129 #define RD_S_RES2 0x000c0000L /* reserved */
130 #define RD_S_SFRMTY 0x00700000L /* frame type bits */
[all …]
/linux-3.3/arch/powerpc/boot/dts/
Dksi8560.dts31 #size-cells = <0>;
33 PowerPC,8560@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
40 timebase-frequency = <0>; /* From U-boot */
41 bus-frequency = <0>; /* From U-boot */
42 clock-frequency = <0>; /* From U-boot */
49 reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
56 ranges = <0x00000000 0xfdf00000 0x00100000>;
[all …]
Dtqm8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
Dtqm8541.dts30 #size-cells = <0>;
32 PowerPC,8541@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
/linux-3.3/drivers/net/ethernet/amd/
D7990.h17 #define LANCE_RDP 0 /* Register Data Port */
134 #define LE_CSR0 0x0000 /* LANCE Controller Status */
135 #define LE_CSR1 0x0001 /* IADR[15:0] (bit0==0 ie word aligned) */
136 #define LE_CSR2 0x0002 /* IADR[23:16] (high bits reserved) */
137 #define LE_CSR3 0x0003 /* Misc */
142 #define LE_C0_ERR 0x8000 /* Error = BABL | CERR | MISS | MERR */
143 #define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */
144 #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
145 #define LE_C0_MISS 0x1000 /* Missed Frame (no rx buffer to put it in) */
146 #define LE_C0_MERR 0x0800 /* Memory Error */
[all …]
/linux-3.3/drivers/scsi/arm/
Dcumana_1.c41 #define BOARD_NORMAL 0
55 #define CTRL 0x16fc
56 #define STAT 0x2004
57 #define L(v) (((v)<<16)|((v) & 0x0000ffff))
58 #define H(v) (((v)>>16)|((v) & 0xffff0000))
64 void __iomem *dma = priv(host)->dma + 0x2000; in NCR5380_pwrite()
66 if(!len) return 0; in NCR5380_pwrite()
68 writeb(0x02, priv(host)->base + CTRL); in NCR5380_pwrite()
75 if(status & 0x80) in NCR5380_pwrite()
77 if(!(status & 0x40)) in NCR5380_pwrite()
[all …]
/linux-3.3/drivers/net/ethernet/ibm/ehea/
Dehea_qmr.h63 #define EHEA_WR_ID_COUNT EHEA_BMASK_IBM(0, 19)
65 #define EHEA_SWQE2_TYPE 0x1
66 #define EHEA_SWQE3_TYPE 0x2
67 #define EHEA_RWQE2_TYPE 0x3
68 #define EHEA_RWQE3_TYPE 0x4
80 #define SWQE2_MAX_IMM (0xD0 - 0x30)
84 #define EHEA_SWQE_CRC 0x8000
85 #define EHEA_SWQE_IP_CHECKSUM 0x4000
86 #define EHEA_SWQE_TCP_CHECKSUM 0x2000
87 #define EHEA_SWQE_TSO 0x1000
[all …]
/linux-3.3/arch/blackfin/mach-bf533/include/mach/
Dbf533.h12 #define OFFSET_(x) ((x) & 0x0000FFFF)
15 #define IMASK_IVG15 0x8000
16 #define IMASK_IVG14 0x4000
17 #define IMASK_IVG13 0x2000
18 #define IMASK_IVG12 0x1000
20 #define IMASK_IVG11 0x0800
21 #define IMASK_IVG10 0x0400
22 #define IMASK_IVG9 0x0200
23 #define IMASK_IVG8 0x0100
25 #define IMASK_IVG7 0x0080
[all …]
/linux-3.3/include/linux/bcma/
Dbcma_regs.h6 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
7 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
8 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
9 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
10 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
11 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
12 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
13 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
14 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
15 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
[all …]
/linux-3.3/arch/blackfin/include/asm/
Dkgdb.h28 BFIN_R0 = 0,
107 # define CACHE_FLUSH_IS_SAFE 0
114 #define TYPE_INST_WATCHPOINT 0
118 #define WPPWR 0x1
119 #define WPIREN01 0x2
120 #define WPIRINV01 0x4
121 #define WPIAEN0 0x8
122 #define WPIAEN1 0x10
123 #define WPICNTEN0 0x20
124 #define WPICNTEN1 0x40
[all …]
/linux-3.3/drivers/net/ethernet/aeroflex/
Dgreth.h7 #define GRETH_RESET 0x40
8 #define GRETH_MII_BUSY 0x8
9 #define GRETH_MII_NVALID 0x10
11 #define GRETH_CTRL_FD 0x10
12 #define GRETH_CTRL_PR 0x20
13 #define GRETH_CTRL_SP 0x80
14 #define GRETH_CTRL_GB 0x100
15 #define GRETH_CTRL_PSTATIEN 0x400
16 #define GRETH_CTRL_MCEN 0x800
17 #define GRETH_CTRL_DISDUPLEX 0x1000
[all …]
/linux-3.3/arch/blackfin/mach-bf518/include/mach/
DdefBF518.h15 #define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
16 #define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
17 #define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
18 #define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
19 #define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
20 #define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
21 #define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
22 #define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
23 #define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
24 #define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
[all …]

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