ethernet/amd/7990.h

17 #define LANCE_RDP	0	/* Register Data Port */
134 #define LE_CSR0         0x0000          /* LANCE Controller Status */
135 #define LE_CSR1         0x0001          /* IADR[15:0] (bit0==0 ie word aligned) */
136 #define LE_CSR2         0x0002          /* IADR[23:16] (high bits reserved) */
137 #define LE_CSR3         0x0003          /* Misc */
142 #define LE_C0_ERR	0x8000		/* Error = BABL | CERR | MISS | MERR */
143 #define LE_C0_BABL	0x4000		/* Babble: Transmitted too many bits */
144 #define LE_C0_CERR	0x2000		/* No Heartbeat (10BASE-T) */
145 #define LE_C0_MISS	0x1000		/* Missed Frame (no rx buffer to put it in) */
146 #define LE_C0_MERR	0x0800		/* Memory Error */
147 #define LE_C0_RINT	0x0400		/* Receive Interrupt */
148 #define LE_C0_TINT	0x0200		/* Transmit Interrupt */
149 #define LE_C0_IDON	0x0100		/* Initialization Done */
150 #define LE_C0_INTR	0x0080		/* Interrupt Flag
152 #define LE_C0_INEA	0x0040		/* Interrupt Enable */
153 #define LE_C0_RXON	0x0020		/* Receive On */
154 #define LE_C0_TXON	0x0010		/* Transmit On */
155 #define LE_C0_TDMD	0x0008		/* Transmit Demand */
156 #define LE_C0_STOP	0x0004		/* Stop */
157 #define LE_C0_STRT	0x0002		/* Start */
158 #define LE_C0_INIT	0x0001		/* Initialize */
164 #define LE_C3_BSWP	0x0004		/* Byte Swap
166 #define LE_C3_ACON	0x0002		/* ALE Control
168 #define LE_C3_BCON	0x0001		/* Byte Control */
174 #define LE_MO_PROM	0x8000		/* Promiscuous Mode */
175 /* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990,
178 #define LE_MO_DRCVBC  0x4000          /* disable receive broadcast */
179 #define LE_MO_DRCVPA  0x2000          /* disable physical address detection */
180 #define LE_MO_DLNKTST 0x1000          /* disable link status */
181 #define LE_MO_DAPC    0x0800          /* disable automatic polarity correction */
182 #define LE_MO_MENDECL 0x0400          /* MENDEC loopback mode */
183 #define LE_MO_LRTTSEL 0x0200          /* lower RX threshold / TX mode selection */
184 #define LE_MO_PSEL1   0x0100          /* port selection bit1 */
185 #define LE_MO_PSEL0   0x0080          /* port selection bit0 */
187 #define LE_MO_EMBA      0x0080          /* Enable Modified Backoff Algorithm
189 #define LE_MO_INTL	0x0040		/* Internal Loopback */
190 #define LE_MO_DRTY	0x0020		/* Disable Retry */
191 #define LE_MO_FCOLL	0x0010		/* Force Collision */
192 #define LE_MO_DXMTFCS	0x0008		/* Disable Transmit CRC */
193 #define LE_MO_LOOP	0x0004		/* Loopback Enable */
194 #define LE_MO_DTX	0x0002		/* Disable Transmitter */
195 #define LE_MO_DRX	0x0001		/* Disable Receiver */
201 #define LE_R1_OWN	0x80		/* LANCE owns the descriptor */
202 #define LE_R1_ERR	0x40		/* Error */
203 #define LE_R1_FRA	0x20		/* Framing Error */
204 #define LE_R1_OFL	0x10		/* Overflow Error */
205 #define LE_R1_CRC	0x08		/* CRC Error */
206 #define LE_R1_BUF	0x04		/* Buffer Error */
207 #define LE_R1_SOP	0x02		/* Start of Packet */
208 #define LE_R1_EOP	0x01		/* End of Packet */
209 #define LE_R1_POK       0x03		/* Packet is complete: SOP + EOP */
215 #define LE_T1_OWN	0x80		/* LANCE owns the descriptor */
216 #define LE_T1_ERR	0x40		/* Error */
217 #define LE_T1_RES	0x20		/* Reserved, LANCE writes this with a zero */
218 #define LE_T1_EMORE	0x10		/* More than one retry needed */
219 #define LE_T1_EONE	0x08		/* One retry needed */
220 #define LE_T1_EDEF	0x04		/* Deferred */
221 #define LE_T1_SOP	0x02		/* Start of Packet */
222 #define LE_T1_EOP	0x01		/* End of Packet */
223 #define LE_T1_POK	0x03		/* Packet is complete: SOP + EOP */
228 #define LE_T3_BUF 	0x8000		/* Buffer Error */
229 #define LE_T3_UFL 	0x4000		/* Underflow Error */
230 #define LE_T3_LCOL 	0x1000		/* Late Collision */
231 #define LE_T3_CLOS 	0x0800		/* Loss of Carrier */
232 #define LE_T3_RTY 	0x0400		/* Retry Error */
233 #define LE_T3_TDR	0x03ff		/* Time Domain Reflectometry */
242 #define LANCE_ADDR(x) ((int)(x) & ~0xff000000)