Lines Matching +full:0 +full:x2000

63 #define EHEA_WR_ID_COUNT   EHEA_BMASK_IBM(0, 19)
65 #define EHEA_SWQE2_TYPE    0x1
66 #define EHEA_SWQE3_TYPE    0x2
67 #define EHEA_RWQE2_TYPE    0x3
68 #define EHEA_RWQE3_TYPE    0x4
80 #define SWQE2_MAX_IMM            	(0xD0 - 0x30)
84 #define EHEA_SWQE_CRC                   0x8000
85 #define EHEA_SWQE_IP_CHECKSUM           0x4000
86 #define EHEA_SWQE_TCP_CHECKSUM          0x2000
87 #define EHEA_SWQE_TSO                   0x1000
88 #define EHEA_SWQE_SIGNALLED_COMPLETION  0x0800
89 #define EHEA_SWQE_VLAN_INSERT           0x0400
90 #define EHEA_SWQE_IMM_DATA_PRESENT      0x0200
91 #define EHEA_SWQE_DESCRIPTORS_PRESENT   0x0100
92 #define EHEA_SWQE_WRAP_CTL_REC          0x0080
93 #define EHEA_SWQE_WRAP_CTL_FORCE        0x0040
94 #define EHEA_SWQE_BIND                  0x0020
95 #define EHEA_SWQE_PURGE                 0x0010
126 			/* 0x30 */
128 			/* 0xd0 */
149 #define EHEA_CQE_VLAN_TAG_XTRACT   0x0400
151 #define EHEA_CQE_TYPE_RQ           0x60
152 #define EHEA_CQE_STAT_ERR_MASK     0x700F
153 #define EHEA_CQE_STAT_FAT_ERR_MASK 0xF
154 #define EHEA_CQE_BLIND_CKSUM       0x8000
155 #define EHEA_CQE_STAT_ERR_TCP      0x4000
156 #define EHEA_CQE_STAT_ERR_IP       0x2000
157 #define EHEA_CQE_STAT_ERR_CRC      0x1000
160 #define EHEA_CQE_STAT_RESET_MASK   0x0002
182 #define EHEA_EQE_VALID           EHEA_BMASK_IBM(0, 0)
195 #define EHEA_AER_RESTYPE_QP  0x8
196 #define EHEA_AER_RESTYPE_CQ  0x4
197 #define EHEA_AER_RESTYPE_EQ  0x3
200 #define EHEA_AER_RESET_MASK   0xFFFFFFFFFEFFFFFFULL
201 #define EHEA_AERR_RESET_MASK  0xFFFFFFFFFFFFFFFFULL
208 #define ERROR_DATA_TYPE    EHEA_BMASK_IBM(0, 7)
229 		queue->current_q_offset = 0;  in hw_qeit_inc()
277 	queue->current_q_offset = 0;  in hw_qeit_reset()
289 		queue->current_q_offset = 0;  in hw_qeit_eq_get_inc()
362 #define EHEA_CQ_REGISTER_ORIG 0
363 #define EHEA_EQ_REGISTER_ORIG 0
366 	EHEA_EQ = 0,		/* event queue              */