Lines Matching +full:0 +full:x2000
39 #define MB 0xff
40 #define MW 0xffff
41 #define MD 0xffffffff
48 #define FS_CI (1<<0)
62 #define FS_ERFBB0 (1<<0) /* - " - */
67 #define FRM_SMT (0) /* asynchr. frames */
85 #define RX_FS_SMT ((long)0<<16) /* SMT frame */
128 #define RD_S_ERFBB 0x00030000L /* received frame byte boundary */
129 #define RD_S_RES2 0x000c0000L /* reserved */
130 #define RD_S_SFRMTY 0x00700000L /* frame type bits */
131 #define RD_S_SADRRG 0x00800000L /* DA == MA or broad-/multicast */
132 #define RD_S_SFRMERR 0x01000000L /* received frame not valid */
133 #define RD_S_SEAC 0x0e000000L /* frame status indicators */
134 #define RD_S_SEAC0 0x02000000L /* frame-copied case-indicator */
135 #define RD_S_SEAC1 0x04000000L /* address-match A-indicator */
136 #define RD_S_SEAC2 0x08000000L /* frame-error E-indicator */
137 #define RD_S_SSRCRTG 0x10000000L /* == 1 SA has MSB set */
138 #define RD_S_RES1 0x20000000L /* reserved */
139 #define RD_S_MSRABT 0x40000000L /* memory status receive abort */
140 #define RD_S_MSVALID 0x80000000L /* memory status valid */
142 #define RD_STATUS 0xffff0000L
143 #define RD_LENGTH 0x0000ffffL
147 #define RD_FRM_SMT (unsigned long)(0<<20) /* asynchr. frames */
154 #define TX_DESCRIPTOR 0x40000000L
155 #define TX_OFFSET_3 0x18000000L
188 #define TD_C_MORE 0x80000000L /* more frame in chain */
189 #define TD_C_DESCR 0x60000000L /* must be TXP1 */
190 #define TD_C_TXFBB 0x18000000L /* byte offset */
191 #define TD_C_XDONE 0x04000000L /* give up token */
192 #define TD_C_NFCS 0x02000000L /* no frame check sequence */
193 #define TD_C_XMTABT 0x01000000L /* transmit abort */
195 #define TD_C_LNCNU 0x0000ff00L
196 #define TD_C_LNCNL 0x000000ffL
197 #define TD_C_LNCN 0x0000ffffL /* frame length lower/upper byte */
218 #define TD_P_CNTRL 0xff000000L
219 #define TD_P_RPXU 0x0000ff00L
220 #define TD_P_RPXL 0x000000ffL
221 #define TD_P_RPX 0x0000ffffL
224 #define TX_PATTERN 0xa0
225 #define TX_POINTER_END 0xa0000000L
226 #define TX_INT_PATTERN 0xa0000000L
241 #define FM_CMDREG1 0x00 /* write command reg 1 instruction */
242 #define FM_CMDREG2 0x01 /* write command reg 2 instruction */
243 #define FM_ST1U 0x00 /* read upper 16-bit of status reg 1 */
244 #define FM_ST1L 0x01 /* read lower 16-bit of status reg 1 */
245 #define FM_ST2U 0x02 /* read upper 16-bit of status reg 2 */
246 #define FM_ST2L 0x03 /* read lower 16-bit of status reg 2 */
247 #define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
248 #define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
249 #define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
250 #define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
251 #define FM_SAID 0x08 /* r/w short addr.-individual */
252 #define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
253 #define FM_LAIC 0x0a /* r/w long addr.-ind. (middle)*/
254 #define FM_LAIL 0x0b /* r/w long addr.-ind. (LSW) */
255 #define FM_SAGP 0x0c /* r/w short address-group */
256 #define FM_LAGM 0x0d /* r/w long addr.-gr. (MSW of LAGP) */
257 #define FM_LAGC 0x0e /* r/w long addr.-gr. (middle) */
258 #define FM_LAGL 0x0f /* r/w long addr.-gr. (LSW) */
259 #define FM_MDREG1 0x10 /* r/w 16-bit mode reg 1 */
260 #define FM_STMCHN 0x11 /* read state-machine reg */
261 #define FM_MIR1 0x12 /* read upper 16-bit of MAC Info Reg */
262 #define FM_MIR0 0x13 /* read lower 16-bit of MAC Info Reg */
263 #define FM_TMAX 0x14 /* r/w 16-bit TMAX reg */
264 #define FM_TVX 0x15 /* write 8-bit TVX reg with NP7-0
265 read TVX on NP7-0, timer on NP15-8*/
266 #define FM_TRT 0x16 /* r/w upper 16-bit of TRT timer */
267 #define FM_THT 0x17 /* r/w upper 16-bit of THT timer */
268 #define FM_TNEG 0x18 /* read upper 16-bit of TNEG (TTRT) */
269 #define FM_TMRS 0x19 /* read lower 5-bit of TNEG,TRT,THT */
270 /* F E D C B A 9 8 7 6 5 4 3 2 1 0
271 x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
272 #define FM_TREQ0 0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */
273 #define FM_TREQ1 0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */
274 #define FM_PRI0 0x1c /* r/w priority r. for asyn.-queue 0 */
275 #define FM_PRI1 0x1d /* r/w priority r. for asyn.-queue 1 */
276 #define FM_PRI2 0x1e /* r/w priority r. for asyn.-queue 2 */
277 #define FM_TSYNC 0x1f /* r/w 16-bit of the TSYNC register */
278 #define FM_MDREG2 0x20 /* r/w 16-bit mode reg 2 */
279 #define FM_FRMTHR 0x21 /* r/w the frame threshold register */
280 #define FM_EACB 0x22 /* r/w end addr of claim/beacon area */
281 #define FM_EARV 0x23 /* r/w end addr of receive queue */
285 #define FM_EAS 0x24 /* r/w end addr of synchr. queue */
286 #define FM_EAA0 0x25 /* r/w end addr of asyn. queue 0 */
287 #define FM_EAA1 0x26 /* r/w end addr of asyn. queue 1 */
288 #define FM_EAA2 0x27 /* r/w end addr of asyn. queue 2 */
289 #define FM_SACL 0x28 /* r/w start addr of claim frame */
290 #define FM_SABC 0x29 /* r/w start addr of beacon frame */
291 #define FM_WPXSF 0x2a /* r/w the write ptr. for special fr.*/
292 #define FM_RPXSF 0x2b /* r/w the read ptr. for special fr. */
293 #define FM_RPR 0x2d /* r/w the read ptr. for receive qu. */
294 #define FM_WPR 0x2e /* r/w the write ptr. for receive qu.*/
295 #define FM_SWPR 0x2f /* r/w the shadow wr.-ptr. for rec.q.*/
301 #define FM_WPXS 0x30 /* r/w the write ptr. for synchr. qu.*/
302 #define FM_WPXA0 0x31 /* r/w the write ptr. for asyn. qu.0 */
303 #define FM_WPXA1 0x32 /* r/w the write ptr. for asyn. qu.1 */
304 #define FM_WPXA2 0x33 /* r/w the write ptr. for asyn. qu.2 */
305 #define FM_SWPXS 0x34 /* r/w the shadow wr.-ptr. for syn.q.*/
306 #define FM_SWPXA0 0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/
307 #define FM_SWPXA1 0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/
308 #define FM_SWPXA2 0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/
309 #define FM_RPXS 0x38 /* r/w the read ptr. for synchr. qu. */
310 #define FM_RPXA0 0x39 /* r/w the read ptr. for asyn. qu. 0 */
311 #define FM_RPXA1 0x3a /* r/w the read ptr. for asyn. qu. 1 */
312 #define FM_RPXA2 0x3b /* r/w the read ptr. for asyn. qu. 2 */
313 #define FM_MARR 0x3c /* r/w the memory read addr register */
314 #define FM_MARW 0x3d /* r/w the memory write addr register*/
315 #define FM_MDRU 0x3e /* r/w upper 16-bit of mem. data reg */
316 #define FM_MDRL 0x3f /* r/w lower 16-bit of mem. data reg */
319 #define FM_TMSYNC 0x40 /* r/w upper 16 bits of TMSYNC timer */
320 #define FM_FCNTR 0x41 /* r/w the 16-bit frame counter */
321 #define FM_LCNTR 0x42 /* r/w the 16-bit lost counter */
322 #define FM_ECNTR 0x43 /* r/w the 16-bit error counter */
325 #define FM_FSCNTR 0x44 /* r/? Frame Strip Counter */
326 #define FM_FRSELREG 0x45 /* r/w Frame Selection Register */
329 #define FM_MDREG3 0x60 /* r/w Mode Register 3 */
330 #define FM_ST3U 0x61 /* read upper 16-bit of status reg 3 */
331 #define FM_ST3L 0x62 /* read lower 16-bit of status reg 3 */
332 #define FM_IMSK3U 0x63 /* r/w upper 16-bit of IMSK reg 3 */
333 #define FM_IMSK3L 0x64 /* r/w lower 16-bit of IMSK reg 3 */
334 #define FM_IVR 0x65 /* read Interrupt Vector register */
335 #define FM_IMR 0x66 /* r/w Interrupt mask register */
336 /* 0x67 Hidden */
337 #define FM_RPR2 0x68 /* r/w the read ptr. for rec. qu. 2 */
338 #define FM_WPR2 0x69 /* r/w the write ptr. for rec. qu. 2 */
339 #define FM_SWPR2 0x6a /* r/w the shadow wptr. for rec. q. 2 */
340 #define FM_EARV2 0x6b /* r/w end addr of rec. qu. 2 */
341 #define FM_UNLCKDLY 0x6c /* r/w Auto Unlock Delay register */
343 /* Bit 7-0: RECV1 unlock threshold */
344 /* 0x6f-0x73 Hidden */
345 #define FM_LTDPA1 0x79 /* r/w Last Trans desc ptr for A1 qu. */
346 /* 0x80-0x9a PLCS registers of built-in PLCS (Supernet 3 only) */
349 #define FM_AFCMD 0xb0 /* r/w Address Filter Command Reg */
350 #define FM_AFSTAT 0xb2 /* r/w Address Filter Status Reg */
351 #define FM_AFBIST 0xb4 /* r/w Address Filter BIST signature */
352 #define FM_AFCOMP2 0xb6 /* r/w Address Filter Comparand 2 */
353 #define FM_AFCOMP1 0xb8 /* r/w Address Filter Comparand 1 */
354 #define FM_AFCOMP0 0xba /* r/w Address Filter Comparand 0 */
355 #define FM_AFMASK2 0xbc /* r/w Address Filter Mask 2 */
356 #define FM_AFMASK1 0xbe /* r/w Address Filter Mask 1 */
357 #define FM_AFMASK0 0xc0 /* r/w Address Filter Mask 0 */
358 #define FM_AFPERS 0xc2 /* r/w Address Filter Personality Reg */
361 #define FM_ORBIST 0xd0 /* r/w Orion BIST signature */
362 #define FM_ORSTAT 0xd2 /* r/w Orion Status Register */
368 #define FM_RES0 0x0001 /* reserved */
370 #define FM_XMTINH_HOLD 0x0002 /* transmit-inhibit/hold bit */
372 #define FM_HOFLXI 0x0003 /* SN3: Hold / Flush / Inhibit */
373 #define FM_FULL_HALF 0x0004 /* full-duplex/half-duplex bit */
374 #define FM_LOCKTX 0x0008 /* lock-transmit-asynchr.-queues bit */
375 #define FM_EXGPA0 0x0010 /* extended-group-addressing bit 0 */
376 #define FM_EXGPA1 0x0020 /* extended-group-addressing bit 1 */
377 #define FM_DISCRY 0x0040 /* disable-carry bit */
379 #define FM_SELRA 0x0080 /* select input from PHY (1=RA,0=RB) */
381 #define FM_ADDET 0x0700 /* address detection */
382 #define FM_MDAMA (0<<8) /* address detection : DA = MA */
391 #define FM_SELSA 0x0800 /* select-short-address bit */
393 #define FM_MMODE 0x7000 /* mode select */
394 #define FM_MINIT (0<<12) /* initialize */
403 #define FM_SNGLFRM 0x8000 /* single-frame-receive mode */
411 #define FM_AFULL 0x000f /* 4-bit value (empty loc.in txqueue)*/
412 #define FM_RCVERR 0x0010 /* rec.-errored-frames bit */
413 #define FM_SYMCTL 0x0020 /* sysmbol-control bit */
415 #define FM_SYNPRQ 0x0040 /* synchron.-NP-DMA-request bit */
416 #define FM_ENNPRQ 0x0080 /* enable-NP-DMA-request bit */
417 #define FM_ENHSRQ 0x0100 /* enable-host-request bit */
418 #define FM_RXFBB01 0x0600 /* rec. frame byte boundary bit0 & 1 */
419 #define FM_LSB 0x0800 /* determ. ordering of bytes in buffer*/
420 #define FM_PARITY 0x1000 /* 1 = even, 0 = odd */
421 #define FM_CHKPAR 0x2000 /* 1 = parity of 32-bit buffer BD-bus*/
422 #define FM_STRPFCS 0x4000 /* 1 = strips FCS field of rec.frame */
423 #define FM_BMMODE 0x8000 /* Buffer-Memory-Mode (1 = tag mode) */
424 /* SN3: 1 = tag, 0 = modified tag */
429 #define FM_STEFRMS 0x0001 /* transmit end of frame: synchr. qu.*/
430 #define FM_STEFRMA0 0x0002 /* transmit end of frame: asyn. qu.0 */
431 #define FM_STEFRMA1 0x0004 /* transmit end of frame: asyn. qu.1 */
432 #define FM_STEFRMA2 0x0008 /* transmit end of frame: asyn. qu.2 */
434 #define FM_STECFRMS 0x0010 /* transmit end of chain of syn. qu. */
436 #define FM_STECFRMA0 0x0020 /* transmit end of chain of asyn. q0 */
438 #define FM_STECFRMA1 0x0040 /* transmit end of chain of asyn. q1 */
440 #define FM_STECMDA1 0x0040 /* SN3: 'no description' */
441 #define FM_STECFRMA2 0x0080 /* transmit end of chain of asyn. q2 */
443 #define FM_STEXDONS 0x0100 /* transmit until XDONE in syn. qu. */
444 #define FM_STBFLA 0x0200 /* asynchr.-queue trans. buffer full */
445 #define FM_STBFLS 0x0400 /* synchr.-queue transm. buffer full */
446 #define FM_STXABRS 0x0800 /* synchr. queue transmit-abort */
447 #define FM_STXABRA0 0x1000 /* asynchr. queue 0 transmit-abort */
448 #define FM_STXABRA1 0x2000 /* asynchr. queue 1 transmit-abort */
449 #define FM_STXABRA2 0x4000 /* asynchr. queue 2 transmit-abort */
451 #define FM_SXMTABT 0x8000 /* transmit abort */
456 #define FM_SQLCKS 0x0001 /* queue lock for synchr. queue */
457 #define FM_SQLCKA0 0x0002 /* queue lock for asynchr. queue 0 */
458 #define FM_SQLCKA1 0x0004 /* queue lock for asynchr. queue 1 */
459 #define FM_SQLCKA2 0x0008 /* queue lock for asynchr. queue 2 */
461 #define FM_STXINFLS 0x0010 /* transmit instruction full: syn. */
463 #define FM_STXINFLA0 0x0020 /* transmit instruction full: asyn.0 */
465 #define FM_STXINFLA1 0x0040 /* transmit instruction full: asyn.1 */
467 #define FM_STXINFLA2 0x0080 /* transmit instruction full: asyn.2 */
469 #define FM_SPCEPDS 0x0100 /* parity/coding error: syn. queue */
470 #define FM_SPCEPDA0 0x0200 /* parity/coding error: asyn. queue0 */
471 #define FM_SPCEPDA1 0x0400 /* parity/coding error: asyn. queue1 */
472 #define FM_SPCEPDA2 0x0800 /* parity/coding error: asyn. queue2 */
474 #define FM_STBURS 0x1000 /* transmit buffer underrun: syn. q. */
475 #define FM_STBURA0 0x2000 /* transmit buffer underrun: asyn.0 */
476 #define FM_STBURA1 0x4000 /* transmit buffer underrun: asyn.1 */
477 #define FM_STBURA2 0x8000 /* transmit buffer underrun: asyn.2 */
483 #define FM_SOTRBEC 0x0001 /* other beacon received */
484 #define FM_SMYBEC 0x0002 /* my beacon received */
485 #define FM_SBEC 0x0004 /* beacon state entered */
486 #define FM_SLOCLM 0x0008 /* low claim received */
487 #define FM_SHICLM 0x0010 /* high claim received */
488 #define FM_SMYCLM 0x0020 /* my claim received */
489 #define FM_SCLM 0x0040 /* claim state entered */
490 #define FM_SERRSF 0x0080 /* error in special frame */
491 #define FM_SNFSLD 0x0100 /* NP and FORMAC+ simultaneous load */
492 #define FM_SRFRCTOV 0x0200 /* receive frame counter overflow */
494 #define FM_SRCVFRM 0x0400 /* receive frame */
496 #define FM_SRCVOVR 0x0800 /* receive FIFO overflow */
497 #define FM_SRBFL 0x1000 /* receive buffer full */
498 #define FM_SRABT 0x2000 /* receive abort */
499 #define FM_SRBMT 0x4000 /* receive buffer empty */
500 #define FM_SRCOMP 0x8000 /* receive complete. Nontag mode */
506 #define FM_SRES0 0x0001 /* reserved */
507 #define FM_SESTRIPTK 0x0001 /* SN3: 'no description' */
508 #define FM_STRTEXR 0x0002 /* TRT expired in claim | beacon st. */
509 #define FM_SDUPCLM 0x0004 /* duplicate claim received */
510 #define FM_SSIFG 0x0008 /* short interframe gap */
511 #define FM_SFRMCTR 0x0010 /* frame counter overflow */
512 #define FM_SERRCTR 0x0020 /* error counter overflow */
513 #define FM_SLSTCTR 0x0040 /* lost counter overflow */
514 #define FM_SPHINV 0x0080 /* PHY invalid */
515 #define FM_SADET 0x0100 /* address detect */
516 #define FM_SMISFRM 0x0200 /* missed frame */
517 #define FM_STRTEXP 0x0400 /* TRT expired and late count > 0 */
518 #define FM_STVXEXP 0x0800 /* TVX expired */
519 #define FM_STKISS 0x1000 /* token issued */
520 #define FM_STKERR 0x2000 /* token error */
521 #define FM_SMULTDA 0x4000 /* multiple destination address */
522 #define FM_SRNGOP 0x8000 /* ring operational */
528 #define FM_SRQUNLCK1 0x0001 /* receive queue unlocked queue 1 */
529 #define FM_SRQUNLCK2 0x0002 /* receive queue unlocked queue 2 */
530 #define FM_SRPERRQ1 0x0004 /* receive parity error rx queue 1 */
531 #define FM_SRPERRQ2 0x0008 /* receive parity error rx queue 2 */
533 #define FM_SRCVOVR2 0x0800 /* receive FIFO overfull rx queue 2 */
534 #define FM_SRBFL2 0x1000 /* receive buffer full rx queue 2 */
535 #define FM_SRABT2 0x2000 /* receive abort rx queue 2 */
536 #define FM_SRBMT2 0x4000 /* receive buf empty rx queue 2 */
537 #define FM_SRCOMP2 0x8000 /* receive comp rx queue 2 */
543 #define FM_AF_BIST_DONE 0x0001 /* Address Filter BIST is done */
544 #define FM_PLC_BIST_DONE 0x0002 /* internal PLC Bist is done */
545 #define FM_PDX_BIST_DONE 0x0004 /* PDX BIST is done */
547 #define FM_SICAMDAMAT 0x0010 /* Status internal CAM DA match */
548 #define FM_SICAMDAXACT 0x0020 /* Status internal CAM DA exact match */
549 #define FM_SICAMSAMAT 0x0040 /* Status internal CAM SA match */
550 #define FM_SICAMSAXACT 0x0080 /* Status internal CAM SA exact match */
555 #define FM_MDRTAG 0x0004 /* tag bit of long word read */
556 #define FM_SNPPND 0x0008 /* r/w from buffer mem. is pending */
557 #define FM_TXSTAT 0x0070 /* transmitter state machine state */
558 #define FM_RCSTAT 0x0380 /* receiver state machine state */
559 #define FM_TM01 0x0c00 /* indicate token mode */
560 #define FM_SIM 0x1000 /* indicate send immediate-mode */
561 #define FM_REV 0xe000 /* FORMAC Plus revision number */
567 #define FM_MENRS 0x0001 /* Ena enhanced rec status encoding */
568 #define FM_MENXS 0x0002 /* Ena enhanced xmit status encoding */
569 #define FM_MENXCT 0x0004 /* Ena EXACT/INEXACT matching */
570 #define FM_MENAFULL 0x0008 /* Ena enh QCTRL encoding for AFULL */
571 #define FM_MEIND 0x0030 /* Ena enh A,C indicator settings */
572 #define FM_MENQCTRL 0x0040 /* Ena enh QCTRL encoding */
573 #define FM_MENRQAUNLCK 0x0080 /* Ena rec q auto unlock */
574 #define FM_MENDAS 0x0100 /* Ena DAS connections by cntr MUX */
575 #define FM_MENPLCCST 0x0200 /* Ena Counter Segm test in PLC blck */
576 #define FM_MENSGLINT 0x0400 /* Ena Vectored Interrupt reading */
577 #define FM_MENDRCV 0x0800 /* Ena dual receive queue operation */
578 #define FM_MENFCLOC 0x3000 /* Ena FC location within frm data */
579 #define FM_MENTRCMD 0x4000 /* Ena ASYNC1 xmit only after command */
580 #define FM_MENTDLPBK 0x8000 /* Ena TDAT to RDAT lkoopback */
586 #define FM_RECV1 0x000f /* options for receive queue 1 */
587 #define FM_RCV1_ALL (0<<0) /* receive all frames */
588 #define FM_RCV1_LLC (1<<0) /* rec all LLC frames */
589 #define FM_RCV1_SMT (2<<0) /* rec all SMT frames */
590 #define FM_RCV1_NSMT (3<<0) /* rec non-SMT frames */
591 #define FM_RCV1_IMP (4<<0) /* rec Implementor frames */
592 #define FM_RCV1_MAC (5<<0) /* rec all MAC frames */
593 #define FM_RCV1_SLLC (6<<0) /* rec all sync LLC frames */
594 #define FM_RCV1_ALLC (7<<0) /* rec all async LLC frames */
595 #define FM_RCV1_VOID (8<<0) /* rec all void frames */
596 #define FM_RCV1_ALSMT (9<<0) /* rec all async LLC & SMT frames */
597 #define FM_RECV2 0x00f0 /* options for receive queue 2 */
598 #define FM_RCV2_ALL (0<<4) /* receive all other frames */
608 #define FM_ENXMTADSWAP 0x4000 /* enh rec addr swap (phys -> can) */
609 #define FM_ENRCVADSWAP 0x8000 /* enh tx addr swap (can -> phys) */
615 #define FM_INST 0x0007 /* Address Filter Operation */
616 #define FM_IINV_CAM (0<<0) /* Invalidate CAM */
617 #define FM_IWRITE_CAM (1<<0) /* Write CAM */
618 #define FM_IREAD_CAM (2<<0) /* Read CAM */
619 #define FM_IRUN_BIST (3<<0) /* Run BIST */
620 #define FM_IFIND (4<<0) /* Find */
621 #define FM_IINV (5<<0) /* Invalidate */
622 #define FM_ISKIP (6<<0) /* Skip */
623 #define FM_ICL_SKIP (7<<0) /* Clear all SKIP bits */
629 /* Bit 0-4: reserved */
630 #define FM_REV_NO 0x00e0 /* Revision Number of Address Filter */
631 #define FM_BIST_DONE 0x0100 /* BIST complete */
632 #define FM_EMPTY 0x0200 /* CAM empty */
633 #define FM_ERROR 0x0400 /* Error (improper operation) */
634 #define FM_MULT 0x0800 /* Multiple Match */
635 #define FM_EXACT 0x1000 /* Exact Match */
636 #define FM_FOUND 0x2000 /* Comparand found in CAM */
637 #define FM_FULL 0x4000 /* CAM full */
638 #define FM_DONE 0x8000 /* DONE indicator */
644 #define AF_BIST_SIGNAT 0x0553 /* Address Filter BIST Signature */
650 #define FM_VALID 0x0001 /* CAM Entry Valid */
651 #define FM_DA 0x0002 /* Destination Address */
652 #define FM_DAX 0x0004 /* Destination Address Exact */
653 #define FM_SA 0x0008 /* Source Address */
654 #define FM_SAX 0x0010 /* Source Address Exact */
655 #define FM_SKIP 0x0020 /* Skip this entry */
658 * instruction set for command register 1 (NPADDR6-0 = 0x00)
660 #define FM_IRESET 0x01 /* software reset */
661 #define FM_IRMEMWI 0x02 /* load Memory Data Reg., inc MARR */
662 #define FM_IRMEMWO 0x03 /* load MDR from buffer memory, n.i. */
663 #define FM_IIL 0x04 /* idle/listen */
664 #define FM_ICL 0x05 /* claim/listen */
665 #define FM_IBL 0x06 /* beacon/listen */
666 #define FM_ILTVX 0x07 /* load TVX timer from TVX reg */
667 #define FM_INRTM 0x08 /* nonrestricted token mode */
668 #define FM_IENTM 0x09 /* enter nonrestricted token mode */
669 #define FM_IERTM 0x0a /* enter restricted token mode */
670 #define FM_IRTM 0x0b /* restricted token mode */
671 #define FM_ISURT 0x0c /* send unrestricted token */
672 #define FM_ISRT 0x0d /* send restricted token */
673 #define FM_ISIM 0x0e /* enter send-immediate mode */
674 #define FM_IESIM 0x0f /* exit send-immediate mode */
675 #define FM_ICLLS 0x11 /* clear synchronous queue lock */
676 #define FM_ICLLA0 0x12 /* clear asynchronous queue 0 lock */
677 #define FM_ICLLA1 0x14 /* clear asynchronous queue 1 lock */
678 #define FM_ICLLA2 0x18 /* clear asynchronous queue 2 lock */
680 #define FM_ICLLR 0x20 /* clear receive queue (SN3:1) lock */
681 #define FM_ICLLR2 0x21 /* SN3: clear receive queue 2 lock */
682 #define FM_ITRXBUS 0x22 /* SN3: Tristate X-Bus (SAS only) */
683 #define FM_IDRXBUS 0x23 /* SN3: drive X-Bus */
684 #define FM_ICLLAL 0x3f /* clear all queue locks */
687 * instruction set for command register 2 (NPADDR6-0 = 0x01)
689 #define FM_ITRS 0x01 /* transmit synchronous queue */
691 #define FM_ITRA0 0x02 /* transmit asynchronous queue 0 */
693 #define FM_ITRA1 0x04 /* transmit asynchronous queue 1 */
695 #define FM_ITRA2 0x08 /* transmit asynchronous queue 2 */
697 #define FM_IACTR 0x10 /* abort current transmit activity */
698 #define FM_IRSTQ 0x20 /* reset transmit queues */
699 #define FM_ISTTB 0x30 /* set tag bit */
700 #define FM_IERSF 0x40 /* enable receive single frame */
702 #define FM_ITR 0x50 /* SN3: Transmit Command */
712 #define PL_CNTRL_A 0x00 /* control register A (r/w) */
713 #define PL_CNTRL_B 0x01 /* control register B (r/w) */
714 #define PL_INTR_MASK 0x02 /* interrupt mask (r/w) */
715 #define PL_XMIT_VECTOR 0x03 /* transmit vector register (r/w) */
716 #define PL_VECTOR_LEN 0x04 /* transmit vector length (r/w) */
717 #define PL_LE_THRESHOLD 0x05 /* link error event threshold (r/w) */
718 #define PL_C_MIN 0x06 /* minimum connect state time (r/w) */
719 #define PL_TL_MIN 0x07 /* min. line state transmit t. (r/w) */
720 #define PL_TB_MIN 0x08 /* minimum break time (r/w) */
721 #define PL_T_OUT 0x09 /* signal timeout (r/w) */
722 #define PL_CNTRL_C 0x0a /* control register C (r/w) */
723 #define PL_LC_LENGTH 0x0b /* link confidence test time (r/w) */
724 #define PL_T_SCRUB 0x0c /* scrub time = MAC TVX (r/w) */
725 #define PL_NS_MAX 0x0d /* max. noise time before break (r/w)*/
726 #define PL_TPC_LOAD_V 0x0e /* TPC timer load value (write only) */
727 #define PL_TNE_LOAD_V 0x0f /* TNE timer load value (write only) */
728 #define PL_STATUS_A 0x10 /* status register A (read only) */
729 #define PL_STATUS_B 0x11 /* status register B (read only) */
730 #define PL_TPC 0x12 /* timer for PCM (ro) [20.48 us] */
731 #define PL_TNE 0x13 /* time of noise event [0.32 us] */
732 #define PL_CLK_DIV 0x14 /* TNE clock divider (read only) */
733 #define PL_BIST_SIGNAT 0x15 /* built in self test signature (ro)*/
734 #define PL_RCV_VECTOR 0x16 /* receive vector reg. (read only) */
735 #define PL_INTR_EVENT 0x17 /* interrupt event reg. (read only) */
736 #define PL_VIOL_SYM_CTR 0x18 /* violation symbol count. (read o) */
737 #define PL_MIN_IDLE_CTR 0x19 /* minimum idle counter (read only) */
738 #define PL_LINK_ERR_CTR 0x1a /* link error event ctr.(read only) */
740 #define PL_T_FOT_ASS 0x1e /* FOTOFF Assert Timer */
741 #define PL_T_FOT_DEASS 0x1f /* FOTOFF Deassert Timer */
749 #define QELM_XBAR_W 0x80 /* Crossbar Control ELM W */
750 #define QELM_XBAR_X 0x81 /* Crossbar Control ELM X */
751 #define QELM_XBAR_Y 0x82 /* Crossbar Control ELM Y */
752 #define QELM_XBAR_Z 0x83 /* Crossbar Control ELM Z */
753 #define QELM_XBAR_P 0x84 /* Crossbar Control Bus P */
754 #define QELM_XBAR_S 0x85 /* Crossbar Control Bus S */
755 #define QELM_XBAR_R 0x86 /* Crossbar Control Bus R */
756 #define QELM_WR_XBAR 0x87 /* Write the Crossbar now (write) */
757 #define QELM_CTR_W 0x88 /* Counter W */
758 #define QELM_CTR_X 0x89 /* Counter X */
759 #define QELM_CTR_Y 0x8a /* Counter Y */
760 #define QELM_CTR_Z 0x8b /* Counter Z */
761 #define QELM_INT_MASK 0x8c /* Interrupt mask register */
762 #define QELM_INT_DATA 0x8d /* Interrupt data (event) register */
763 #define QELM_ELMB 0x00 /* Elm base */
764 #define QELM_ELM_SIZE 0x20 /* ELM size */
767 * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
771 #define PL_RUN_BIST 0x0001 /* begin running its Built In Self T.*/
772 #define PL_RF_DISABLE 0x0002 /* disable the Repeat Filter state m.*/
773 #define PL_SC_REM_LOOP 0x0004 /* remote loopback path */
774 #define PL_SC_BYPASS 0x0008 /* by providing a physical bypass */
775 #define PL_LM_LOC_LOOP 0x0010 /* loop path just after elastic buff.*/
776 #define PL_EB_LOC_LOOP 0x0020 /* loop path just prior to PDT/PDR IF*/
777 #define PL_FOT_OFF 0x0040 /* assertion of /FOTOFF pin of PLC */
778 #define PL_LOOPBACK 0x0080 /* it cause the /LPBCK pin ass. low */
779 #define PL_MINI_CTR_INT 0x0100 /* partially contr. when bit is ass. */
780 #define PL_VSYM_CTR_INT 0x0200 /* controls when int bit is asserted */
781 #define PL_ENA_PAR_CHK 0x0400 /* enable parity check */
782 #define PL_REQ_SCRUB 0x0800 /* limited access to scrub capability*/
783 #define PL_TPC_16BIT 0x1000 /* causes the TPC as a 16 bit timer */
784 #define PL_TNE_16BIT 0x2000 /* causes the TNE as a 16 bit timer */
785 #define PL_NOISE_TIMER 0x4000 /* allows the noise timing function */
788 * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
792 #define PL_PCM_CNTRL 0x0003 /* control PCM state machine */
793 #define PL_PCM_NAF (0) /* state is not affected */
798 #define PL_MAINT 0x0004 /* if OFF state --> MAINT state */
799 #define PL_LONG 0x0008 /* perf. a long Link Confid.Test(LCT)*/
800 #define PL_PC_JOIN 0x0010 /* if NEXT state --> JOIN state */
802 #define PL_PC_LOOP 0x0060 /* loopback used in the LCT */
803 #define PL_NOLCT (0<<5) /* no LCT is performed */
808 #define PL_CLASS_S 0x0080 /* signif. that single att. station */
810 #define PL_MAINT_LS 0x0700 /* line state while in the MAINT st. */
811 #define PL_M_QUI0 (0<<8) /* transmit QUIET line state */
820 #define PL_MATCH_LS 0x7800 /* line state to be comp. with curr.*/
821 #define PL_I_ANY (0<<11) /* Int. on any change in *_LINE_ST */
827 #define PL_CONFIG_CNTRL 0x8000 /* control over scrub, byp. & loopb.*/
830 * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
833 #define PL_C_CIPHER_ENABLE (1<<0) /* enable scrambler */
839 #define PL_C_FOTOFF_TIM (0<<2) /* FOTOFF use timer for (de)-assert */
843 #define PL_C_RXDATA_EN (1<<5) /* Rec scr data forced to 0 */
847 #define PL_C_FOTOFF_0 (0<<8) /* timer off */
852 #define PL_C_SDON_084 (0<<10) /* 0.84 uS */
857 #define PL_C_SOFF_076 (0<<12) /* 0.76 uS */
865 * PLC status register A (PL_STATUS_A: log. addr. 0x10)
870 #define PLC_INT_MASK 0xc000 /* ELM integration bits in status A */
871 #define PLC_INT_C 0x0000 /* ELM Revision Band C */
872 #define PLC_INT_CAMEL 0x4000 /* ELM integrated into CAMEL */
873 #define PLC_INT_QE 0x8000 /* ELM integrated into Quad ELM */
874 #define PLC_REV_MASK 0x3800 /* revision bits in status A */
875 #define PLC_REVISION_B 0x0000 /* rev bits for ELM Rev B */
876 #define PLC_REVISION_QA 0x0800 /* rev bits for ELM core in QELM-A */
878 #define PLC_REV_MASK 0xf800 /* revision bits in status A */
879 #define PLC_REVISION_A 0x0000 /* revision bits for PLC */
880 #define PLC_REVISION_S 0xf800 /* revision bits for PLC-S */
881 #define PLC_REV_SN3 0x7800 /* revision bits for PLC-S in IFCP */
883 #define PL_SYM_PR_CTR 0x0007 /* contains the LSM symbol pair Ctr. */
884 #define PL_UNKN_LINE_ST 0x0008 /* unknown line state bit from LSM */
885 #define PL_LSM_STATE 0x0010 /* state bit of LSM */
887 #define PL_LINE_ST 0x00e0 /* contains recogn. line state of LSM*/
888 #define PL_L_NLS (0<<5) /* noise line state */
897 #define PL_PREV_LINE_ST 0x0300 /* value of previous line state */
898 #define PL_P_QLS (0<<8) /* quiet line state */
903 #define PL_SIGNAL_DET 0x0400 /* 1=that signal detect is deasserted*/
907 * PLC status register B (PL_STATUS_B: log. addr. 0x11)
910 #define PL_BREAK_REASON 0x0007 /* reason for PCM state mach.s to br.*/
911 #define PL_B_NOT (0) /* PCM SM has not gone to BREAK state*/
919 #define PL_TCF 0x0008 /* transmit code flag (start exec.) */
920 #define PL_RCF 0x0010 /* receive code flag (start exec.) */
921 #define PL_LSF 0x0020 /* line state flag (l.s. has been r.)*/
922 #define PL_PCM_SIGNAL 0x0040 /* indic. that XMIT_VECTOR hb.written*/
924 #define PL_PCM_STATE 0x0780 /* state bits of PCM state machine */
925 #define PL_PC0 (0<<7) /* OFF - when /RST or PCM_CNTRL */
937 #define PL_PCI_SCRUB 0x0800 /* scrubbing function is being exec. */
939 #define PL_PCI_STATE 0x3000 /* Physical Connect. Insertion SM */
940 #define PL_CI_REMV (0<<12) /* REMOVED */
945 #define PL_RF_STATE 0xc000 /* state bit of repeate filter SM */
946 #define PL_RF_REPT (0<<14) /* REPEAT */
953 * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17)
957 #define PL_PARITY_ERR 0x0001 /* p. error h.b.detected on TX9-0 inp*/
958 #define PL_LS_MATCH 0x0002 /* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/
959 #define PL_PCM_CODE 0x0004 /* transmit&receive | LCT complete */
960 #define PL_TRACE_PROP 0x0008 /* master l.s. while PCM ACTIV|TRACE */
961 #define PL_SELF_TEST 0x0010 /* QUIET|HALT while PCM in TRACE st. */
962 #define PL_PCM_BREAK 0x0020 /* PCM has entered the BREAK state */
963 #define PL_PCM_ENABLED 0x0040 /* asserted SC_JOIN, scrub. & ACTIV */
964 #define PL_TPC_EXPIRED 0x0080 /* TPC timer reached zero */
965 #define PL_TNE_EXPIRED 0x0100 /* TNE timer reached zero */
966 #define PL_EBUF_ERR 0x0200 /* elastic buff. det. over-|underflow*/
967 #define PL_PHYINV 0x0400 /* physical layer invalid signal */
968 #define PL_VSYM_CTR 0x0800 /* violation symbol counter has incr.*/
969 #define PL_MINI_CTR 0x1000 /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
970 #define PL_LE_CTR 0x2000 /* link error event counter */
971 #define PL_LSDO 0x4000 /* SDO input pin changed to a 1 */
972 #define PL_NP_ERR 0x8000 /* NP has requested to r/w an inv. r.*/
975 * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is
984 #define QELM_XOUT_IDLE 0x0000 /* Idles/Passthrough */
985 #define QELM_XOUT_P 0x0001 /* Output to: Bus P */
986 #define QELM_XOUT_S 0x0002 /* Output to: Bus S */
987 #define QELM_XOUT_R 0x0003 /* Output to: Bus R */
988 #define QELM_XOUT_W 0x0004 /* Output to: ELM W */
989 #define QELM_XOUT_X 0x0005 /* Output to: ELM X */
990 #define QELM_XOUT_Y 0x0006 /* Output to: ELM Y */
991 #define QELM_XOUT_Z 0x0007 /* Output to: ELM Z */
1004 #define QELM_ELM_W (1<<0) /* ELM W Interrupt */
1009 #define TP_C_MIN 0xff9c /* 2 ms */
1010 #define TP_TL_MIN 0xfff0 /* 0.3 ms */
1011 #define TP_TB_MIN 0xff10 /* 5 ms */
1012 #define TP_T_OUT 0xd9db /* 200 ms */
1013 #define TP_LC_LENGTH 0xf676 /* 50 ms */
1014 #define TP_LC_LONGLN 0xa0a2 /* 500 ms */
1015 #define TP_T_SCRUB 0xff6d /* 3.5 ms */
1016 #define TP_NS_MAX 0xf021 /* 1.3 ms */
1021 #define PLC_BIST 0x6ecd /* BIST signature for PLC */
1022 #define PLCS_BIST 0x5b6b /* BIST signature for PLC-S */
1023 #define PLC_ELM_B_BIST 0x6ecd /* BIST signature of ELM Rev. B */
1024 #define PLC_ELM_D_BIST 0x5b6b /* BIST signature of ELM Rev. D */
1025 #define PLC_CAM_A_BIST 0x9e75 /* BIST signature of CAMEL Rev. A */
1026 #define PLC_CAM_B_BIST 0x5b6b /* BIST signature of CAMEL Rev. B */
1027 #define PLC_IFD_A_BIST 0x9e75 /* BIST signature of IFDDI Rev. A */
1028 #define PLC_IFD_B_BIST 0x5b6b /* BIST signature of IFDDI Rev. B */
1029 #define PLC_QELM_A_BIST 0x5b6b /* BIST signature of QELM Rev. A */
1036 * request register array (log. addr: RQA_A + a<<1 {a=0..7}) write only.
1039 #define RQ_NOT 0 /* not request */
1044 #define RQ_WA0 5 /* write requ.: asynchronous queue 0 */