Lines Matching +full:0 +full:x2000
12 #define OFFSET_(x) ((x) & 0x0000FFFF)
15 #define IMASK_IVG15 0x8000
16 #define IMASK_IVG14 0x4000
17 #define IMASK_IVG13 0x2000
18 #define IMASK_IVG12 0x1000
20 #define IMASK_IVG11 0x0800
21 #define IMASK_IVG10 0x0400
22 #define IMASK_IVG9 0x0200
23 #define IMASK_IVG8 0x0100
25 #define IMASK_IVG7 0x0080
26 #define IMASK_IVGTMR 0x0040
27 #define IMASK_IVGHW 0x0020
39 #define WAY0_L 0x1
40 #define WAY1_L 0x2
41 #define WAY01_L 0x3
42 #define WAY2_L 0x4
43 #define WAY02_L 0x5
44 #define WAY12_L 0x6
45 #define WAY012_L 0x7
47 #define WAY3_L 0x8
48 #define WAY03_L 0x9
49 #define WAY13_L 0xA
50 #define WAY013_L 0xB
52 #define WAY32_L 0xC
53 #define WAY320_L 0xD
54 #define WAY321_L 0xE
55 #define WAYALL_L 0xF
60 #define RTC_ERROR_BIT 0x0FFFFFFF
61 #define UART_ERROR_BIT 0xF0FFFFFF
62 #define SPORT1_ERROR_BIT 0xFF0FFFFF
63 #define SPI_ERROR_BIT 0xFFF0FFFF
64 #define SPORT0_ERROR_BIT 0xFFFF0FFF
65 #define PPI_ERROR_BIT 0xFFFFF0FF
66 #define DMA_ERROR_BIT 0xFFFFFF0F
67 #define PLLWAKE_ERROR_BIT 0xFFFFFFFF
70 #define DMA7_UARTTX_BIT 0x0FFFFFFF
71 #define DMA6_UARTRX_BIT 0xF0FFFFFF
72 #define DMA5_SPI_BIT 0xFF0FFFFF
73 #define DMA4_SPORT1TX_BIT 0xFFF0FFFF
74 #define DMA3_SPORT1RX_BIT 0xFFFF0FFF
75 #define DMA2_SPORT0TX_BIT 0xFFFFF0FF
76 #define DMA1_SPORT0RX_BIT 0xFFFFFF0F
77 #define DMA0_PPI_BIT 0xFFFFFFFF
80 #define WDTIMER_BIT 0x0FFFFFFF
81 #define MEMDMA1_BIT 0xF0FFFFFF
82 #define MEMDMA0_BIT 0xFF0FFFFF
83 #define PFB_BIT 0xFFF0FFFF
84 #define PFA_BIT 0xFFFF0FFF
85 #define TIMER2_BIT 0xFFFFF0FF
86 #define TIMER1_BIT 0xFFFFFF0F
87 #define TIMER0_BIT 0xFFFFFFFF
97 #define V_AMBEN 0x0
111 #define V_AMCKEN 0x0
114 #define V_CDPRIO 0x100
116 #define V_CDPRIO 0x0
123 #define CPUID 0x27a5
127 #define CPUID 0x27a5
131 #define CPUID 0x27a5