Lines Matching +full:0 +full:x2000

8 #define	PIIX_PM_START		0x0F80
10 #define	SIO_GPIO_START		0x0FC0
12 #define	SIO_PM_START		0x0FC8
15 #define	GPIREG0			(PMBASE+0x30)
31 #define	SIO_INDEX		0x2e
32 #define	SIO_DATA		0x2f
34 #define	SIO_DEV_SEL		0x7
35 #define	SIO_DEV_ENB		0x30
36 #define	SIO_DEV_MSB		0x60
37 #define	SIO_DEV_LSB		0x61
39 #define	SIO_GP_DEV		0x7
43 #define	SIO_GP_LSB		(SIO_GP_BASE&0xff)
45 #define	SIO_GP_DATA1		(SIO_GP_BASE+0)
47 #define	SIO_PM_DEV		0x8
51 #define	SIO_PM_LSB		(SIO_PM_BASE&0xff)
52 #define	SIO_PM_INDEX		(SIO_PM_BASE+0)
55 #define	SIO_PM_FER2		0x1
57 #define	SIO_PM_GP_EN		0x80
65 #define SPECIAL_DEV		0xff
66 #define SPECIAL_REG		0x00
74 #define PIIX_SPECIAL_STOP		0x00120002
76 #define PIIX4_RESET_PORT	0xcf9
77 #define PIIX4_RESET_VAL		0x6
79 #define PMSTS_PORT		0xf80	// 2 bytes	PM Status
80 #define PMEN_PORT		0xf82	// 2 bytes	PM Enable
81 #define	PMCNTRL_PORT		0xf84	// 2 bytes	PM Control
83 #define PM_SUSPEND_ENABLE	0x2000	// start sequence to suspend state
95 #define PM_STS_TMROF		(1<<0)	// Timer Overflow Status.
100 #define PIIX_GPIREG0			(0xf80 + 0x30)
105 #define	PIIX_GPI_STPCLK		0x4	// STPCLK signal routed back in