Lines Matching +full:0 +full:x2000
32 #define SPI_ADRS_READ_BIT_15 0x8000
34 #define SPI_ADRS_ARM_INTERRUPTS 0x00
35 #define SPI_ADRS_ARM_INT_EN 0x04
37 #define SPI_ADRS_HOST_INTERRUPTS 0x08
38 #define SPI_ADRS_HOST_INT_EN 0x0c
39 #define SPI_ADRS_HOST_INT_ACK 0x10
41 #define SPI_ADRS_GEN_PURP_1 0x14
42 #define SPI_ADRS_GEN_PURP_2 0x18
44 #define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */
46 #define SPI_ADRS_DMA_DATA 0x28
48 #define SPI_ADRS_DMA_WRITE_CTRL 0x2c
49 #define SPI_ADRS_DMA_WRITE_LEN 0x2e
50 #define SPI_ADRS_DMA_WRITE_BASE 0x30
52 #define SPI_ADRS_DMA_READ_CTRL 0x34
53 #define SPI_ADRS_DMA_READ_LEN 0x36
54 #define SPI_ADRS_DMA_READ_BASE 0x38
56 #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000
57 #define SPI_CTRL_STAT_START_HALTED 0x4000
58 #define SPI_CTRL_STAT_RAM_BOOT 0x2000
59 #define SPI_CTRL_STAT_HOST_RESET 0x1000
60 #define SPI_CTRL_STAT_HOST_CPU_EN 0x0800
62 #define SPI_DMA_WRITE_CTRL_ENABLE 0x0001
63 #define SPI_DMA_READ_CTRL_ENABLE 0x0001
72 #define SPI_TARGET_INT_WAKEUP 0x00000001
73 #define SPI_TARGET_INT_SLEEP 0x00000002
74 #define SPI_TARGET_INT_RDDONE 0x00000004
76 #define SPI_TARGET_INT_CTS 0x00004000
77 #define SPI_TARGET_INT_DR 0x00008000
79 #define SPI_HOST_INT_READY 0x00000001
80 #define SPI_HOST_INT_WR_READY 0x00000002
81 #define SPI_HOST_INT_SW_UPDATE 0x00000004
82 #define SPI_HOST_INT_UPDATE 0x10000000
85 #define SPI_HOST_INT_CR 0x00004000
88 #define SPI_HOST_INT_DR 0x00008000