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/linux-3.3/fs/cachefiles/
Dkey.c16 "0123456789" /* 0 - 9 */
17 "abcdefghijklmnopqrstuvwxyz" /* 10 - 35 */
18 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" /* 36 - 61 */
19 "_-" /* 62 - 63 */
24 [33 ... 46] = 1, /* '!' -> '.' */
26 [48 ... 127] = 1, /* '0' -> '~' */
31 * - the raw key should include the length in the two bytes at the front
32 * - the key may be up to 514 bytes in length (including the length word)
33 * - "base64" encode the strange keys, mapping 3 bytes of raw to four of
35 * - need to cut the cooked key into 252 char lengths (189 raw bytes)
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/linux-3.3/drivers/gpu/drm/i915/
Di915_debugfs.c60 struct drm_info_node *node = (struct drm_info_node *) m->private; in i915_capabilities()
61 struct drm_device *dev = node->minor->dev; in i915_capabilities()
64 seq_printf(m, "gen: %d\n", info->gen); in i915_capabilities()
66 #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) in i915_capabilities()
93 if (obj->user_pin_count > 0) in get_pin_flag()
95 else if (obj->pin_count > 0) in get_pin_flag()
103 switch (obj->tiling_mode) { in get_tiling_flag()
125 &obj->base, in describe_obj()
128 obj->base.size / 1024, in describe_obj()
129 obj->base.read_domains, in describe_obj()
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Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
64 int min, max; member
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
102 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fdi_link_freq()
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
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Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
181 * - One can actually load arbitrary many arbitrary registers: Simply issue x
184 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
245 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
279 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
287 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
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/linux-3.3/sound/pci/lx6464es/
Dlx_defs.h1 /* -*- linux-c -*- *
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
31 * [ 44k - ( 44.1k + 48k ) / 2 ]
90 #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
95 /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
145 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
147 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
185 SF_XRUN = 0x20000000, /* the stream is un x-run state. */
296 #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
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/linux-3.3/drivers/video/console/
Dfbcon.h2 * linux/drivers/video/console/fbcon.h -- Low level frame buffer based console driver
24 * This is the interface between the low-level console driver and the
25 * low-level frame buffer device
29 /* Filled in by the low-level console driver */
112 max_len = max(info->var.green.length, info->var.red.length); in mono_col()
113 max_len = max(info->var.blue.length, max_len); in mono_col()
128 if (vc->vc_can_do_color) in attr_col_ec()
129 return is_fg ? attr_fgcol(shift,vc->vc_video_erase_char) in attr_col_ec()
130 : attr_bgcol(shift,vc->vc_video_erase_char); in attr_col_ec()
136 is_mono01 = info->fix.visual == FB_VISUAL_MONO01; in attr_col_ec()
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/linux-3.3/drivers/gpu/drm/vmwgfx/
Dsvga3d_reg.h2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
27 * svga3d_reg.h --
43 * us make new guest drivers which are backwards-compatible with old
68 typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
80 * human-readable names in GLUtil_GetFormatName.
115 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
116 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
131 /* Single- and dual-component floating point formats */
191 * This format can be used as a render target if the current display mode
193 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
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Dsvga_reg.h2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
27 * svga_reg.h --
51 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
154 /* Legacy multi-monitor support */
169 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
200 * SVGA_REG_GMR_ID --
203 * This register holds the 32-bit ID (a small positive integer)
205 * has no side-effects.
207 * SVGA_REG_GMR_DESCRIPTOR --
209 * Write-only.
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/linux-3.3/drivers/staging/iio/dac/
Dad5421.c6 * Licensed under the GPL-2.
61 * struct ad5421_state - driver instance specific data
100 .channel = -1,
110 st->data[0].d32 = cpu_to_be32((reg << 16) | val); in ad5421_write_unlocked()
112 return spi_write(st->spi, &st->data[0].d8[1], 3); in ad5421_write_unlocked()
120 mutex_lock(&indio_dev->mlock); in ad5421_write()
122 mutex_unlock(&indio_dev->mlock); in ad5421_write()
134 .tx_buf = &st->data[0].d8[1], in ad5421_read()
138 .rx_buf = &st->data[1].d8[1], in ad5421_read()
147 mutex_lock(&indio_dev->mlock); in ad5421_read()
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/linux-3.3/include/drm/
Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
33 * subject to backwards-compatibility constraints.
47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
339 /* Allow memory manager to be torn down and re-initialized (eg on
384 * The (page-aligned) allocated size for the object will be returned.
407 * This is a fixed-size type for 32/64 compatibility.
423 * This is a fixed-size type for 32/64 compatibility.
437 * The value will be page-aligned.
443 * This is a fixed-size type for 32/64 compatibility.
455 * This is a fixed-size type for 32/64 compatibility.
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/linux-3.3/Documentation/
Dlockdep-design.txt7 Lock-class
8 ----------
18 The validator tracks the 'state' of lock-classes, and it tracks
19 dependencies between different lock-classes. The validator maintains a
22 Unlike an lock instantiation, the lock-class itself never goes away: when
23 a lock-class is used for the first time after bootup it gets registered,
24 and all subsequent uses of that lock-class will be attached to this
25 lock-class.
28 -----
30 The validator tracks lock-class usage history into 4n + 1 separate state bits:
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/linux-3.3/drivers/video/
Dudlfb.c2 * udlfb.c -- Framebuffer driver for DisplayLink USB controller
13 * usb-skeleton by GregKH.
15 * Device-specific portions based on information from Displaylink, with work
51 * There are many DisplayLink-based graphics products, all with unique PIDs.
52 * So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
109 * ----- -----------------------------
195 while (actual_count--) { in dlfb_lfsr16()
224 xds = var->left_margin + var->hsync_len; in dlfb_set_vid_cmds()
227 xde = xds + var->xres; in dlfb_set_vid_cmds()
231 yds = var->upper_margin + var->vsync_len; in dlfb_set_vid_cmds()
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Dsmscufx.c2 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller
16 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev
20 * usb-skeleton by GregKH.
55 * DisplayLink X server as yet - need both to be modified in tandem
61 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
63 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
97 struct device *gdev; /* &udev->dev */
105 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
152 return -ENOMEM; in ufx_reg_read()
154 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), in ufx_reg_read()
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/linux-3.3/drivers/input/mouse/
Dalps.c5 * Copyright (c) 2003-2005 Peter Osterlund <petero2@telia.com>
78 #define ALPS_PASS 0x04 /* device has a pass-through port */
84 #define ALPS_PS2_INTERLEAVED 0x80 /* 3-byte PS/2 packet interleaved with
85 6-byte ALPS packet */
89 { { 0x33, 0x02, 0x0a }, 0x00, ALPS_PROTO_V1, 0x88, 0xf8, 0 }, /* UMAX-530T */
96 …3, 0x02, 0x3c }, 0x00, ALPS_PROTO_V2, 0x8f, 0x8f, ALPS_WHEEL }, /* Toshiba Satellite S2400-103 */
100 …{ { 0x73, 0x00, 0x0a }, 0x00, ALPS_PROTO_V2, 0xf8, 0xf8, ALPS_DUALPOINT }, /* ThinkPad R61 8918-5…
111 ALPS_PASS | ALPS_DUALPOINT | ALPS_PS2_INTERLEAVED }, /* Toshiba Tecra A11-11L */
118 * XXX - this entry is suspicious. First byte has zero lower nibble,
128 return (data & model->mask0) == model->byte0; in alps_is_valid_first_byte()
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/linux-3.3/drivers/infiniband/hw/qib/
Dqib_diag.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
38 * of the QLogic_IB chip may render the chip or board unusable until the
82 client_pool = dc->next; in get_client()
88 dc->next = NULL; in get_client()
89 dc->dd = dd; in get_client()
90 dc->pid = current->pid; in get_client()
91 dc->state = OPENED; in get_client()
101 struct qib_devdata *dd = dc->dd; in return_client()
105 if (dc == dd->diag_client) { in return_client()
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/linux-3.3/include/linux/
Dlibata.h2 * Copyright 2003-2005 Red Hat, Inc. All rights reserved.
3 * Copyright 2003-2005 Jeff Garzik
32 #include <linux/dma-mapping.h>
43 * Define if arch has non-standard setup. This is a _PCI_ standard
47 #include <asm/libata-portmap.h>
49 #include <asm-generic/libata-portmap.h>
53 * compile-time options: to be removed as soon as all the drivers are
75 #define BPRINTK(fmt, args...) if (ap->flags & ATA_FLAG_DEBUGMSG) printk(KERN_ERR "%s: " fmt, __func…
101 #define ata_msg_drv(p) ((p)->msg_enable & ATA_MSG_DRV)
102 #define ata_msg_info(p) ((p)->msg_enable & ATA_MSG_INFO)
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/linux-3.3/drivers/gpu/drm/radeon/
Dr600_cp.c2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
70 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
78 /* MAX values used for gfx init */
105 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
107 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
109 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
123 return -EBUSY; in r600_do_wait_for_fifo()
130 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
132 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
138 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
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Drv770.c48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip()
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
57 if (radeon_crtc->crtc_id) { in rv770_page_flip()
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
70 for (i = 0; i < rdev->usec_timeout; i++) { in rv770_page_flip()
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
77 /* Unlock the lock, so double-buffering can take place inside vblank */ in rv770_page_flip()
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
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/linux-3.3/fs/reiserfs/
Dfix_node.c66 "vs-8005: for INSERT mode and item number of inserted item"); in old_item_num()
68 return new_num - 1; in old_item_num()
72 "vs-8010: old_item_num: mode must be M_DELETE (mode = \'%c\'", in old_item_num()
81 struct virtual_node *vn = tb->tb_vn; in create_virtual_node()
83 struct buffer_head *Sh; /* this comes from tb->S[h] */ in create_virtual_node()
85 Sh = PATH_H_PBUFFER(tb->tb_path, h); in create_virtual_node()
88 vn->vn_size = in create_virtual_node()
89 MAX_CHILD_SIZE(Sh) - B_FREE_SPACE(Sh) + tb->insert_size[h]; in create_virtual_node()
93 vn->vn_nr_item = (vn->vn_size - DC_SIZE) / (DC_SIZE + KEY_SIZE); in create_virtual_node()
98 vn->vn_nr_item = in create_virtual_node()
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/linux-3.3/drivers/video/savage/
Dsavagefb_driver.c2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
16 * - hardware accelerated clear and move
19 * - wait for vertical retrace before writing to cr67
21 * - use synchronization registers cr23 and cr26
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
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