Lines Matching +full:render +full:- +full:max
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip()
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
57 if (radeon_crtc->crtc_id) { in rv770_page_flip()
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
70 for (i = 0; i < rdev->usec_timeout; i++) { in rv770_page_flip()
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
77 /* Unlock the lock, so double-buffering can take place inside vblank */ in rv770_page_flip()
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
82 …return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDIN… in rv770_page_flip()
93 actual_temp = -256; in rv770_get_temp()
107 int req_ps_idx = rdev->pm.requested_power_state_index; in rv770_pm_misc()
108 int req_cm_idx = rdev->pm.requested_clock_mode_index; in rv770_pm_misc()
109 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in rv770_pm_misc()
110 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; in rv770_pm_misc()
112 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { in rv770_pm_misc()
114 if (voltage->voltage == 0xff01) in rv770_pm_misc()
116 if (voltage->voltage != rdev->pm.current_vddc) { in rv770_pm_misc()
117 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in rv770_pm_misc()
118 rdev->pm.current_vddc = voltage->voltage; in rv770_pm_misc()
119 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); in rv770_pm_misc()
132 if (rdev->gart.robj == NULL) { in rv770_pcie_gart_enable()
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rv770_pcie_gart_enable()
134 return -EINVAL; in rv770_pcie_gart_enable()
158 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in rv770_pcie_gart_enable()
159 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in rv770_pcie_gart_enable()
160 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
164 (u32)(rdev->dummy_page.addr >> 12)); in rv770_pcie_gart_enable()
170 (unsigned)(rdev->mc.gtt_size >> 20), in rv770_pcie_gart_enable()
171 (unsigned long long)rdev->gart.table_addr); in rv770_pcie_gart_enable()
172 rdev->gart.ready = true; in rv770_pcie_gart_enable()
258 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
263 if (rdev->flags & RADEON_IS_AGP) { in rv770_mc_program()
264 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
267 rdev->mc.vram_start >> 12); in rv770_mc_program()
269 rdev->mc.gtt_end >> 12); in rv770_mc_program()
273 rdev->mc.gtt_start >> 12); in rv770_mc_program()
275 rdev->mc.vram_end >> 12); in rv770_mc_program()
279 rdev->mc.vram_start >> 12); in rv770_mc_program()
281 rdev->mc.vram_end >> 12); in rv770_mc_program()
283 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in rv770_mc_program()
284 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in rv770_mc_program()
285 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in rv770_mc_program()
287 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in rv770_mc_program()
290 if (rdev->flags & RADEON_IS_AGP) { in rv770_mc_program()
291 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in rv770_mc_program()
292 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in rv770_mc_program()
293 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in rv770_mc_program()
300 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
314 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r700_cp_stop()
324 if (!rdev->me_fw || !rdev->pfp_fw) in rv770_cp_load_microcode()
325 return -EINVAL; in rv770_cp_load_microcode()
340 fw_data = (const __be32 *)rdev->pfp_fw->data; in rv770_cp_load_microcode()
346 fw_data = (const __be32 *)rdev->me_fw->data; in rv770_cp_load_microcode()
360 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r700_cp_fini()
408 switch (rdev->family) { in r700_get_tile_pipe_to_backend_map()
563 switch (rdev->family) { in rv770_gpu_init()
565 rdev->config.rv770.max_pipes = 4; in rv770_gpu_init()
566 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()
567 rdev->config.rv770.max_simds = 10; in rv770_gpu_init()
568 rdev->config.rv770.max_backends = 4; in rv770_gpu_init()
569 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
570 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
571 rdev->config.rv770.max_stack_entries = 512; in rv770_gpu_init()
572 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
573 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
574 rdev->config.rv770.sx_max_export_size = 128; in rv770_gpu_init()
575 rdev->config.rv770.sx_max_export_pos_size = 16; in rv770_gpu_init()
576 rdev->config.rv770.sx_max_export_smx_size = 112; in rv770_gpu_init()
577 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
579 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
580 rdev->config.rv770.sc_prim_fifo_size = 0xF9; in rv770_gpu_init()
581 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
582 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
585 rdev->config.rv770.max_pipes = 2; in rv770_gpu_init()
586 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()
587 rdev->config.rv770.max_simds = 8; in rv770_gpu_init()
588 rdev->config.rv770.max_backends = 2; in rv770_gpu_init()
589 rdev->config.rv770.max_gprs = 128; in rv770_gpu_init()
590 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
591 rdev->config.rv770.max_stack_entries = 256; in rv770_gpu_init()
592 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
593 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
594 rdev->config.rv770.sx_max_export_size = 256; in rv770_gpu_init()
595 rdev->config.rv770.sx_max_export_pos_size = 32; in rv770_gpu_init()
596 rdev->config.rv770.sx_max_export_smx_size = 224; in rv770_gpu_init()
597 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
599 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
600 rdev->config.rv770.sc_prim_fifo_size = 0xf9; in rv770_gpu_init()
601 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
602 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
603 if (rdev->config.rv770.sx_max_export_pos_size > 16) { in rv770_gpu_init()
604 rdev->config.rv770.sx_max_export_pos_size -= 16; in rv770_gpu_init()
605 rdev->config.rv770.sx_max_export_smx_size += 16; in rv770_gpu_init()
609 rdev->config.rv770.max_pipes = 2; in rv770_gpu_init()
610 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()
611 rdev->config.rv770.max_simds = 2; in rv770_gpu_init()
612 rdev->config.rv770.max_backends = 1; in rv770_gpu_init()
613 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
614 rdev->config.rv770.max_threads = 192; in rv770_gpu_init()
615 rdev->config.rv770.max_stack_entries = 256; in rv770_gpu_init()
616 rdev->config.rv770.max_hw_contexts = 4; in rv770_gpu_init()
617 rdev->config.rv770.max_gs_threads = 8 * 2; in rv770_gpu_init()
618 rdev->config.rv770.sx_max_export_size = 128; in rv770_gpu_init()
619 rdev->config.rv770.sx_max_export_pos_size = 16; in rv770_gpu_init()
620 rdev->config.rv770.sx_max_export_smx_size = 112; in rv770_gpu_init()
621 rdev->config.rv770.sq_num_cf_insts = 1; in rv770_gpu_init()
623 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
624 rdev->config.rv770.sc_prim_fifo_size = 0x40; in rv770_gpu_init()
625 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
626 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
629 rdev->config.rv770.max_pipes = 4; in rv770_gpu_init()
630 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()
631 rdev->config.rv770.max_simds = 8; in rv770_gpu_init()
632 rdev->config.rv770.max_backends = 4; in rv770_gpu_init()
633 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
634 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
635 rdev->config.rv770.max_stack_entries = 512; in rv770_gpu_init()
636 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
637 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
638 rdev->config.rv770.sx_max_export_size = 256; in rv770_gpu_init()
639 rdev->config.rv770.sx_max_export_pos_size = 32; in rv770_gpu_init()
640 rdev->config.rv770.sx_max_export_smx_size = 224; in rv770_gpu_init()
641 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
643 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
644 rdev->config.rv770.sc_prim_fifo_size = 0x100; in rv770_gpu_init()
645 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
646 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
648 if (rdev->config.rv770.sx_max_export_pos_size > 16) { in rv770_gpu_init()
649 rdev->config.rv770.sx_max_export_pos_size -= 16; in rv770_gpu_init()
650 rdev->config.rv770.sx_max_export_smx_size += 16; in rv770_gpu_init()
673 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()
688 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
690 if (rdev->family == CHIP_RV770) in rv770_gpu_init()
694 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); in rv770_gpu_init()
697 rdev->config.rv770.tiling_group_size = 512; in rv770_gpu_init()
699 rdev->config.rv770.tiling_group_size = 256; in rv770_gpu_init()
714 …BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MA… in rv770_gpu_init()
718 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); in rv770_gpu_init()
720 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); in rv770_gpu_init()
722 if (rdev->family == CHIP_RV740) in rv770_gpu_init()
726 rdev->config.rv770.max_tile_pipes, in rv770_gpu_init()
727 (R7XX_MAX_BACKENDS - in rv770_gpu_init()
732 rdev->config.rv770.tile_config = gb_tiling_config; in rv770_gpu_init()
733 rdev->config.rv770.backend_map = backend_map; in rv770_gpu_init()
751 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); in rv770_gpu_init()
753 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); in rv770_gpu_init()
770 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); in rv770_gpu_init()
773 if (rdev->family != CHIP_RV740) in rv770_gpu_init()
781 switch (rdev->family) { in rv770_gpu_init()
794 if (rdev->family != CHIP_RV770) { in rv770_gpu_init()
800 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1)… in rv770_gpu_init()
801 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | in rv770_gpu_init()
802 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); in rv770_gpu_init()
804 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | in rv770_gpu_init()
805 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | in rv770_gpu_init()
806 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); in rv770_gpu_init()
818 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | in rv770_gpu_init()
821 switch (rdev->family) { in rv770_gpu_init()
849 if (rdev->family == CHIP_RV710) in rv770_gpu_init()
855 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
856 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
857 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); in rv770_gpu_init()
859 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | in rv770_gpu_init()
860 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); in rv770_gpu_init()
862 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | in rv770_gpu_init()
863 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | in rv770_gpu_init()
864 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); in rv770_gpu_init()
865 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) in rv770_gpu_init()
866 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); in rv770_gpu_init()
868 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); in rv770_gpu_init()
871 …WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
872 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); in rv770_gpu_init()
874 …WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
875 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); in rv770_gpu_init()
877 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
878 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
879 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
880 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); in rv770_gpu_init()
894 if (rdev->family == CHIP_RV710) in rv770_gpu_init()
901 switch (rdev->family) { in rv770_gpu_init()
914 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; in rv770_gpu_init()
916 /* Max value for this is 256 */ in rv770_gpu_init()
938 /* clear render buffer base addresses */ in rv770_gpu_init()
964 if (mc->mc_vram_size > 0xE0000000) { in r700_vram_gtt_location()
966 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
967 mc->real_vram_size = 0xE0000000; in r700_vram_gtt_location()
968 mc->mc_vram_size = 0xE0000000; in r700_vram_gtt_location()
970 if (rdev->flags & RADEON_IS_AGP) { in r700_vram_gtt_location()
971 size_bf = mc->gtt_start; in r700_vram_gtt_location()
972 size_af = 0xFFFFFFFF - mc->gtt_end + 1; in r700_vram_gtt_location()
974 if (mc->mc_vram_size > size_bf) { in r700_vram_gtt_location()
975 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
976 mc->real_vram_size = size_bf; in r700_vram_gtt_location()
977 mc->mc_vram_size = size_bf; in r700_vram_gtt_location()
979 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r700_vram_gtt_location()
981 if (mc->mc_vram_size > size_af) { in r700_vram_gtt_location()
982 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
983 mc->real_vram_size = size_af; in r700_vram_gtt_location()
984 mc->mc_vram_size = size_af; in r700_vram_gtt_location()
986 mc->vram_start = mc->gtt_end; in r700_vram_gtt_location()
988 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r700_vram_gtt_location()
989 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r700_vram_gtt_location()
990 mc->mc_vram_size >> 20, mc->vram_start, in r700_vram_gtt_location()
991 mc->vram_end, mc->real_vram_size >> 20); in r700_vram_gtt_location()
993 radeon_vram_location(rdev, &rdev->mc, 0); in r700_vram_gtt_location()
994 rdev->mc.gtt_base_align = 0; in r700_vram_gtt_location()
1005 rdev->mc.vram_is_ddr = true; in rv770_mc_init()
1030 rdev->mc.vram_width = numchan * chansize; in rv770_mc_init()
1032 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rv770_mc_init()
1033 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rv770_mc_init()
1035 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in rv770_mc_init()
1036 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in rv770_mc_init()
1037 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rv770_mc_init()
1038 r700_vram_gtt_location(rdev, &rdev->mc); in rv770_mc_init()
1046 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in rv770_startup()
1052 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in rv770_startup()
1065 if (rdev->flags & RADEON_IS_AGP) { in rv770_startup()
1077 rdev->asic->copy = NULL; in rv770_startup()
1078 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); in rv770_startup()
1088 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rv770_startup()
1101 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in rv770_startup()
1119 dev_err(rdev->dev, "IB test failed (%d).\n", r); in rv770_startup()
1120 rdev->accel_working = false; in rv770_startup()
1136 atom_asic_init(rdev->mode_info.atom_context); in rv770_resume()
1138 rdev->accel_working = true; in rv770_resume()
1142 rdev->accel_working = false; in rv770_resume()
1148 dev_err(rdev->dev, "radeon: audio init failed\n"); in rv770_resume()
1163 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in rv770_suspend()
1188 return -EINVAL; in rv770_init()
1191 if (!rdev->is_atom_bios) { in rv770_init()
1192 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in rv770_init()
1193 return -EINVAL; in rv770_init()
1200 if (!rdev->bios) { in rv770_init()
1201 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in rv770_init()
1202 return -EINVAL; in rv770_init()
1205 atom_asic_init(rdev->mode_info.atom_context); in rv770_init()
1212 radeon_get_clock_info(rdev->ddev); in rv770_init()
1218 if (rdev->flags & RADEON_IS_AGP) { in rv770_init()
1235 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in rv770_init()
1236 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in rv770_init()
1238 rdev->ih.ring_obj = NULL; in rv770_init()
1246 rdev->accel_working = true; in rv770_init()
1248 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rv770_init()
1249 rdev->accel_working = false; in rv770_init()
1254 dev_err(rdev->dev, "disabling GPU acceleration\n"); in rv770_init()
1261 rdev->accel_working = false; in rv770_init()
1266 dev_err(rdev->dev, "radeon: audio init failed\n"); in rv770_init()
1289 kfree(rdev->bios); in rv770_fini()
1290 rdev->bios = NULL; in rv770_fini()
1301 if (rdev->flags & RADEON_IS_IGP) in rv770_pcie_gen2_enable()
1304 if (!(rdev->flags & RADEON_IS_PCIE)) in rv770_pcie_gen2_enable()