1 /*
2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 * Sven Neumann <neo@directfb.org>
6 *
7 *
8 * Card specific code is based on XFree86's savage driver.
9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 * 0.4.0 (neo)
16 * - hardware accelerated clear and move
17 *
18 * 0.3.2 (dok)
19 * - wait for vertical retrace before writing to cr67
20 * at the beginning of savagefb_set_par
21 * - use synchronization registers cr23 and cr26
22 *
23 * 0.3.1 (dok)
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
26 *
27 * 0.3.0 (dok)
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
31 *
32 * 0.2.0 (dok)
33 * - first working version
34 *
35 *
36 * TODO
37 * - clock validations in decode_var
38 *
39 * BUGS
40 * - white margin on bootup
41 *
42 */
43
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/errno.h>
47 #include <linux/string.h>
48 #include <linux/mm.h>
49 #include <linux/slab.h>
50 #include <linux/delay.h>
51 #include <linux/fb.h>
52 #include <linux/pci.h>
53 #include <linux/init.h>
54 #include <linux/console.h>
55
56 #include <asm/io.h>
57 #include <asm/irq.h>
58 #include <asm/pgtable.h>
59 #include <asm/system.h>
60
61 #ifdef CONFIG_MTRR
62 #include <asm/mtrr.h>
63 #endif
64
65 #include "savagefb.h"
66
67
68 #define SAVAGEFB_VERSION "0.4.0_2.6"
69
70 /* --------------------------------------------------------------------- */
71
72
73 static char *mode_option __devinitdata = NULL;
74
75 #ifdef MODULE
76
77 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
78 MODULE_LICENSE("GPL");
79 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
80
81 #endif
82
83
84 /* --------------------------------------------------------------------- */
85
vgaHWSeqReset(struct savagefb_par * par,int start)86 static void vgaHWSeqReset(struct savagefb_par *par, int start)
87 {
88 if (start)
89 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
90 else
91 VGAwSEQ(0x00, 0x03, par); /* End Reset */
92 }
93
vgaHWProtect(struct savagefb_par * par,int on)94 static void vgaHWProtect(struct savagefb_par *par, int on)
95 {
96 unsigned char tmp;
97
98 if (on) {
99 /*
100 * Turn off screen and disable sequencer.
101 */
102 tmp = VGArSEQ(0x01, par);
103
104 vgaHWSeqReset(par, 1); /* start synchronous reset */
105 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
106
107 VGAenablePalette(par);
108 } else {
109 /*
110 * Reenable sequencer, then turn on screen.
111 */
112
113 tmp = VGArSEQ(0x01, par);
114
115 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
116 vgaHWSeqReset(par, 0); /* clear synchronous reset */
117
118 VGAdisablePalette(par);
119 }
120 }
121
vgaHWRestore(struct savagefb_par * par,struct savage_reg * reg)122 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
123 {
124 int i;
125
126 VGAwMISC(reg->MiscOutReg, par);
127
128 for (i = 1; i < 5; i++)
129 VGAwSEQ(i, reg->Sequencer[i], par);
130
131 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
132 CRTC[17] */
133 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
134
135 for (i = 0; i < 25; i++)
136 VGAwCR(i, reg->CRTC[i], par);
137
138 for (i = 0; i < 9; i++)
139 VGAwGR(i, reg->Graphics[i], par);
140
141 VGAenablePalette(par);
142
143 for (i = 0; i < 21; i++)
144 VGAwATTR(i, reg->Attribute[i], par);
145
146 VGAdisablePalette(par);
147 }
148
vgaHWInit(struct fb_var_screeninfo * var,struct savagefb_par * par,struct xtimings * timings,struct savage_reg * reg)149 static void vgaHWInit(struct fb_var_screeninfo *var,
150 struct savagefb_par *par,
151 struct xtimings *timings,
152 struct savage_reg *reg)
153 {
154 reg->MiscOutReg = 0x23;
155
156 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
157 reg->MiscOutReg |= 0x40;
158
159 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
160 reg->MiscOutReg |= 0x80;
161
162 /*
163 * Time Sequencer
164 */
165 reg->Sequencer[0x00] = 0x00;
166 reg->Sequencer[0x01] = 0x01;
167 reg->Sequencer[0x02] = 0x0F;
168 reg->Sequencer[0x03] = 0x00; /* Font select */
169 reg->Sequencer[0x04] = 0x0E; /* Misc */
170
171 /*
172 * CRTC Controller
173 */
174 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
175 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
176 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
177 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
178 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
179 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
180 (((timings->HSyncEnd >> 3)) & 0x1f);
181 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
182 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
183 (((timings->VDisplay - 1) & 0x100) >> 7) |
184 ((timings->VSyncStart & 0x100) >> 6) |
185 (((timings->VSyncStart - 1) & 0x100) >> 5) |
186 0x10 |
187 (((timings->VTotal - 2) & 0x200) >> 4) |
188 (((timings->VDisplay - 1) & 0x200) >> 3) |
189 ((timings->VSyncStart & 0x200) >> 2);
190 reg->CRTC[0x08] = 0x00;
191 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
192
193 if (timings->dblscan)
194 reg->CRTC[0x09] |= 0x80;
195
196 reg->CRTC[0x0a] = 0x00;
197 reg->CRTC[0x0b] = 0x00;
198 reg->CRTC[0x0c] = 0x00;
199 reg->CRTC[0x0d] = 0x00;
200 reg->CRTC[0x0e] = 0x00;
201 reg->CRTC[0x0f] = 0x00;
202 reg->CRTC[0x10] = timings->VSyncStart & 0xff;
203 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
204 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
205 reg->CRTC[0x13] = var->xres_virtual >> 4;
206 reg->CRTC[0x14] = 0x00;
207 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
208 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
209 reg->CRTC[0x17] = 0xc3;
210 reg->CRTC[0x18] = 0xff;
211
212 /*
213 * are these unnecessary?
214 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
215 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
216 */
217
218 /*
219 * Graphics Display Controller
220 */
221 reg->Graphics[0x00] = 0x00;
222 reg->Graphics[0x01] = 0x00;
223 reg->Graphics[0x02] = 0x00;
224 reg->Graphics[0x03] = 0x00;
225 reg->Graphics[0x04] = 0x00;
226 reg->Graphics[0x05] = 0x40;
227 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
228 reg->Graphics[0x07] = 0x0F;
229 reg->Graphics[0x08] = 0xFF;
230
231
232 reg->Attribute[0x00] = 0x00; /* standard colormap translation */
233 reg->Attribute[0x01] = 0x01;
234 reg->Attribute[0x02] = 0x02;
235 reg->Attribute[0x03] = 0x03;
236 reg->Attribute[0x04] = 0x04;
237 reg->Attribute[0x05] = 0x05;
238 reg->Attribute[0x06] = 0x06;
239 reg->Attribute[0x07] = 0x07;
240 reg->Attribute[0x08] = 0x08;
241 reg->Attribute[0x09] = 0x09;
242 reg->Attribute[0x0a] = 0x0A;
243 reg->Attribute[0x0b] = 0x0B;
244 reg->Attribute[0x0c] = 0x0C;
245 reg->Attribute[0x0d] = 0x0D;
246 reg->Attribute[0x0e] = 0x0E;
247 reg->Attribute[0x0f] = 0x0F;
248 reg->Attribute[0x10] = 0x41;
249 reg->Attribute[0x11] = 0xFF;
250 reg->Attribute[0x12] = 0x0F;
251 reg->Attribute[0x13] = 0x00;
252 reg->Attribute[0x14] = 0x00;
253 }
254
255 /* -------------------- Hardware specific routines ------------------------- */
256
257 /*
258 * Hardware Acceleration for SavageFB
259 */
260
261 /* Wait for fifo space */
262 static void
savage3D_waitfifo(struct savagefb_par * par,int space)263 savage3D_waitfifo(struct savagefb_par *par, int space)
264 {
265 int slots = MAXFIFO - space;
266
267 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
268 }
269
270 static void
savage4_waitfifo(struct savagefb_par * par,int space)271 savage4_waitfifo(struct savagefb_par *par, int space)
272 {
273 int slots = MAXFIFO - space;
274
275 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
276 }
277
278 static void
savage2000_waitfifo(struct savagefb_par * par,int space)279 savage2000_waitfifo(struct savagefb_par *par, int space)
280 {
281 int slots = MAXFIFO - space;
282
283 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
284 }
285
286 /* Wait for idle accelerator */
287 static void
savage3D_waitidle(struct savagefb_par * par)288 savage3D_waitidle(struct savagefb_par *par)
289 {
290 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
291 }
292
293 static void
savage4_waitidle(struct savagefb_par * par)294 savage4_waitidle(struct savagefb_par *par)
295 {
296 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
297 }
298
299 static void
savage2000_waitidle(struct savagefb_par * par)300 savage2000_waitidle(struct savagefb_par *par)
301 {
302 while ((savage_in32(0x48C60, par) & 0x009fffff));
303 }
304
305 #ifdef CONFIG_FB_SAVAGE_ACCEL
306 static void
SavageSetup2DEngine(struct savagefb_par * par)307 SavageSetup2DEngine(struct savagefb_par *par)
308 {
309 unsigned long GlobalBitmapDescriptor;
310
311 GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
312 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
313 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
314
315 switch(par->chip) {
316 case S3_SAVAGE3D:
317 case S3_SAVAGE_MX:
318 /* Disable BCI */
319 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
320 /* Setup BCI command overflow buffer */
321 savage_out32(0x48C14,
322 (par->cob_offset >> 11) | (par->cob_index << 29),
323 par);
324 /* Program shadow status update. */
325 savage_out32(0x48C10, 0x78207220, par);
326 savage_out32(0x48C0C, 0, par);
327 /* Enable BCI and command overflow buffer */
328 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
329 break;
330 case S3_SAVAGE4:
331 case S3_TWISTER:
332 case S3_PROSAVAGE:
333 case S3_PROSAVAGEDDR:
334 case S3_SUPERSAVAGE:
335 /* Disable BCI */
336 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
337 /* Program shadow status update */
338 savage_out32(0x48C10, 0x00700040, par);
339 savage_out32(0x48C0C, 0, par);
340 /* Enable BCI without the COB */
341 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
342 break;
343 case S3_SAVAGE2000:
344 /* Disable BCI */
345 savage_out32(0x48C18, 0, par);
346 /* Setup BCI command overflow buffer */
347 savage_out32(0x48C18,
348 (par->cob_offset >> 7) | (par->cob_index),
349 par);
350 /* Disable shadow status update */
351 savage_out32(0x48A30, 0, par);
352 /* Enable BCI and command overflow buffer */
353 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
354 par);
355 break;
356 default:
357 break;
358 }
359 /* Turn on 16-bit register access. */
360 vga_out8(0x3d4, 0x31, par);
361 vga_out8(0x3d5, 0x0c, par);
362
363 /* Set stride to use GBD. */
364 vga_out8(0x3d4, 0x50, par);
365 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
366
367 /* Enable 2D engine. */
368 vga_out8(0x3d4, 0x40, par);
369 vga_out8(0x3d5, 0x01, par);
370
371 savage_out32(MONO_PAT_0, ~0, par);
372 savage_out32(MONO_PAT_1, ~0, par);
373
374 /* Setup plane masks */
375 savage_out32(0x8128, ~0, par); /* enable all write planes */
376 savage_out32(0x812C, ~0, par); /* enable all read planes */
377 savage_out16(0x8134, 0x27, par);
378 savage_out16(0x8136, 0x07, par);
379
380 /* Now set the GBD */
381 par->bci_ptr = 0;
382 par->SavageWaitFifo(par, 4);
383
384 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
385 BCI_SEND(0);
386 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
387 BCI_SEND(GlobalBitmapDescriptor);
388
389 /*
390 * I don't know why, sending this twice fixes the initial black screen,
391 * prevents X from crashing at least in Toshiba laptops with SavageIX.
392 * --Tony
393 */
394 par->bci_ptr = 0;
395 par->SavageWaitFifo(par, 4);
396
397 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
398 BCI_SEND(0);
399 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
400 BCI_SEND(GlobalBitmapDescriptor);
401 }
402
savagefb_set_clip(struct fb_info * info)403 static void savagefb_set_clip(struct fb_info *info)
404 {
405 struct savagefb_par *par = info->par;
406 int cmd;
407
408 cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
409 par->bci_ptr = 0;
410 par->SavageWaitFifo(par,3);
411 BCI_SEND(cmd);
412 BCI_SEND(BCI_CLIP_TL(0, 0));
413 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
414 }
415 #else
SavageSetup2DEngine(struct savagefb_par * par)416 static void SavageSetup2DEngine(struct savagefb_par *par) {}
417
418 #endif
419
SavageCalcClock(long freq,int min_m,int min_n1,int max_n1,int min_n2,int max_n2,long freq_min,long freq_max,unsigned int * mdiv,unsigned int * ndiv,unsigned int * r)420 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
421 int min_n2, int max_n2, long freq_min,
422 long freq_max, unsigned int *mdiv,
423 unsigned int *ndiv, unsigned int *r)
424 {
425 long diff, best_diff;
426 unsigned int m;
427 unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
428
429 if (freq < freq_min / (1 << max_n2)) {
430 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
431 freq = freq_min / (1 << max_n2);
432 }
433 if (freq > freq_max / (1 << min_n2)) {
434 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
435 freq = freq_max / (1 << min_n2);
436 }
437
438 /* work out suitable timings */
439 best_diff = freq;
440
441 for (n2=min_n2; n2<=max_n2; n2++) {
442 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
443 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
444 BASE_FREQ;
445 if (m < min_m+2 || m > 127+2)
446 continue;
447 if ((m * BASE_FREQ >= freq_min * n1) &&
448 (m * BASE_FREQ <= freq_max * n1)) {
449 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
450 if (diff < 0)
451 diff = -diff;
452 if (diff < best_diff) {
453 best_diff = diff;
454 best_m = m;
455 best_n1 = n1;
456 best_n2 = n2;
457 }
458 }
459 }
460 }
461
462 *ndiv = best_n1 - 2;
463 *r = best_n2;
464 *mdiv = best_m - 2;
465 }
466
common_calc_clock(long freq,int min_m,int min_n1,int max_n1,int min_n2,int max_n2,long freq_min,long freq_max,unsigned char * mdiv,unsigned char * ndiv)467 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
468 int min_n2, int max_n2, long freq_min,
469 long freq_max, unsigned char *mdiv,
470 unsigned char *ndiv)
471 {
472 long diff, best_diff;
473 unsigned int m;
474 unsigned char n1, n2;
475 unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
476
477 best_diff = freq;
478
479 for (n2 = min_n2; n2 <= max_n2; n2++) {
480 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
481 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
482 BASE_FREQ;
483 if (m < min_m + 2 || m > 127+2)
484 continue;
485 if ((m * BASE_FREQ >= freq_min * n1) &&
486 (m * BASE_FREQ <= freq_max * n1)) {
487 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
488 if (diff < 0)
489 diff = -diff;
490 if (diff < best_diff) {
491 best_diff = diff;
492 best_m = m;
493 best_n1 = n1;
494 best_n2 = n2;
495 }
496 }
497 }
498 }
499
500 if (max_n1 == 63)
501 *ndiv = (best_n1 - 2) | (best_n2 << 6);
502 else
503 *ndiv = (best_n1 - 2) | (best_n2 << 5);
504
505 *mdiv = best_m - 2;
506
507 return 0;
508 }
509
510 #ifdef SAVAGEFB_DEBUG
511 /* This function is used to debug, it prints out the contents of s3 regs */
512
SavagePrintRegs(struct savagefb_par * par)513 static void SavagePrintRegs(struct savagefb_par *par)
514 {
515 unsigned char i;
516 int vgaCRIndex = 0x3d4;
517 int vgaCRReg = 0x3d5;
518
519 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
520 "xF");
521
522 for (i = 0; i < 0x70; i++) {
523 if (!(i % 16))
524 printk(KERN_DEBUG "\nSR%xx ", i >> 4);
525 vga_out8(0x3c4, i, par);
526 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
527 }
528
529 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
530 "xD xE xF");
531
532 for (i = 0; i < 0xB7; i++) {
533 if (!(i % 16))
534 printk(KERN_DEBUG "\nCR%xx ", i >> 4);
535 vga_out8(vgaCRIndex, i, par);
536 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
537 }
538
539 printk(KERN_DEBUG "\n\n");
540 }
541 #endif
542
543 /* --------------------------------------------------------------------- */
544
savage_get_default_par(struct savagefb_par * par,struct savage_reg * reg)545 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
546 {
547 unsigned char cr3a, cr53, cr66;
548
549 vga_out16(0x3d4, 0x4838, par);
550 vga_out16(0x3d4, 0xa039, par);
551 vga_out16(0x3c4, 0x0608, par);
552
553 vga_out8(0x3d4, 0x66, par);
554 cr66 = vga_in8(0x3d5, par);
555 vga_out8(0x3d5, cr66 | 0x80, par);
556 vga_out8(0x3d4, 0x3a, par);
557 cr3a = vga_in8(0x3d5, par);
558 vga_out8(0x3d5, cr3a | 0x80, par);
559 vga_out8(0x3d4, 0x53, par);
560 cr53 = vga_in8(0x3d5, par);
561 vga_out8(0x3d5, cr53 & 0x7f, par);
562
563 vga_out8(0x3d4, 0x66, par);
564 vga_out8(0x3d5, cr66, par);
565 vga_out8(0x3d4, 0x3a, par);
566 vga_out8(0x3d5, cr3a, par);
567
568 vga_out8(0x3d4, 0x66, par);
569 vga_out8(0x3d5, cr66, par);
570 vga_out8(0x3d4, 0x3a, par);
571 vga_out8(0x3d5, cr3a, par);
572
573 /* unlock extended seq regs */
574 vga_out8(0x3c4, 0x08, par);
575 reg->SR08 = vga_in8(0x3c5, par);
576 vga_out8(0x3c5, 0x06, par);
577
578 /* now save all the extended regs we need */
579 vga_out8(0x3d4, 0x31, par);
580 reg->CR31 = vga_in8(0x3d5, par);
581 vga_out8(0x3d4, 0x32, par);
582 reg->CR32 = vga_in8(0x3d5, par);
583 vga_out8(0x3d4, 0x34, par);
584 reg->CR34 = vga_in8(0x3d5, par);
585 vga_out8(0x3d4, 0x36, par);
586 reg->CR36 = vga_in8(0x3d5, par);
587 vga_out8(0x3d4, 0x3a, par);
588 reg->CR3A = vga_in8(0x3d5, par);
589 vga_out8(0x3d4, 0x40, par);
590 reg->CR40 = vga_in8(0x3d5, par);
591 vga_out8(0x3d4, 0x42, par);
592 reg->CR42 = vga_in8(0x3d5, par);
593 vga_out8(0x3d4, 0x45, par);
594 reg->CR45 = vga_in8(0x3d5, par);
595 vga_out8(0x3d4, 0x50, par);
596 reg->CR50 = vga_in8(0x3d5, par);
597 vga_out8(0x3d4, 0x51, par);
598 reg->CR51 = vga_in8(0x3d5, par);
599 vga_out8(0x3d4, 0x53, par);
600 reg->CR53 = vga_in8(0x3d5, par);
601 vga_out8(0x3d4, 0x58, par);
602 reg->CR58 = vga_in8(0x3d5, par);
603 vga_out8(0x3d4, 0x60, par);
604 reg->CR60 = vga_in8(0x3d5, par);
605 vga_out8(0x3d4, 0x66, par);
606 reg->CR66 = vga_in8(0x3d5, par);
607 vga_out8(0x3d4, 0x67, par);
608 reg->CR67 = vga_in8(0x3d5, par);
609 vga_out8(0x3d4, 0x68, par);
610 reg->CR68 = vga_in8(0x3d5, par);
611 vga_out8(0x3d4, 0x69, par);
612 reg->CR69 = vga_in8(0x3d5, par);
613 vga_out8(0x3d4, 0x6f, par);
614 reg->CR6F = vga_in8(0x3d5, par);
615
616 vga_out8(0x3d4, 0x33, par);
617 reg->CR33 = vga_in8(0x3d5, par);
618 vga_out8(0x3d4, 0x86, par);
619 reg->CR86 = vga_in8(0x3d5, par);
620 vga_out8(0x3d4, 0x88, par);
621 reg->CR88 = vga_in8(0x3d5, par);
622 vga_out8(0x3d4, 0x90, par);
623 reg->CR90 = vga_in8(0x3d5, par);
624 vga_out8(0x3d4, 0x91, par);
625 reg->CR91 = vga_in8(0x3d5, par);
626 vga_out8(0x3d4, 0xb0, par);
627 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
628
629 /* extended mode timing regs */
630 vga_out8(0x3d4, 0x3b, par);
631 reg->CR3B = vga_in8(0x3d5, par);
632 vga_out8(0x3d4, 0x3c, par);
633 reg->CR3C = vga_in8(0x3d5, par);
634 vga_out8(0x3d4, 0x43, par);
635 reg->CR43 = vga_in8(0x3d5, par);
636 vga_out8(0x3d4, 0x5d, par);
637 reg->CR5D = vga_in8(0x3d5, par);
638 vga_out8(0x3d4, 0x5e, par);
639 reg->CR5E = vga_in8(0x3d5, par);
640 vga_out8(0x3d4, 0x65, par);
641 reg->CR65 = vga_in8(0x3d5, par);
642
643 /* save seq extended regs for DCLK PLL programming */
644 vga_out8(0x3c4, 0x0e, par);
645 reg->SR0E = vga_in8(0x3c5, par);
646 vga_out8(0x3c4, 0x0f, par);
647 reg->SR0F = vga_in8(0x3c5, par);
648 vga_out8(0x3c4, 0x10, par);
649 reg->SR10 = vga_in8(0x3c5, par);
650 vga_out8(0x3c4, 0x11, par);
651 reg->SR11 = vga_in8(0x3c5, par);
652 vga_out8(0x3c4, 0x12, par);
653 reg->SR12 = vga_in8(0x3c5, par);
654 vga_out8(0x3c4, 0x13, par);
655 reg->SR13 = vga_in8(0x3c5, par);
656 vga_out8(0x3c4, 0x29, par);
657 reg->SR29 = vga_in8(0x3c5, par);
658
659 vga_out8(0x3c4, 0x15, par);
660 reg->SR15 = vga_in8(0x3c5, par);
661 vga_out8(0x3c4, 0x30, par);
662 reg->SR30 = vga_in8(0x3c5, par);
663 vga_out8(0x3c4, 0x18, par);
664 reg->SR18 = vga_in8(0x3c5, par);
665
666 /* Save flat panel expansion regsters. */
667 if (par->chip == S3_SAVAGE_MX) {
668 int i;
669
670 for (i = 0; i < 8; i++) {
671 vga_out8(0x3c4, 0x54+i, par);
672 reg->SR54[i] = vga_in8(0x3c5, par);
673 }
674 }
675
676 vga_out8(0x3d4, 0x66, par);
677 cr66 = vga_in8(0x3d5, par);
678 vga_out8(0x3d5, cr66 | 0x80, par);
679 vga_out8(0x3d4, 0x3a, par);
680 cr3a = vga_in8(0x3d5, par);
681 vga_out8(0x3d5, cr3a | 0x80, par);
682
683 /* now save MIU regs */
684 if (par->chip != S3_SAVAGE_MX) {
685 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
686 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
687 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
688 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
689 }
690
691 vga_out8(0x3d4, 0x3a, par);
692 vga_out8(0x3d5, cr3a, par);
693 vga_out8(0x3d4, 0x66, par);
694 vga_out8(0x3d5, cr66, par);
695 }
696
savage_set_default_par(struct savagefb_par * par,struct savage_reg * reg)697 static void savage_set_default_par(struct savagefb_par *par,
698 struct savage_reg *reg)
699 {
700 unsigned char cr3a, cr53, cr66;
701
702 vga_out16(0x3d4, 0x4838, par);
703 vga_out16(0x3d4, 0xa039, par);
704 vga_out16(0x3c4, 0x0608, par);
705
706 vga_out8(0x3d4, 0x66, par);
707 cr66 = vga_in8(0x3d5, par);
708 vga_out8(0x3d5, cr66 | 0x80, par);
709 vga_out8(0x3d4, 0x3a, par);
710 cr3a = vga_in8(0x3d5, par);
711 vga_out8(0x3d5, cr3a | 0x80, par);
712 vga_out8(0x3d4, 0x53, par);
713 cr53 = vga_in8(0x3d5, par);
714 vga_out8(0x3d5, cr53 & 0x7f, par);
715
716 vga_out8(0x3d4, 0x66, par);
717 vga_out8(0x3d5, cr66, par);
718 vga_out8(0x3d4, 0x3a, par);
719 vga_out8(0x3d5, cr3a, par);
720
721 vga_out8(0x3d4, 0x66, par);
722 vga_out8(0x3d5, cr66, par);
723 vga_out8(0x3d4, 0x3a, par);
724 vga_out8(0x3d5, cr3a, par);
725
726 /* unlock extended seq regs */
727 vga_out8(0x3c4, 0x08, par);
728 vga_out8(0x3c5, reg->SR08, par);
729 vga_out8(0x3c5, 0x06, par);
730
731 /* now restore all the extended regs we need */
732 vga_out8(0x3d4, 0x31, par);
733 vga_out8(0x3d5, reg->CR31, par);
734 vga_out8(0x3d4, 0x32, par);
735 vga_out8(0x3d5, reg->CR32, par);
736 vga_out8(0x3d4, 0x34, par);
737 vga_out8(0x3d5, reg->CR34, par);
738 vga_out8(0x3d4, 0x36, par);
739 vga_out8(0x3d5,reg->CR36, par);
740 vga_out8(0x3d4, 0x3a, par);
741 vga_out8(0x3d5, reg->CR3A, par);
742 vga_out8(0x3d4, 0x40, par);
743 vga_out8(0x3d5, reg->CR40, par);
744 vga_out8(0x3d4, 0x42, par);
745 vga_out8(0x3d5, reg->CR42, par);
746 vga_out8(0x3d4, 0x45, par);
747 vga_out8(0x3d5, reg->CR45, par);
748 vga_out8(0x3d4, 0x50, par);
749 vga_out8(0x3d5, reg->CR50, par);
750 vga_out8(0x3d4, 0x51, par);
751 vga_out8(0x3d5, reg->CR51, par);
752 vga_out8(0x3d4, 0x53, par);
753 vga_out8(0x3d5, reg->CR53, par);
754 vga_out8(0x3d4, 0x58, par);
755 vga_out8(0x3d5, reg->CR58, par);
756 vga_out8(0x3d4, 0x60, par);
757 vga_out8(0x3d5, reg->CR60, par);
758 vga_out8(0x3d4, 0x66, par);
759 vga_out8(0x3d5, reg->CR66, par);
760 vga_out8(0x3d4, 0x67, par);
761 vga_out8(0x3d5, reg->CR67, par);
762 vga_out8(0x3d4, 0x68, par);
763 vga_out8(0x3d5, reg->CR68, par);
764 vga_out8(0x3d4, 0x69, par);
765 vga_out8(0x3d5, reg->CR69, par);
766 vga_out8(0x3d4, 0x6f, par);
767 vga_out8(0x3d5, reg->CR6F, par);
768
769 vga_out8(0x3d4, 0x33, par);
770 vga_out8(0x3d5, reg->CR33, par);
771 vga_out8(0x3d4, 0x86, par);
772 vga_out8(0x3d5, reg->CR86, par);
773 vga_out8(0x3d4, 0x88, par);
774 vga_out8(0x3d5, reg->CR88, par);
775 vga_out8(0x3d4, 0x90, par);
776 vga_out8(0x3d5, reg->CR90, par);
777 vga_out8(0x3d4, 0x91, par);
778 vga_out8(0x3d5, reg->CR91, par);
779 vga_out8(0x3d4, 0xb0, par);
780 vga_out8(0x3d5, reg->CRB0, par);
781
782 /* extended mode timing regs */
783 vga_out8(0x3d4, 0x3b, par);
784 vga_out8(0x3d5, reg->CR3B, par);
785 vga_out8(0x3d4, 0x3c, par);
786 vga_out8(0x3d5, reg->CR3C, par);
787 vga_out8(0x3d4, 0x43, par);
788 vga_out8(0x3d5, reg->CR43, par);
789 vga_out8(0x3d4, 0x5d, par);
790 vga_out8(0x3d5, reg->CR5D, par);
791 vga_out8(0x3d4, 0x5e, par);
792 vga_out8(0x3d5, reg->CR5E, par);
793 vga_out8(0x3d4, 0x65, par);
794 vga_out8(0x3d5, reg->CR65, par);
795
796 /* save seq extended regs for DCLK PLL programming */
797 vga_out8(0x3c4, 0x0e, par);
798 vga_out8(0x3c5, reg->SR0E, par);
799 vga_out8(0x3c4, 0x0f, par);
800 vga_out8(0x3c5, reg->SR0F, par);
801 vga_out8(0x3c4, 0x10, par);
802 vga_out8(0x3c5, reg->SR10, par);
803 vga_out8(0x3c4, 0x11, par);
804 vga_out8(0x3c5, reg->SR11, par);
805 vga_out8(0x3c4, 0x12, par);
806 vga_out8(0x3c5, reg->SR12, par);
807 vga_out8(0x3c4, 0x13, par);
808 vga_out8(0x3c5, reg->SR13, par);
809 vga_out8(0x3c4, 0x29, par);
810 vga_out8(0x3c5, reg->SR29, par);
811
812 vga_out8(0x3c4, 0x15, par);
813 vga_out8(0x3c5, reg->SR15, par);
814 vga_out8(0x3c4, 0x30, par);
815 vga_out8(0x3c5, reg->SR30, par);
816 vga_out8(0x3c4, 0x18, par);
817 vga_out8(0x3c5, reg->SR18, par);
818
819 /* Save flat panel expansion regsters. */
820 if (par->chip == S3_SAVAGE_MX) {
821 int i;
822
823 for (i = 0; i < 8; i++) {
824 vga_out8(0x3c4, 0x54+i, par);
825 vga_out8(0x3c5, reg->SR54[i], par);
826 }
827 }
828
829 vga_out8(0x3d4, 0x66, par);
830 cr66 = vga_in8(0x3d5, par);
831 vga_out8(0x3d5, cr66 | 0x80, par);
832 vga_out8(0x3d4, 0x3a, par);
833 cr3a = vga_in8(0x3d5, par);
834 vga_out8(0x3d5, cr3a | 0x80, par);
835
836 /* now save MIU regs */
837 if (par->chip != S3_SAVAGE_MX) {
838 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
839 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
840 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
841 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
842 }
843
844 vga_out8(0x3d4, 0x3a, par);
845 vga_out8(0x3d5, cr3a, par);
846 vga_out8(0x3d4, 0x66, par);
847 vga_out8(0x3d5, cr66, par);
848 }
849
savage_update_var(struct fb_var_screeninfo * var,const struct fb_videomode * modedb)850 static void savage_update_var(struct fb_var_screeninfo *var,
851 const struct fb_videomode *modedb)
852 {
853 var->xres = var->xres_virtual = modedb->xres;
854 var->yres = modedb->yres;
855 if (var->yres_virtual < var->yres)
856 var->yres_virtual = var->yres;
857 var->xoffset = var->yoffset = 0;
858 var->pixclock = modedb->pixclock;
859 var->left_margin = modedb->left_margin;
860 var->right_margin = modedb->right_margin;
861 var->upper_margin = modedb->upper_margin;
862 var->lower_margin = modedb->lower_margin;
863 var->hsync_len = modedb->hsync_len;
864 var->vsync_len = modedb->vsync_len;
865 var->sync = modedb->sync;
866 var->vmode = modedb->vmode;
867 }
868
savagefb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)869 static int savagefb_check_var(struct fb_var_screeninfo *var,
870 struct fb_info *info)
871 {
872 struct savagefb_par *par = info->par;
873 int memlen, vramlen, mode_valid = 0;
874
875 DBG("savagefb_check_var");
876
877 var->transp.offset = 0;
878 var->transp.length = 0;
879 switch (var->bits_per_pixel) {
880 case 8:
881 var->red.offset = var->green.offset =
882 var->blue.offset = 0;
883 var->red.length = var->green.length =
884 var->blue.length = var->bits_per_pixel;
885 break;
886 case 16:
887 var->red.offset = 11;
888 var->red.length = 5;
889 var->green.offset = 5;
890 var->green.length = 6;
891 var->blue.offset = 0;
892 var->blue.length = 5;
893 break;
894 case 32:
895 var->transp.offset = 24;
896 var->transp.length = 8;
897 var->red.offset = 16;
898 var->red.length = 8;
899 var->green.offset = 8;
900 var->green.length = 8;
901 var->blue.offset = 0;
902 var->blue.length = 8;
903 break;
904
905 default:
906 return -EINVAL;
907 }
908
909 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
910 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
911 mode_valid = 1;
912
913 /* calculate modeline if supported by monitor */
914 if (!mode_valid && info->monspecs.gtf) {
915 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
916 mode_valid = 1;
917 }
918
919 if (!mode_valid) {
920 const struct fb_videomode *mode;
921
922 mode = fb_find_best_mode(var, &info->modelist);
923 if (mode) {
924 savage_update_var(var, mode);
925 mode_valid = 1;
926 }
927 }
928
929 if (!mode_valid && info->monspecs.modedb_len)
930 return -EINVAL;
931
932 /* Is the mode larger than the LCD panel? */
933 if (par->SavagePanelWidth &&
934 (var->xres > par->SavagePanelWidth ||
935 var->yres > par->SavagePanelHeight)) {
936 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
937 "(%dx%d)\n", var->xres, var->yres,
938 par->SavagePanelWidth,
939 par->SavagePanelHeight);
940 return -1;
941 }
942
943 if (var->yres_virtual < var->yres)
944 var->yres_virtual = var->yres;
945 if (var->xres_virtual < var->xres)
946 var->xres_virtual = var->xres;
947
948 vramlen = info->fix.smem_len;
949
950 memlen = var->xres_virtual * var->bits_per_pixel *
951 var->yres_virtual / 8;
952 if (memlen > vramlen) {
953 var->yres_virtual = vramlen * 8 /
954 (var->xres_virtual * var->bits_per_pixel);
955 memlen = var->xres_virtual * var->bits_per_pixel *
956 var->yres_virtual / 8;
957 }
958
959 /* we must round yres/xres down, we already rounded y/xres_virtual up
960 if it was possible. We should return -EINVAL, but I disagree */
961 if (var->yres_virtual < var->yres)
962 var->yres = var->yres_virtual;
963 if (var->xres_virtual < var->xres)
964 var->xres = var->xres_virtual;
965 if (var->xoffset + var->xres > var->xres_virtual)
966 var->xoffset = var->xres_virtual - var->xres;
967 if (var->yoffset + var->yres > var->yres_virtual)
968 var->yoffset = var->yres_virtual - var->yres;
969
970 return 0;
971 }
972
973
savagefb_decode_var(struct fb_var_screeninfo * var,struct savagefb_par * par,struct savage_reg * reg)974 static int savagefb_decode_var(struct fb_var_screeninfo *var,
975 struct savagefb_par *par,
976 struct savage_reg *reg)
977 {
978 struct xtimings timings;
979 int width, dclk, i, j; /*, refresh; */
980 unsigned int m, n, r;
981 unsigned char tmp = 0;
982 unsigned int pixclock = var->pixclock;
983
984 DBG("savagefb_decode_var");
985
986 memset(&timings, 0, sizeof(timings));
987
988 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
989 timings.Clock = 1000000000 / pixclock;
990 if (timings.Clock < 1) timings.Clock = 1;
991 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
992 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
993 timings.HDisplay = var->xres;
994 timings.HSyncStart = timings.HDisplay + var->right_margin;
995 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
996 timings.HTotal = timings.HSyncEnd + var->left_margin;
997 timings.VDisplay = var->yres;
998 timings.VSyncStart = timings.VDisplay + var->lower_margin;
999 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
1000 timings.VTotal = timings.VSyncEnd + var->upper_margin;
1001 timings.sync = var->sync;
1002
1003
1004 par->depth = var->bits_per_pixel;
1005 par->vwidth = var->xres_virtual;
1006
1007 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
1008 timings.HDisplay *= 2;
1009 timings.HSyncStart *= 2;
1010 timings.HSyncEnd *= 2;
1011 timings.HTotal *= 2;
1012 }
1013
1014 /*
1015 * This will allocate the datastructure and initialize all of the
1016 * generic VGA registers.
1017 */
1018 vgaHWInit(var, par, &timings, reg);
1019
1020 /* We need to set CR67 whether or not we use the BIOS. */
1021
1022 dclk = timings.Clock;
1023 reg->CR67 = 0x00;
1024
1025 switch(var->bits_per_pixel) {
1026 case 8:
1027 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1028 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
1029 else
1030 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
1031 break;
1032 case 15:
1033 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1034 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1035 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
1036 else
1037 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
1038 break;
1039 case 16:
1040 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1041 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1042 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
1043 else
1044 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
1045 break;
1046 case 24:
1047 reg->CR67 = 0x70;
1048 break;
1049 case 32:
1050 reg->CR67 = 0xd0;
1051 break;
1052 }
1053
1054 /*
1055 * Either BIOS use is disabled, or we failed to find a suitable
1056 * match. Fall back to traditional register-crunching.
1057 */
1058
1059 vga_out8(0x3d4, 0x3a, par);
1060 tmp = vga_in8(0x3d5, par);
1061 if (1 /*FIXME:psav->pci_burst*/)
1062 reg->CR3A = (tmp & 0x7f) | 0x15;
1063 else
1064 reg->CR3A = tmp | 0x95;
1065
1066 reg->CR53 = 0x00;
1067 reg->CR31 = 0x8c;
1068 reg->CR66 = 0x89;
1069
1070 vga_out8(0x3d4, 0x58, par);
1071 reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1072 reg->CR58 |= 0x13;
1073
1074 reg->SR15 = 0x03 | 0x80;
1075 reg->SR18 = 0x00;
1076 reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1077
1078 vga_out8(0x3d4, 0x40, par);
1079 reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1080
1081 reg->MMPR0 = 0x010400;
1082 reg->MMPR1 = 0x00;
1083 reg->MMPR2 = 0x0808;
1084 reg->MMPR3 = 0x08080810;
1085
1086 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1087 /* m = 107; n = 4; r = 2; */
1088
1089 if (par->MCLK <= 0) {
1090 reg->SR10 = 255;
1091 reg->SR11 = 255;
1092 } else {
1093 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1094 ®->SR11, ®->SR10);
1095 /* reg->SR10 = 80; // MCLK == 286000 */
1096 /* reg->SR11 = 125; */
1097 }
1098
1099 reg->SR12 = (r << 6) | (n & 0x3f);
1100 reg->SR13 = m & 0xff;
1101 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1102
1103 if (var->bits_per_pixel < 24)
1104 reg->MMPR0 -= 0x8000;
1105 else
1106 reg->MMPR0 -= 0x4000;
1107
1108 if (timings.interlaced)
1109 reg->CR42 = 0x20;
1110 else
1111 reg->CR42 = 0x00;
1112
1113 reg->CR34 = 0x10; /* display fifo */
1114
1115 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1116 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1117 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1118 ((timings.HSyncStart & 0x800) >> 7);
1119
1120 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1121 i |= 0x08;
1122 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1123 i |= 0x20;
1124
1125 j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1126 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1127
1128 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1129 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1130 reg->CRTC[0] + ((i & 0x01) << 8))
1131 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1132 else
1133 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1134 }
1135
1136 reg->CR3B = j & 0xff;
1137 i |= (j & 0x100) >> 2;
1138 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1139 reg->CR5D = i;
1140 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1141 (((timings.VDisplay - 1) & 0x400) >> 9) |
1142 (((timings.VSyncStart) & 0x400) >> 8) |
1143 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1144 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1145 reg->CR91 = reg->CRTC[19] = 0xff & width;
1146 reg->CR51 = (0x300 & width) >> 4;
1147 reg->CR90 = 0x80 | (width >> 8);
1148 reg->MiscOutReg |= 0x0c;
1149
1150 /* Set frame buffer description. */
1151
1152 if (var->bits_per_pixel <= 8)
1153 reg->CR50 = 0;
1154 else if (var->bits_per_pixel <= 16)
1155 reg->CR50 = 0x10;
1156 else
1157 reg->CR50 = 0x30;
1158
1159 if (var->xres_virtual <= 640)
1160 reg->CR50 |= 0x40;
1161 else if (var->xres_virtual == 800)
1162 reg->CR50 |= 0x80;
1163 else if (var->xres_virtual == 1024)
1164 reg->CR50 |= 0x00;
1165 else if (var->xres_virtual == 1152)
1166 reg->CR50 |= 0x01;
1167 else if (var->xres_virtual == 1280)
1168 reg->CR50 |= 0xc0;
1169 else if (var->xres_virtual == 1600)
1170 reg->CR50 |= 0x81;
1171 else
1172 reg->CR50 |= 0xc1; /* Use GBD */
1173
1174 if (par->chip == S3_SAVAGE2000)
1175 reg->CR33 = 0x08;
1176 else
1177 reg->CR33 = 0x20;
1178
1179 reg->CRTC[0x17] = 0xeb;
1180
1181 reg->CR67 |= 1;
1182
1183 vga_out8(0x3d4, 0x36, par);
1184 reg->CR36 = vga_in8(0x3d5, par);
1185 vga_out8(0x3d4, 0x68, par);
1186 reg->CR68 = vga_in8(0x3d5, par);
1187 reg->CR69 = 0;
1188 vga_out8(0x3d4, 0x6f, par);
1189 reg->CR6F = vga_in8(0x3d5, par);
1190 vga_out8(0x3d4, 0x86, par);
1191 reg->CR86 = vga_in8(0x3d5, par);
1192 vga_out8(0x3d4, 0x88, par);
1193 reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1194 vga_out8(0x3d4, 0xb0, par);
1195 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1196
1197 return 0;
1198 }
1199
1200 /* --------------------------------------------------------------------- */
1201
1202 /*
1203 * Set a single color register. Return != 0 for invalid regno.
1204 */
savagefb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1205 static int savagefb_setcolreg(unsigned regno,
1206 unsigned red,
1207 unsigned green,
1208 unsigned blue,
1209 unsigned transp,
1210 struct fb_info *info)
1211 {
1212 struct savagefb_par *par = info->par;
1213
1214 if (regno >= NR_PALETTE)
1215 return -EINVAL;
1216
1217 par->palette[regno].red = red;
1218 par->palette[regno].green = green;
1219 par->palette[regno].blue = blue;
1220 par->palette[regno].transp = transp;
1221
1222 switch (info->var.bits_per_pixel) {
1223 case 8:
1224 vga_out8(0x3c8, regno, par);
1225
1226 vga_out8(0x3c9, red >> 10, par);
1227 vga_out8(0x3c9, green >> 10, par);
1228 vga_out8(0x3c9, blue >> 10, par);
1229 break;
1230
1231 case 16:
1232 if (regno < 16)
1233 ((u32 *)info->pseudo_palette)[regno] =
1234 ((red & 0xf800) ) |
1235 ((green & 0xfc00) >> 5) |
1236 ((blue & 0xf800) >> 11);
1237 break;
1238
1239 case 24:
1240 if (regno < 16)
1241 ((u32 *)info->pseudo_palette)[regno] =
1242 ((red & 0xff00) << 8) |
1243 ((green & 0xff00) ) |
1244 ((blue & 0xff00) >> 8);
1245 break;
1246 case 32:
1247 if (regno < 16)
1248 ((u32 *)info->pseudo_palette)[regno] =
1249 ((transp & 0xff00) << 16) |
1250 ((red & 0xff00) << 8) |
1251 ((green & 0xff00) ) |
1252 ((blue & 0xff00) >> 8);
1253 break;
1254
1255 default:
1256 return 1;
1257 }
1258
1259 return 0;
1260 }
1261
savagefb_set_par_int(struct savagefb_par * par,struct savage_reg * reg)1262 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
1263 {
1264 unsigned char tmp, cr3a, cr66, cr67;
1265
1266 DBG("savagefb_set_par_int");
1267
1268 par->SavageWaitIdle(par);
1269
1270 vga_out8(0x3c2, 0x23, par);
1271
1272 vga_out16(0x3d4, 0x4838, par);
1273 vga_out16(0x3d4, 0xa539, par);
1274 vga_out16(0x3c4, 0x0608, par);
1275
1276 vgaHWProtect(par, 1);
1277
1278 /*
1279 * Some Savage/MX and /IX systems go nuts when trying to exit the
1280 * server after WindowMaker has displayed a gradient background. I
1281 * haven't been able to find what causes it, but a non-destructive
1282 * switch to mode 3 here seems to eliminate the issue.
1283 */
1284
1285 VerticalRetraceWait(par);
1286 vga_out8(0x3d4, 0x67, par);
1287 cr67 = vga_in8(0x3d5, par);
1288 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1289
1290 vga_out8(0x3d4, 0x23, par);
1291 vga_out8(0x3d5, 0x00, par);
1292 vga_out8(0x3d4, 0x26, par);
1293 vga_out8(0x3d5, 0x00, par);
1294
1295 /* restore extended regs */
1296 vga_out8(0x3d4, 0x66, par);
1297 vga_out8(0x3d5, reg->CR66, par);
1298 vga_out8(0x3d4, 0x3a, par);
1299 vga_out8(0x3d5, reg->CR3A, par);
1300 vga_out8(0x3d4, 0x31, par);
1301 vga_out8(0x3d5, reg->CR31, par);
1302 vga_out8(0x3d4, 0x32, par);
1303 vga_out8(0x3d5, reg->CR32, par);
1304 vga_out8(0x3d4, 0x58, par);
1305 vga_out8(0x3d5, reg->CR58, par);
1306 vga_out8(0x3d4, 0x53, par);
1307 vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1308
1309 vga_out16(0x3c4, 0x0608, par);
1310
1311 /* Restore DCLK registers. */
1312
1313 vga_out8(0x3c4, 0x0e, par);
1314 vga_out8(0x3c5, reg->SR0E, par);
1315 vga_out8(0x3c4, 0x0f, par);
1316 vga_out8(0x3c5, reg->SR0F, par);
1317 vga_out8(0x3c4, 0x29, par);
1318 vga_out8(0x3c5, reg->SR29, par);
1319 vga_out8(0x3c4, 0x15, par);
1320 vga_out8(0x3c5, reg->SR15, par);
1321
1322 /* Restore flat panel expansion regsters. */
1323 if (par->chip == S3_SAVAGE_MX) {
1324 int i;
1325
1326 for (i = 0; i < 8; i++) {
1327 vga_out8(0x3c4, 0x54+i, par);
1328 vga_out8(0x3c5, reg->SR54[i], par);
1329 }
1330 }
1331
1332 vgaHWRestore (par, reg);
1333
1334 /* extended mode timing registers */
1335 vga_out8(0x3d4, 0x53, par);
1336 vga_out8(0x3d5, reg->CR53, par);
1337 vga_out8(0x3d4, 0x5d, par);
1338 vga_out8(0x3d5, reg->CR5D, par);
1339 vga_out8(0x3d4, 0x5e, par);
1340 vga_out8(0x3d5, reg->CR5E, par);
1341 vga_out8(0x3d4, 0x3b, par);
1342 vga_out8(0x3d5, reg->CR3B, par);
1343 vga_out8(0x3d4, 0x3c, par);
1344 vga_out8(0x3d5, reg->CR3C, par);
1345 vga_out8(0x3d4, 0x43, par);
1346 vga_out8(0x3d5, reg->CR43, par);
1347 vga_out8(0x3d4, 0x65, par);
1348 vga_out8(0x3d5, reg->CR65, par);
1349
1350 /* restore the desired video mode with cr67 */
1351 vga_out8(0x3d4, 0x67, par);
1352 /* following part not present in X11 driver */
1353 cr67 = vga_in8(0x3d5, par) & 0xf;
1354 vga_out8(0x3d5, 0x50 | cr67, par);
1355 udelay(10000);
1356 vga_out8(0x3d4, 0x67, par);
1357 /* end of part */
1358 vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1359
1360 /* other mode timing and extended regs */
1361 vga_out8(0x3d4, 0x34, par);
1362 vga_out8(0x3d5, reg->CR34, par);
1363 vga_out8(0x3d4, 0x40, par);
1364 vga_out8(0x3d5, reg->CR40, par);
1365 vga_out8(0x3d4, 0x42, par);
1366 vga_out8(0x3d5, reg->CR42, par);
1367 vga_out8(0x3d4, 0x45, par);
1368 vga_out8(0x3d5, reg->CR45, par);
1369 vga_out8(0x3d4, 0x50, par);
1370 vga_out8(0x3d5, reg->CR50, par);
1371 vga_out8(0x3d4, 0x51, par);
1372 vga_out8(0x3d5, reg->CR51, par);
1373
1374 /* memory timings */
1375 vga_out8(0x3d4, 0x36, par);
1376 vga_out8(0x3d5, reg->CR36, par);
1377 vga_out8(0x3d4, 0x60, par);
1378 vga_out8(0x3d5, reg->CR60, par);
1379 vga_out8(0x3d4, 0x68, par);
1380 vga_out8(0x3d5, reg->CR68, par);
1381 vga_out8(0x3d4, 0x69, par);
1382 vga_out8(0x3d5, reg->CR69, par);
1383 vga_out8(0x3d4, 0x6f, par);
1384 vga_out8(0x3d5, reg->CR6F, par);
1385
1386 vga_out8(0x3d4, 0x33, par);
1387 vga_out8(0x3d5, reg->CR33, par);
1388 vga_out8(0x3d4, 0x86, par);
1389 vga_out8(0x3d5, reg->CR86, par);
1390 vga_out8(0x3d4, 0x88, par);
1391 vga_out8(0x3d5, reg->CR88, par);
1392 vga_out8(0x3d4, 0x90, par);
1393 vga_out8(0x3d5, reg->CR90, par);
1394 vga_out8(0x3d4, 0x91, par);
1395 vga_out8(0x3d5, reg->CR91, par);
1396
1397 if (par->chip == S3_SAVAGE4) {
1398 vga_out8(0x3d4, 0xb0, par);
1399 vga_out8(0x3d5, reg->CRB0, par);
1400 }
1401
1402 vga_out8(0x3d4, 0x32, par);
1403 vga_out8(0x3d5, reg->CR32, par);
1404
1405 /* unlock extended seq regs */
1406 vga_out8(0x3c4, 0x08, par);
1407 vga_out8(0x3c5, 0x06, par);
1408
1409 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1410 * that we should leave the default SR10 and SR11 values there.
1411 */
1412 if (reg->SR10 != 255) {
1413 vga_out8(0x3c4, 0x10, par);
1414 vga_out8(0x3c5, reg->SR10, par);
1415 vga_out8(0x3c4, 0x11, par);
1416 vga_out8(0x3c5, reg->SR11, par);
1417 }
1418
1419 /* restore extended seq regs for dclk */
1420 vga_out8(0x3c4, 0x0e, par);
1421 vga_out8(0x3c5, reg->SR0E, par);
1422 vga_out8(0x3c4, 0x0f, par);
1423 vga_out8(0x3c5, reg->SR0F, par);
1424 vga_out8(0x3c4, 0x12, par);
1425 vga_out8(0x3c5, reg->SR12, par);
1426 vga_out8(0x3c4, 0x13, par);
1427 vga_out8(0x3c5, reg->SR13, par);
1428 vga_out8(0x3c4, 0x29, par);
1429 vga_out8(0x3c5, reg->SR29, par);
1430 vga_out8(0x3c4, 0x18, par);
1431 vga_out8(0x3c5, reg->SR18, par);
1432
1433 /* load new m, n pll values for dclk & mclk */
1434 vga_out8(0x3c4, 0x15, par);
1435 tmp = vga_in8(0x3c5, par) & ~0x21;
1436
1437 vga_out8(0x3c5, tmp | 0x03, par);
1438 vga_out8(0x3c5, tmp | 0x23, par);
1439 vga_out8(0x3c5, tmp | 0x03, par);
1440 vga_out8(0x3c5, reg->SR15, par);
1441 udelay(100);
1442
1443 vga_out8(0x3c4, 0x30, par);
1444 vga_out8(0x3c5, reg->SR30, par);
1445 vga_out8(0x3c4, 0x08, par);
1446 vga_out8(0x3c5, reg->SR08, par);
1447
1448 /* now write out cr67 in full, possibly starting STREAMS */
1449 VerticalRetraceWait(par);
1450 vga_out8(0x3d4, 0x67, par);
1451 vga_out8(0x3d5, reg->CR67, par);
1452
1453 vga_out8(0x3d4, 0x66, par);
1454 cr66 = vga_in8(0x3d5, par);
1455 vga_out8(0x3d5, cr66 | 0x80, par);
1456 vga_out8(0x3d4, 0x3a, par);
1457 cr3a = vga_in8(0x3d5, par);
1458 vga_out8(0x3d5, cr3a | 0x80, par);
1459
1460 if (par->chip != S3_SAVAGE_MX) {
1461 VerticalRetraceWait(par);
1462 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1463 par->SavageWaitIdle(par);
1464 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1465 par->SavageWaitIdle(par);
1466 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1467 par->SavageWaitIdle(par);
1468 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1469 }
1470
1471 vga_out8(0x3d4, 0x66, par);
1472 vga_out8(0x3d5, cr66, par);
1473 vga_out8(0x3d4, 0x3a, par);
1474 vga_out8(0x3d5, cr3a, par);
1475
1476 SavageSetup2DEngine(par);
1477 vgaHWProtect(par, 0);
1478 }
1479
savagefb_update_start(struct savagefb_par * par,int base)1480 static void savagefb_update_start(struct savagefb_par *par, int base)
1481 {
1482 /* program the start address registers */
1483 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1484 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1485 vga_out8(0x3d4, 0x69, par);
1486 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1487 }
1488
1489
savagefb_set_fix(struct fb_info * info)1490 static void savagefb_set_fix(struct fb_info *info)
1491 {
1492 info->fix.line_length = info->var.xres_virtual *
1493 info->var.bits_per_pixel / 8;
1494
1495 if (info->var.bits_per_pixel == 8) {
1496 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1497 info->fix.xpanstep = 4;
1498 } else {
1499 info->fix.visual = FB_VISUAL_TRUECOLOR;
1500 info->fix.xpanstep = 2;
1501 }
1502
1503 }
1504
savagefb_set_par(struct fb_info * info)1505 static int savagefb_set_par(struct fb_info *info)
1506 {
1507 struct savagefb_par *par = info->par;
1508 struct fb_var_screeninfo *var = &info->var;
1509 int err;
1510
1511 DBG("savagefb_set_par");
1512 err = savagefb_decode_var(var, par, &par->state);
1513 if (err)
1514 return err;
1515
1516 if (par->dacSpeedBpp <= 0) {
1517 if (var->bits_per_pixel > 24)
1518 par->dacSpeedBpp = par->clock[3];
1519 else if (var->bits_per_pixel >= 24)
1520 par->dacSpeedBpp = par->clock[2];
1521 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1522 par->dacSpeedBpp = par->clock[1];
1523 else if (var->bits_per_pixel <= 8)
1524 par->dacSpeedBpp = par->clock[0];
1525 }
1526
1527 /* Set ramdac limits */
1528 par->maxClock = par->dacSpeedBpp;
1529 par->minClock = 10000;
1530
1531 savagefb_set_par_int(par, &par->state);
1532 fb_set_cmap(&info->cmap, info);
1533 savagefb_set_fix(info);
1534 savagefb_set_clip(info);
1535
1536 SavagePrintRegs(par);
1537 return 0;
1538 }
1539
1540 /*
1541 * Pan or Wrap the Display
1542 */
savagefb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1543 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1544 struct fb_info *info)
1545 {
1546 struct savagefb_par *par = info->par;
1547 int base;
1548
1549 base = (var->yoffset * info->fix.line_length
1550 + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2;
1551
1552 savagefb_update_start(par, base);
1553 return 0;
1554 }
1555
savagefb_blank(int blank,struct fb_info * info)1556 static int savagefb_blank(int blank, struct fb_info *info)
1557 {
1558 struct savagefb_par *par = info->par;
1559 u8 sr8 = 0, srd = 0;
1560
1561 if (par->display_type == DISP_CRT) {
1562 vga_out8(0x3c4, 0x08, par);
1563 sr8 = vga_in8(0x3c5, par);
1564 sr8 |= 0x06;
1565 vga_out8(0x3c5, sr8, par);
1566 vga_out8(0x3c4, 0x0d, par);
1567 srd = vga_in8(0x3c5, par);
1568 srd &= 0x50;
1569
1570 switch (blank) {
1571 case FB_BLANK_UNBLANK:
1572 case FB_BLANK_NORMAL:
1573 break;
1574 case FB_BLANK_VSYNC_SUSPEND:
1575 srd |= 0x10;
1576 break;
1577 case FB_BLANK_HSYNC_SUSPEND:
1578 srd |= 0x40;
1579 break;
1580 case FB_BLANK_POWERDOWN:
1581 srd |= 0x50;
1582 break;
1583 }
1584
1585 vga_out8(0x3c4, 0x0d, par);
1586 vga_out8(0x3c5, srd, par);
1587 }
1588
1589 if (par->display_type == DISP_LCD ||
1590 par->display_type == DISP_DFP) {
1591 switch(blank) {
1592 case FB_BLANK_UNBLANK:
1593 case FB_BLANK_NORMAL:
1594 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1595 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1596 break;
1597 case FB_BLANK_VSYNC_SUSPEND:
1598 case FB_BLANK_HSYNC_SUSPEND:
1599 case FB_BLANK_POWERDOWN:
1600 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1601 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1602 break;
1603 }
1604 }
1605
1606 return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1607 }
1608
savagefb_open(struct fb_info * info,int user)1609 static int savagefb_open(struct fb_info *info, int user)
1610 {
1611 struct savagefb_par *par = info->par;
1612
1613 mutex_lock(&par->open_lock);
1614
1615 if (!par->open_count) {
1616 memset(&par->vgastate, 0, sizeof(par->vgastate));
1617 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
1618 VGA_SAVE_MODE;
1619 par->vgastate.vgabase = par->mmio.vbase + 0x8000;
1620 save_vga(&par->vgastate);
1621 savage_get_default_par(par, &par->initial);
1622 }
1623
1624 par->open_count++;
1625 mutex_unlock(&par->open_lock);
1626 return 0;
1627 }
1628
savagefb_release(struct fb_info * info,int user)1629 static int savagefb_release(struct fb_info *info, int user)
1630 {
1631 struct savagefb_par *par = info->par;
1632
1633 mutex_lock(&par->open_lock);
1634
1635 if (par->open_count == 1) {
1636 savage_set_default_par(par, &par->initial);
1637 restore_vga(&par->vgastate);
1638 }
1639
1640 par->open_count--;
1641 mutex_unlock(&par->open_lock);
1642 return 0;
1643 }
1644
1645 static struct fb_ops savagefb_ops = {
1646 .owner = THIS_MODULE,
1647 .fb_open = savagefb_open,
1648 .fb_release = savagefb_release,
1649 .fb_check_var = savagefb_check_var,
1650 .fb_set_par = savagefb_set_par,
1651 .fb_setcolreg = savagefb_setcolreg,
1652 .fb_pan_display = savagefb_pan_display,
1653 .fb_blank = savagefb_blank,
1654 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1655 .fb_fillrect = savagefb_fillrect,
1656 .fb_copyarea = savagefb_copyarea,
1657 .fb_imageblit = savagefb_imageblit,
1658 .fb_sync = savagefb_sync,
1659 #else
1660 .fb_fillrect = cfb_fillrect,
1661 .fb_copyarea = cfb_copyarea,
1662 .fb_imageblit = cfb_imageblit,
1663 #endif
1664 };
1665
1666 /* --------------------------------------------------------------------- */
1667
1668 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1669 .accel_flags = FB_ACCELF_TEXT,
1670 .xres = 800,
1671 .yres = 600,
1672 .xres_virtual = 800,
1673 .yres_virtual = 600,
1674 .bits_per_pixel = 8,
1675 .pixclock = 25000,
1676 .left_margin = 88,
1677 .right_margin = 40,
1678 .upper_margin = 23,
1679 .lower_margin = 1,
1680 .hsync_len = 128,
1681 .vsync_len = 4,
1682 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1683 .vmode = FB_VMODE_NONINTERLACED
1684 };
1685
savage_enable_mmio(struct savagefb_par * par)1686 static void savage_enable_mmio(struct savagefb_par *par)
1687 {
1688 unsigned char val;
1689
1690 DBG("savage_enable_mmio\n");
1691
1692 val = vga_in8(0x3c3, par);
1693 vga_out8(0x3c3, val | 0x01, par);
1694 val = vga_in8(0x3cc, par);
1695 vga_out8(0x3c2, val | 0x01, par);
1696
1697 if (par->chip >= S3_SAVAGE4) {
1698 vga_out8(0x3d4, 0x40, par);
1699 val = vga_in8(0x3d5, par);
1700 vga_out8(0x3d5, val | 1, par);
1701 }
1702 }
1703
1704
savage_disable_mmio(struct savagefb_par * par)1705 static void savage_disable_mmio(struct savagefb_par *par)
1706 {
1707 unsigned char val;
1708
1709 DBG("savage_disable_mmio\n");
1710
1711 if (par->chip >= S3_SAVAGE4) {
1712 vga_out8(0x3d4, 0x40, par);
1713 val = vga_in8(0x3d5, par);
1714 vga_out8(0x3d5, val | 1, par);
1715 }
1716 }
1717
1718
savage_map_mmio(struct fb_info * info)1719 static int __devinit savage_map_mmio(struct fb_info *info)
1720 {
1721 struct savagefb_par *par = info->par;
1722 DBG("savage_map_mmio");
1723
1724 if (S3_SAVAGE3D_SERIES(par->chip))
1725 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1726 SAVAGE_NEWMMIO_REGBASE_S3;
1727 else
1728 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1729 SAVAGE_NEWMMIO_REGBASE_S4;
1730
1731 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1732
1733 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1734 if (!par->mmio.vbase) {
1735 printk("savagefb: unable to map memory mapped IO\n");
1736 return -ENOMEM;
1737 } else
1738 printk(KERN_INFO "savagefb: mapped io at %p\n",
1739 par->mmio.vbase);
1740
1741 info->fix.mmio_start = par->mmio.pbase;
1742 info->fix.mmio_len = par->mmio.len;
1743
1744 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1745 par->bci_ptr = 0;
1746
1747 savage_enable_mmio(par);
1748
1749 return 0;
1750 }
1751
savage_unmap_mmio(struct fb_info * info)1752 static void savage_unmap_mmio(struct fb_info *info)
1753 {
1754 struct savagefb_par *par = info->par;
1755 DBG("savage_unmap_mmio");
1756
1757 savage_disable_mmio(par);
1758
1759 if (par->mmio.vbase) {
1760 iounmap(par->mmio.vbase);
1761 par->mmio.vbase = NULL;
1762 }
1763 }
1764
savage_map_video(struct fb_info * info,int video_len)1765 static int __devinit savage_map_video(struct fb_info *info,
1766 int video_len)
1767 {
1768 struct savagefb_par *par = info->par;
1769 int resource;
1770
1771 DBG("savage_map_video");
1772
1773 if (S3_SAVAGE3D_SERIES(par->chip))
1774 resource = 0;
1775 else
1776 resource = 1;
1777
1778 par->video.pbase = pci_resource_start(par->pcidev, resource);
1779 par->video.len = video_len;
1780 par->video.vbase = ioremap(par->video.pbase, par->video.len);
1781
1782 if (!par->video.vbase) {
1783 printk("savagefb: unable to map screen memory\n");
1784 return -ENOMEM;
1785 } else
1786 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1787 "pbase == %x\n", par->video.vbase, par->video.pbase);
1788
1789 info->fix.smem_start = par->video.pbase;
1790 info->fix.smem_len = par->video.len - par->cob_size;
1791 info->screen_base = par->video.vbase;
1792
1793 #ifdef CONFIG_MTRR
1794 par->video.mtrr = mtrr_add(par->video.pbase, video_len,
1795 MTRR_TYPE_WRCOMB, 1);
1796 #endif
1797
1798 /* Clear framebuffer, it's all white in memory after boot */
1799 memset_io(par->video.vbase, 0, par->video.len);
1800
1801 return 0;
1802 }
1803
savage_unmap_video(struct fb_info * info)1804 static void savage_unmap_video(struct fb_info *info)
1805 {
1806 struct savagefb_par *par = info->par;
1807
1808 DBG("savage_unmap_video");
1809
1810 if (par->video.vbase) {
1811 #ifdef CONFIG_MTRR
1812 mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
1813 #endif
1814
1815 iounmap(par->video.vbase);
1816 par->video.vbase = NULL;
1817 info->screen_base = NULL;
1818 }
1819 }
1820
savage_init_hw(struct savagefb_par * par)1821 static int savage_init_hw(struct savagefb_par *par)
1822 {
1823 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1824
1825 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1826 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
1827 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1828 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1829 int videoRam, videoRambytes, dvi;
1830
1831 DBG("savage_init_hw");
1832
1833 /* unprotect CRTC[0-7] */
1834 vga_out8(0x3d4, 0x11, par);
1835 tmp = vga_in8(0x3d5, par);
1836 vga_out8(0x3d5, tmp & 0x7f, par);
1837
1838 /* unlock extended regs */
1839 vga_out16(0x3d4, 0x4838, par);
1840 vga_out16(0x3d4, 0xa039, par);
1841 vga_out16(0x3c4, 0x0608, par);
1842
1843 vga_out8(0x3d4, 0x40, par);
1844 tmp = vga_in8(0x3d5, par);
1845 vga_out8(0x3d5, tmp & ~0x01, par);
1846
1847 /* unlock sys regs */
1848 vga_out8(0x3d4, 0x38, par);
1849 vga_out8(0x3d5, 0x48, par);
1850
1851 /* Unlock system registers. */
1852 vga_out16(0x3d4, 0x4838, par);
1853
1854 /* Next go on to detect amount of installed ram */
1855
1856 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1857 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1858
1859 /* Compute the amount of video memory and offscreen memory. */
1860
1861 switch (par->chip) {
1862 case S3_SAVAGE3D:
1863 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1864 break;
1865
1866 case S3_SAVAGE4:
1867 /*
1868 * The Savage4 has one ugly special case to consider. On
1869 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1870 * when it really means 8MB. Why do it the same when you
1871 * can do it different...
1872 */
1873 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1874 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1875 RamSavage4[1] = 8;
1876
1877 /*FALLTHROUGH*/
1878
1879 case S3_SAVAGE2000:
1880 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1881 break;
1882
1883 case S3_SAVAGE_MX:
1884 case S3_SUPERSAVAGE:
1885 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1886 break;
1887
1888 case S3_PROSAVAGE:
1889 case S3_PROSAVAGEDDR:
1890 case S3_TWISTER:
1891 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1892 break;
1893
1894 default:
1895 /* How did we get here? */
1896 videoRam = 0;
1897 break;
1898 }
1899
1900 videoRambytes = videoRam * 1024;
1901
1902 printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
1903
1904 /* reset graphics engine to avoid memory corruption */
1905 vga_out8(0x3d4, 0x66, par);
1906 cr66 = vga_in8(0x3d5, par);
1907 vga_out8(0x3d5, cr66 | 0x02, par);
1908 udelay(10000);
1909
1910 vga_out8(0x3d4, 0x66, par);
1911 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1912 udelay(10000);
1913
1914
1915 /*
1916 * reset memory interface, 3D engine, AGP master, PCI master,
1917 * master engine unit, motion compensation/LPB
1918 */
1919 vga_out8(0x3d4, 0x3f, par);
1920 cr3f = vga_in8(0x3d5, par);
1921 vga_out8(0x3d5, cr3f | 0x08, par);
1922 udelay(10000);
1923
1924 vga_out8(0x3d4, 0x3f, par);
1925 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1926 udelay(10000);
1927
1928 /* Savage ramdac speeds */
1929 par->numClocks = 4;
1930 par->clock[0] = 250000;
1931 par->clock[1] = 250000;
1932 par->clock[2] = 220000;
1933 par->clock[3] = 220000;
1934
1935 /* detect current mclk */
1936 vga_out8(0x3c4, 0x08, par);
1937 sr8 = vga_in8(0x3c5, par);
1938 vga_out8(0x3c5, 0x06, par);
1939 vga_out8(0x3c4, 0x10, par);
1940 n = vga_in8(0x3c5, par);
1941 vga_out8(0x3c4, 0x11, par);
1942 m = vga_in8(0x3c5, par);
1943 vga_out8(0x3c4, 0x08, par);
1944 vga_out8(0x3c5, sr8, par);
1945 m &= 0x7f;
1946 n1 = n & 0x1f;
1947 n2 = (n >> 5) & 0x03;
1948 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1949 printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1950 par->MCLK);
1951
1952 /* check for DVI/flat panel */
1953 dvi = 0;
1954
1955 if (par->chip == S3_SAVAGE4) {
1956 unsigned char sr30 = 0x00;
1957
1958 vga_out8(0x3c4, 0x30, par);
1959 /* clear bit 1 */
1960 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1961 sr30 = vga_in8(0x3c5, par);
1962 if (sr30 & 0x02 /*0x04 */) {
1963 dvi = 1;
1964 printk("savagefb: Digital Flat Panel Detected\n");
1965 }
1966 }
1967
1968 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1969 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1970 par->display_type = DISP_LCD;
1971 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1972 par->display_type = DISP_DFP;
1973 else
1974 par->display_type = DISP_CRT;
1975
1976 /* Check LCD panel parrmation */
1977
1978 if (par->display_type == DISP_LCD) {
1979 unsigned char cr6b = VGArCR(0x6b, par);
1980
1981 int panelX = (VGArSEQ(0x61, par) +
1982 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1983 int panelY = (VGArSEQ(0x69, par) +
1984 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1985
1986 char * sTechnology = "Unknown";
1987
1988 /* OK, I admit it. I don't know how to limit the max dot clock
1989 * for LCD panels of various sizes. I thought I copied the
1990 * formula from the BIOS, but many users have parrmed me of
1991 * my folly.
1992 *
1993 * Instead, I'll abandon any attempt to automatically limit the
1994 * clock, and add an LCDClock option to XF86Config. Some day,
1995 * I should come back to this.
1996 */
1997
1998 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1999 ActiveCRT = 0x01,
2000 ActiveLCD = 0x02,
2001 ActiveTV = 0x04,
2002 ActiveCRT2 = 0x20,
2003 ActiveDUO = 0x80
2004 };
2005
2006 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
2007 sTechnology = "TFT";
2008 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
2009 sTechnology = "DSTN";
2010 } else {
2011 sTechnology = "STN";
2012 }
2013
2014 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
2015 panelX, panelY, sTechnology,
2016 cr6b & ActiveLCD ? "and active" : "but not active");
2017
2018 if (cr6b & ActiveLCD) {
2019 /*
2020 * If the LCD is active and panel expansion is enabled,
2021 * we probably want to kill the HW cursor.
2022 */
2023
2024 printk(KERN_INFO "savagefb: Limiting video mode to "
2025 "%dx%d\n", panelX, panelY);
2026
2027 par->SavagePanelWidth = panelX;
2028 par->SavagePanelHeight = panelY;
2029
2030 } else
2031 par->display_type = DISP_CRT;
2032 }
2033
2034 savage_get_default_par(par, &par->state);
2035 par->save = par->state;
2036
2037 if (S3_SAVAGE4_SERIES(par->chip)) {
2038 /*
2039 * The Savage4 and ProSavage have COB coherency bugs which
2040 * render the buffer useless. We disable it.
2041 */
2042 par->cob_index = 2;
2043 par->cob_size = 0x8000 << par->cob_index;
2044 par->cob_offset = videoRambytes;
2045 } else {
2046 /* We use 128kB for the COB on all chips. */
2047
2048 par->cob_index = 7;
2049 par->cob_size = 0x400 << par->cob_index;
2050 par->cob_offset = videoRambytes - par->cob_size;
2051 }
2052
2053 return videoRambytes;
2054 }
2055
savage_init_fb_info(struct fb_info * info,struct pci_dev * dev,const struct pci_device_id * id)2056 static int __devinit savage_init_fb_info(struct fb_info *info,
2057 struct pci_dev *dev,
2058 const struct pci_device_id *id)
2059 {
2060 struct savagefb_par *par = info->par;
2061 int err = 0;
2062
2063 par->pcidev = dev;
2064
2065 info->fix.type = FB_TYPE_PACKED_PIXELS;
2066 info->fix.type_aux = 0;
2067 info->fix.ypanstep = 1;
2068 info->fix.ywrapstep = 0;
2069 info->fix.accel = id->driver_data;
2070
2071 switch (info->fix.accel) {
2072 case FB_ACCEL_SUPERSAVAGE:
2073 par->chip = S3_SUPERSAVAGE;
2074 snprintf(info->fix.id, 16, "SuperSavage");
2075 break;
2076 case FB_ACCEL_SAVAGE4:
2077 par->chip = S3_SAVAGE4;
2078 snprintf(info->fix.id, 16, "Savage4");
2079 break;
2080 case FB_ACCEL_SAVAGE3D:
2081 par->chip = S3_SAVAGE3D;
2082 snprintf(info->fix.id, 16, "Savage3D");
2083 break;
2084 case FB_ACCEL_SAVAGE3D_MV:
2085 par->chip = S3_SAVAGE3D;
2086 snprintf(info->fix.id, 16, "Savage3D-MV");
2087 break;
2088 case FB_ACCEL_SAVAGE2000:
2089 par->chip = S3_SAVAGE2000;
2090 snprintf(info->fix.id, 16, "Savage2000");
2091 break;
2092 case FB_ACCEL_SAVAGE_MX_MV:
2093 par->chip = S3_SAVAGE_MX;
2094 snprintf(info->fix.id, 16, "Savage/MX-MV");
2095 break;
2096 case FB_ACCEL_SAVAGE_MX:
2097 par->chip = S3_SAVAGE_MX;
2098 snprintf(info->fix.id, 16, "Savage/MX");
2099 break;
2100 case FB_ACCEL_SAVAGE_IX_MV:
2101 par->chip = S3_SAVAGE_MX;
2102 snprintf(info->fix.id, 16, "Savage/IX-MV");
2103 break;
2104 case FB_ACCEL_SAVAGE_IX:
2105 par->chip = S3_SAVAGE_MX;
2106 snprintf(info->fix.id, 16, "Savage/IX");
2107 break;
2108 case FB_ACCEL_PROSAVAGE_PM:
2109 par->chip = S3_PROSAVAGE;
2110 snprintf(info->fix.id, 16, "ProSavagePM");
2111 break;
2112 case FB_ACCEL_PROSAVAGE_KM:
2113 par->chip = S3_PROSAVAGE;
2114 snprintf(info->fix.id, 16, "ProSavageKM");
2115 break;
2116 case FB_ACCEL_S3TWISTER_P:
2117 par->chip = S3_TWISTER;
2118 snprintf(info->fix.id, 16, "TwisterP");
2119 break;
2120 case FB_ACCEL_S3TWISTER_K:
2121 par->chip = S3_TWISTER;
2122 snprintf(info->fix.id, 16, "TwisterK");
2123 break;
2124 case FB_ACCEL_PROSAVAGE_DDR:
2125 par->chip = S3_PROSAVAGEDDR;
2126 snprintf(info->fix.id, 16, "ProSavageDDR");
2127 break;
2128 case FB_ACCEL_PROSAVAGE_DDRK:
2129 par->chip = S3_PROSAVAGEDDR;
2130 snprintf(info->fix.id, 16, "ProSavage8");
2131 break;
2132 }
2133
2134 if (S3_SAVAGE3D_SERIES(par->chip)) {
2135 par->SavageWaitIdle = savage3D_waitidle;
2136 par->SavageWaitFifo = savage3D_waitfifo;
2137 } else if (S3_SAVAGE4_SERIES(par->chip) ||
2138 S3_SUPERSAVAGE == par->chip) {
2139 par->SavageWaitIdle = savage4_waitidle;
2140 par->SavageWaitFifo = savage4_waitfifo;
2141 } else {
2142 par->SavageWaitIdle = savage2000_waitidle;
2143 par->SavageWaitFifo = savage2000_waitfifo;
2144 }
2145
2146 info->var.nonstd = 0;
2147 info->var.activate = FB_ACTIVATE_NOW;
2148 info->var.width = -1;
2149 info->var.height = -1;
2150 info->var.accel_flags = 0;
2151
2152 info->fbops = &savagefb_ops;
2153 info->flags = FBINFO_DEFAULT |
2154 FBINFO_HWACCEL_YPAN |
2155 FBINFO_HWACCEL_XPAN;
2156
2157 info->pseudo_palette = par->pseudo_palette;
2158
2159 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2160 /* FIFO size + padding for commands */
2161 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL);
2162
2163 err = -ENOMEM;
2164 if (info->pixmap.addr) {
2165 info->pixmap.size = 8*1024;
2166 info->pixmap.scan_align = 4;
2167 info->pixmap.buf_align = 4;
2168 info->pixmap.access_align = 32;
2169
2170 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2171 if (!err)
2172 info->flags |= FBINFO_HWACCEL_COPYAREA |
2173 FBINFO_HWACCEL_FILLRECT |
2174 FBINFO_HWACCEL_IMAGEBLIT;
2175 }
2176 #endif
2177 return err;
2178 }
2179
2180 /* --------------------------------------------------------------------- */
2181
savagefb_probe(struct pci_dev * dev,const struct pci_device_id * id)2182 static int __devinit savagefb_probe(struct pci_dev* dev,
2183 const struct pci_device_id* id)
2184 {
2185 struct fb_info *info;
2186 struct savagefb_par *par;
2187 u_int h_sync, v_sync;
2188 int err, lpitch;
2189 int video_len;
2190
2191 DBG("savagefb_probe");
2192
2193 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2194 if (!info)
2195 return -ENOMEM;
2196 par = info->par;
2197 mutex_init(&par->open_lock);
2198 err = pci_enable_device(dev);
2199 if (err)
2200 goto failed_enable;
2201
2202 if ((err = pci_request_regions(dev, "savagefb"))) {
2203 printk(KERN_ERR "cannot request PCI regions\n");
2204 goto failed_enable;
2205 }
2206
2207 err = -ENOMEM;
2208
2209 if ((err = savage_init_fb_info(info, dev, id)))
2210 goto failed_init;
2211
2212 err = savage_map_mmio(info);
2213 if (err)
2214 goto failed_mmio;
2215
2216 video_len = savage_init_hw(par);
2217 /* FIXME: can't be negative */
2218 if (video_len < 0) {
2219 err = video_len;
2220 goto failed_mmio;
2221 }
2222
2223 err = savage_map_video(info, video_len);
2224 if (err)
2225 goto failed_video;
2226
2227 INIT_LIST_HEAD(&info->modelist);
2228 #if defined(CONFIG_FB_SAVAGE_I2C)
2229 savagefb_create_i2c_busses(info);
2230 savagefb_probe_i2c_connector(info, &par->edid);
2231 fb_edid_to_monspecs(par->edid, &info->monspecs);
2232 kfree(par->edid);
2233 fb_videomode_to_modelist(info->monspecs.modedb,
2234 info->monspecs.modedb_len,
2235 &info->modelist);
2236 #endif
2237 info->var = savagefb_var800x600x8;
2238 /* if a panel was detected, default to a CVT mode instead */
2239 if (par->SavagePanelWidth) {
2240 struct fb_videomode cvt_mode;
2241
2242 memset(&cvt_mode, 0, sizeof(cvt_mode));
2243 cvt_mode.xres = par->SavagePanelWidth;
2244 cvt_mode.yres = par->SavagePanelHeight;
2245 cvt_mode.refresh = 60;
2246 /* FIXME: if we know there is only the panel
2247 * we can enable reduced blanking as well */
2248 if (fb_find_mode_cvt(&cvt_mode, 0, 0))
2249 printk(KERN_WARNING "No CVT mode found for panel\n");
2250 else if (fb_find_mode(&info->var, info, NULL, NULL, 0,
2251 &cvt_mode, 0) != 3)
2252 info->var = savagefb_var800x600x8;
2253 }
2254
2255 if (mode_option) {
2256 fb_find_mode(&info->var, info, mode_option,
2257 info->monspecs.modedb, info->monspecs.modedb_len,
2258 NULL, 8);
2259 } else if (info->monspecs.modedb != NULL) {
2260 const struct fb_videomode *mode;
2261
2262 mode = fb_find_best_display(&info->monspecs, &info->modelist);
2263 savage_update_var(&info->var, mode);
2264 }
2265
2266 /* maximize virtual vertical length */
2267 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2268 info->var.yres_virtual = info->fix.smem_len/lpitch;
2269
2270 if (info->var.yres_virtual < info->var.yres)
2271 goto failed;
2272
2273 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2274 /*
2275 * The clipping coordinates are masked with 0xFFF, so limit our
2276 * virtual resolutions to these sizes.
2277 */
2278 if (info->var.yres_virtual > 0x1000)
2279 info->var.yres_virtual = 0x1000;
2280
2281 if (info->var.xres_virtual > 0x1000)
2282 info->var.xres_virtual = 0x1000;
2283 #endif
2284 savagefb_check_var(&info->var, info);
2285 savagefb_set_fix(info);
2286
2287 /*
2288 * Calculate the hsync and vsync frequencies. Note that
2289 * we split the 1e12 constant up so that we can preserve
2290 * the precision and fit the results into 32-bit registers.
2291 * (1953125000 * 512 = 1e12)
2292 */
2293 h_sync = 1953125000 / info->var.pixclock;
2294 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2295 info->var.right_margin +
2296 info->var.hsync_len);
2297 v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2298 info->var.lower_margin + info->var.vsync_len);
2299
2300 printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2301 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2302 info->fix.smem_len >> 10,
2303 info->var.xres, info->var.yres,
2304 h_sync / 1000, h_sync % 1000, v_sync);
2305
2306
2307 fb_destroy_modedb(info->monspecs.modedb);
2308 info->monspecs.modedb = NULL;
2309
2310 err = register_framebuffer(info);
2311 if (err < 0)
2312 goto failed;
2313
2314 printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2315 info->fix.id);
2316
2317 /*
2318 * Our driver data
2319 */
2320 pci_set_drvdata(dev, info);
2321
2322 return 0;
2323
2324 failed:
2325 #ifdef CONFIG_FB_SAVAGE_I2C
2326 savagefb_delete_i2c_busses(info);
2327 #endif
2328 fb_alloc_cmap(&info->cmap, 0, 0);
2329 savage_unmap_video(info);
2330 failed_video:
2331 savage_unmap_mmio(info);
2332 failed_mmio:
2333 kfree(info->pixmap.addr);
2334 failed_init:
2335 pci_release_regions(dev);
2336 failed_enable:
2337 framebuffer_release(info);
2338
2339 return err;
2340 }
2341
savagefb_remove(struct pci_dev * dev)2342 static void __devexit savagefb_remove(struct pci_dev *dev)
2343 {
2344 struct fb_info *info = pci_get_drvdata(dev);
2345
2346 DBG("savagefb_remove");
2347
2348 if (info) {
2349 /*
2350 * If unregister_framebuffer fails, then
2351 * we will be leaving hooks that could cause
2352 * oopsen laying around.
2353 */
2354 if (unregister_framebuffer(info))
2355 printk(KERN_WARNING "savagefb: danger danger! "
2356 "Oopsen imminent!\n");
2357
2358 #ifdef CONFIG_FB_SAVAGE_I2C
2359 savagefb_delete_i2c_busses(info);
2360 #endif
2361 fb_alloc_cmap(&info->cmap, 0, 0);
2362 savage_unmap_video(info);
2363 savage_unmap_mmio(info);
2364 kfree(info->pixmap.addr);
2365 pci_release_regions(dev);
2366 framebuffer_release(info);
2367
2368 /*
2369 * Ensure that the driver data is no longer
2370 * valid.
2371 */
2372 pci_set_drvdata(dev, NULL);
2373 }
2374 }
2375
savagefb_suspend(struct pci_dev * dev,pm_message_t mesg)2376 static int savagefb_suspend(struct pci_dev *dev, pm_message_t mesg)
2377 {
2378 struct fb_info *info = pci_get_drvdata(dev);
2379 struct savagefb_par *par = info->par;
2380
2381 DBG("savagefb_suspend");
2382
2383 if (mesg.event == PM_EVENT_PRETHAW)
2384 mesg.event = PM_EVENT_FREEZE;
2385 par->pm_state = mesg.event;
2386 dev->dev.power.power_state = mesg;
2387
2388 /*
2389 * For PM_EVENT_FREEZE, do not power down so the console
2390 * can remain active.
2391 */
2392 if (mesg.event == PM_EVENT_FREEZE)
2393 return 0;
2394
2395 console_lock();
2396 fb_set_suspend(info, 1);
2397
2398 if (info->fbops->fb_sync)
2399 info->fbops->fb_sync(info);
2400
2401 savagefb_blank(FB_BLANK_POWERDOWN, info);
2402 savage_set_default_par(par, &par->save);
2403 savage_disable_mmio(par);
2404 pci_save_state(dev);
2405 pci_disable_device(dev);
2406 pci_set_power_state(dev, pci_choose_state(dev, mesg));
2407 console_unlock();
2408
2409 return 0;
2410 }
2411
savagefb_resume(struct pci_dev * dev)2412 static int savagefb_resume(struct pci_dev* dev)
2413 {
2414 struct fb_info *info = pci_get_drvdata(dev);
2415 struct savagefb_par *par = info->par;
2416 int cur_state = par->pm_state;
2417
2418 DBG("savage_resume");
2419
2420 par->pm_state = PM_EVENT_ON;
2421
2422 /*
2423 * The adapter was not powered down coming back from a
2424 * PM_EVENT_FREEZE.
2425 */
2426 if (cur_state == PM_EVENT_FREEZE) {
2427 pci_set_power_state(dev, PCI_D0);
2428 return 0;
2429 }
2430
2431 console_lock();
2432
2433 pci_set_power_state(dev, PCI_D0);
2434 pci_restore_state(dev);
2435
2436 if (pci_enable_device(dev))
2437 DBG("err");
2438
2439 pci_set_master(dev);
2440 savage_enable_mmio(par);
2441 savage_init_hw(par);
2442 savagefb_set_par(info);
2443 fb_set_suspend(info, 0);
2444 savagefb_blank(FB_BLANK_UNBLANK, info);
2445 console_unlock();
2446
2447 return 0;
2448 }
2449
2450
2451 static struct pci_device_id savagefb_devices[] __devinitdata = {
2452 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2454
2455 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2456 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2457
2458 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2460
2461 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2463
2464 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2466
2467 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2469
2470 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2472
2473 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2475
2476 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2478
2479 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2481
2482 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2484
2485 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2487
2488 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2490
2491 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2493
2494 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2496
2497 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2499
2500 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2502
2503 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2505
2506 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2508
2509 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2511
2512 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2514
2515 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2517
2518 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2520
2521 {0, 0, 0, 0, 0, 0, 0}
2522 };
2523
2524 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2525
2526 static struct pci_driver savagefb_driver = {
2527 .name = "savagefb",
2528 .id_table = savagefb_devices,
2529 .probe = savagefb_probe,
2530 .suspend = savagefb_suspend,
2531 .resume = savagefb_resume,
2532 .remove = __devexit_p(savagefb_remove)
2533 };
2534
2535 /* **************************** exit-time only **************************** */
2536
savage_done(void)2537 static void __exit savage_done(void)
2538 {
2539 DBG("savage_done");
2540 pci_unregister_driver(&savagefb_driver);
2541 }
2542
2543
2544 /* ************************* init in-kernel code ************************** */
2545
savagefb_setup(char * options)2546 static int __init savagefb_setup(char *options)
2547 {
2548 #ifndef MODULE
2549 char *this_opt;
2550
2551 if (!options || !*options)
2552 return 0;
2553
2554 while ((this_opt = strsep(&options, ",")) != NULL) {
2555 mode_option = this_opt;
2556 }
2557 #endif /* !MODULE */
2558 return 0;
2559 }
2560
savagefb_init(void)2561 static int __init savagefb_init(void)
2562 {
2563 char *option;
2564
2565 DBG("savagefb_init");
2566
2567 if (fb_get_options("savagefb", &option))
2568 return -ENODEV;
2569
2570 savagefb_setup(option);
2571 return pci_register_driver(&savagefb_driver);
2572
2573 }
2574
2575 module_init(savagefb_init);
2576 module_exit(savage_done);
2577
2578 module_param(mode_option, charp, 0);
2579 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2580