16  *      - Redistributions of source code must retain the above
20  *      - Redistributions in binary form must reproduce the above
38  * of the QLogic_IB chip may render the chip or board unusable until the
82 		client_pool = dc->next;  in get_client()
88 		dc->next = NULL;  in get_client()
89 		dc->dd = dd;  in get_client()
90 		dc->pid = current->pid;  in get_client()
91 		dc->state = OPENED;  in get_client()
101 	struct qib_devdata *dd = dc->dd;  in return_client()
105 	if (dc == dd->diag_client) {  in return_client()
106 		dd->diag_client = dc->next;  in return_client()
109 		tdc = dc->dd->diag_client;  in return_client()
111 			if (dc == tdc->next) {  in return_client()
112 				tdc->next = dc->next;  in return_client()
116 			tdc = tdc->next;  in return_client()
120 		rdc->state = UNUSED;  in return_client()
121 		rdc->dd = NULL;  in return_client()
122 		rdc->pid = 0;  in return_client()
123 		rdc->next = client_pool;  in return_client()
170 	snprintf(name, sizeof(name), "ipath_diag%d", dd->unit);  in qib_diag_add()
171 	ret = qib_cdev_init(QIB_DIAG_MINOR_BASE + dd->unit, name,  in qib_diag_add()
172 			    &diag_file_ops, &dd->diag_cdev,  in qib_diag_add()
173 			    &dd->diag_device);  in qib_diag_add()
187 	qib_cdev_cleanup(&dd->diag_cdev, &dd->diag_device);  in qib_diag_remove()
193 	while (dd->diag_client)  in qib_diag_remove()
194 		return_client(dd->diag_client);  in qib_diag_remove()
199 		client_pool = dc->next;  in qib_diag_remove()
206 /* qib_remap_ioaddr32 - remap an offset into chip address space to __iomem *
209  * @offs: the offset in chip-space
210  * @cntp: Pointer to max (byte) count for transfer starting at offset
211  * This returns a u32 __iomem * so it can be used for both 64 and 32-bit
213  * write-combining, the logically contiguous address-space of the chip
214  * may be split into virtually non-contiguous spaces, with different
221  *		- kregs + sregs + cregs + uregs (in any order)
222  *		- piobufs (2K and 4K bufs in either order)
224  *		- kregs + sregs + cregs (in any order)
225  *		- piobufs (2K and 4K bufs in either order)
226  *		- uregs
228  * If cntp is non-NULL, returns how many bytes from offset can be accessed
236 	u32 __iomem *krb32 = (u32 __iomem *)dd->kregbase;  in qib_remap_ioaddr32()
242 	kreglen = (dd->kregend - dd->kregbase) * sizeof(u64);  in qib_remap_ioaddr32()
245 		cnt = kreglen - offset;  in qib_remap_ioaddr32()
254 	if (dd->userbase) {  in qib_remap_ioaddr32()
256 		u32 ulim = (dd->cfgctxts * dd->ureg_align) + dd->uregbase;  in qib_remap_ioaddr32()
257 		if (!dd->piovl15base)  in qib_remap_ioaddr32()
258 			snd_lim = dd->uregbase;  in qib_remap_ioaddr32()
259 		krb32 = (u32 __iomem *)dd->userbase;  in qib_remap_ioaddr32()
260 		if (offset >= dd->uregbase && offset < ulim) {  in qib_remap_ioaddr32()
261 			map = krb32 + (offset - dd->uregbase) / sizeof(u32);  in qib_remap_ioaddr32()
262 			cnt = ulim - offset;  in qib_remap_ioaddr32()
271 	 * chip-specific code here, so should not make many assumptions.  in qib_remap_ioaddr32()
277 	snd_bottom = dd->pio2k_bufbase;  in qib_remap_ioaddr32()
279 		u32 tot2k = dd->piobcnt2k * ALIGN(dd->piosize2k, dd->palign);  in qib_remap_ioaddr32()
285 	tot4k = dd->piobcnt4k * dd->align4k;  in qib_remap_ioaddr32()
286 	offs4k = dd->piobufbase >> 32;  in qib_remap_ioaddr32()
287 	if (dd->piobcnt4k) {  in qib_remap_ioaddr32()
292 			if (!dd->userbase || dd->piovl15base)  in qib_remap_ioaddr32()
301 		offset -= snd_bottom;  in qib_remap_ioaddr32()
302 		map = (u32 __iomem *)dd->piobase + (offset / sizeof(u32));  in qib_remap_ioaddr32()
303 		cnt = snd_lim - offset;  in qib_remap_ioaddr32()
306 	if (!map && offs4k && dd->piovl15base) {  in qib_remap_ioaddr32()
307 		snd_lim = offs4k + tot4k + 2 * dd->align4k;  in qib_remap_ioaddr32()
309 			map = (u32 __iomem *)dd->piovl15base +  in qib_remap_ioaddr32()
310 				((offset - (offs4k + tot4k)) / sizeof(u32));  in qib_remap_ioaddr32()
311 			cnt = snd_lim - offset;  in qib_remap_ioaddr32()
322  * qib_read_umem64 - read a 64-bit quantity from the chip into user space
332  * NOTE:  This assumes the chip address is 64-bit aligned.
343 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_read_umem64()
344 		ret = -EINVAL;  in qib_read_umem64()
356 			ret = -EFAULT;  in qib_read_umem64()
368  * qib_write_umem64 - write a 64-bit quantity to the chip from user space
375  * NOTE:  This assumes the chip address is 64-bit aligned.
387 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_write_umem64()
388 		ret = -EINVAL;  in qib_write_umem64()
399 			ret = -EFAULT;  in qib_write_umem64()
413  * qib_read_umem32 - read a 32-bit quantity from the chip into user space
431 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_read_umem32()
432 		ret = -EINVAL;  in qib_read_umem32()
444 			ret = -EFAULT;  in qib_read_umem32()
458  * qib_write_umem32 - write a 32-bit quantity to the chip from user space
477 	if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {  in qib_write_umem32()
478 		ret = -EINVAL;  in qib_write_umem32()
489 			ret = -EFAULT;  in qib_write_umem32()
504 	int unit = iminor(in) - QIB_DIAG_MINOR_BASE;  in qib_diag_open()
513 	if (dd == NULL || !(dd->flags & QIB_PRESENT) ||  in qib_diag_open()
514 	    !dd->kregbase) {  in qib_diag_open()
515 		ret = -ENODEV;  in qib_diag_open()
521 		ret = -ENOMEM;  in qib_diag_open()
524 	dc->next = dd->diag_client;  in qib_diag_open()
525 	dd->diag_client = dc;  in qib_diag_open()
526 	fp->private_data = dc;  in qib_diag_open()
535  * qib_diagpkt_write - write an IB packet
554 		ret = -EINVAL;  in qib_diagpkt_write()
558 		ret = -EFAULT;  in qib_diagpkt_write()
563 	if (!dd || !(dd->flags & QIB_PRESENT) || !dd->kregbase) {  in qib_diagpkt_write()
564 		ret = -ENODEV;  in qib_diagpkt_write()
567 	if (!(dd->flags & QIB_INITTED)) {  in qib_diagpkt_write()
569 		ret = -ENODEV;  in qib_diagpkt_write()
576 		ret = -EINVAL;  in qib_diagpkt_write()
581 		ret = -EINVAL;  in qib_diagpkt_write()
584 	if (!dp.port || dp.port > dd->num_pports) {  in qib_diagpkt_write()
585 		ret = -EINVAL;  in qib_diagpkt_write()
588 	ppd = &dd->pport[dp.port - 1];  in qib_diagpkt_write()
595 	if ((plen + 4) > ppd->ibmaxlen) {  in qib_diagpkt_write()
596 		ret = -EINVAL;  in qib_diagpkt_write()
601 		qib_devinfo(dd->pcidev, "Unable to allocate tmp buffer, "  in qib_diagpkt_write()
603 		ret = -ENOMEM;  in qib_diagpkt_write()
610 		ret = -EFAULT;  in qib_diagpkt_write()
619 	piobuf = dd->f_getsendbuf(ppd, dp.pbc_wd, &pbufn);  in qib_diagpkt_write()
621 		ret = -EBUSY;  in qib_diagpkt_write()
625 	dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbufn));  in qib_diagpkt_write()
628 	dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_DIS1, NULL);  in qib_diagpkt_write()
636 	if (dd->flags & QIB_PIO_FLUSH_WC) {  in qib_diagpkt_write()
638 		qib_pio_copy(piobuf + 2, tmpbuf, clen - 1);  in qib_diagpkt_write()
640 		__raw_writel(tmpbuf[clen - 1], piobuf + clen + 1);  in qib_diagpkt_write()
644 	if (dd->flags & QIB_USE_SPCL_TRIG) {  in qib_diagpkt_write()
645 		u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;  in qib_diagpkt_write()
652 	 * Ensure buffer is written to the chip, then re-enable  in qib_diagpkt_write()
658 	dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_ENAB1, NULL);  in qib_diagpkt_write()
670 	return_client(fp->private_data);  in qib_diag_release()
671 	fp->private_data = NULL;  in qib_diag_release()
677  * Chip-specific code calls to register its interest in
689 	int ret = -EINVAL;  in qib_register_observer()
693 	ret = -ENOMEM;  in qib_register_observer()
702 		spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_register_observer()
703 		olp->op = op;  in qib_register_observer()
704 		olp->next = dd->diag_observer_list;  in qib_register_observer()
705 		dd->diag_observer_list = olp;  in qib_register_observer()
706 		spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_register_observer()
719 	spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
720 	olp = dd->diag_observer_list;  in qib_unregister_observers()
723 		dd->diag_observer_list = olp->next;  in qib_unregister_observers()
724 		spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
727 		spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
728 		olp = dd->diag_observer_list;  in qib_unregister_observers()
730 	spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_unregister_observers()
744 	olp = dd->diag_observer_list;  in diag_get_observer()
746 		op = olp->op;  in diag_get_observer()
747 		if (addr >= op->bottom && addr <= op->top)  in diag_get_observer()
749 		olp = olp->next;  in diag_get_observer()
760 	struct qib_diag_client *dc = fp->private_data;  in qib_diag_read()
761 	struct qib_devdata *dd = dc->dd;  in qib_diag_read()
765 	if (dc->pid != current->pid) {  in qib_diag_read()
766 		ret = -EPERM;  in qib_diag_read()
770 	kreg_base = dd->kregbase;  in qib_diag_read()
775 		/* address or length is not 32-bit aligned, hence invalid */  in qib_diag_read()
776 		ret = -EINVAL;  in qib_diag_read()
777 	else if (dc->state < READY && (*off || count != 8))  in qib_diag_read()
778 		ret = -EINVAL;  /* prevent cat /dev/qib_diag* */  in qib_diag_read()
786 		ret = -1;  in qib_diag_read()
787 		spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_diag_read()
790 		 * we only support a single 32 or 64-bit read  in qib_diag_read()
796 			ret = op->hook(dd, op, offset, &data64, 0, use_32);  in qib_diag_read()
802 		spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_diag_read()
806 				 * Address or length is not 64-bit aligned;  in qib_diag_read()
807 				 * do 32-bit rd  in qib_diag_read()
819 				ret = -EFAULT;  in qib_diag_read()
826 		if (dc->state == OPENED)  in qib_diag_read()
827 			dc->state = INIT;  in qib_diag_read()
836 	struct qib_diag_client *dc = fp->private_data;  in qib_diag_write()
837 	struct qib_devdata *dd = dc->dd;  in qib_diag_write()
841 	if (dc->pid != current->pid) {  in qib_diag_write()
842 		ret = -EPERM;  in qib_diag_write()
846 	kreg_base = dd->kregbase;  in qib_diag_write()
851 		/* address or length is not 32-bit aligned, hence invalid */  in qib_diag_write()
852 		ret = -EINVAL;  in qib_diag_write()
853 	else if (dc->state < READY &&  in qib_diag_write()
854 		((*off || count != 8) || dc->state != INIT))  in qib_diag_write()
855 		/* No writes except second-step of init seq */  in qib_diag_write()
856 		ret = -EINVAL;  /* before any other write allowed */  in qib_diag_write()
864 		 * We only support a single 32 or 64-bit write  in qib_diag_write()
875 				ret = -EFAULT;  in qib_diag_write()
878 			spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);  in qib_diag_write()
881 				ret = op->hook(dd, op, offset, &data64, ~0Ull,  in qib_diag_write()
883 			spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);  in qib_diag_write()
889 				 * Address or length is not 64-bit aligned;  in qib_diag_write()
890 				 * do 32-bit write  in qib_diag_write()
903 		if (dc->state == INIT)  in qib_diag_write()
904 			dc->state = READY; /* all read/write OK now */  in qib_diag_write()