Lines Matching +full:render +full:- +full:max
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
70 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
78 /* MAX values used for gfx init */
105 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
107 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
109 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
123 return -EBUSY; in r600_do_wait_for_fifo()
130 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
132 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
138 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
147 return -EBUSY; in r600_do_wait_for_idle()
152 struct drm_sg_mem *entry = dev->sg; in r600_page_table_cleanup()
160 if (gart_info->bus_addr) { in r600_page_table_cleanup()
161 max_pages = (gart_info->table_size / sizeof(u64)); in r600_page_table_cleanup()
162 pages = (entry->pages <= max_pages) in r600_page_table_cleanup()
163 ? entry->pages : max_pages; in r600_page_table_cleanup()
166 if (!entry->busaddr[i]) in r600_page_table_cleanup()
168 pci_unmap_page(dev->pdev, entry->busaddr[i], in r600_page_table_cleanup()
171 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) in r600_page_table_cleanup()
172 gart_info->bus_addr = 0; in r600_page_table_cleanup()
179 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_page_table_init()
180 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; in r600_page_table_init()
181 struct drm_local_map *map = &gart_info->mapping; in r600_page_table_init()
182 struct drm_sg_mem *entry = dev->sg; in r600_page_table_init()
190 /* okay page table is available - lets rock */ in r600_page_table_init()
191 max_ati_pages = (gart_info->table_size / sizeof(u64)); in r600_page_table_init()
194 pages = (entry->pages <= max_real_pages) ? in r600_page_table_init()
195 entry->pages : max_real_pages; in r600_page_table_init()
197 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); in r600_page_table_init()
201 entry->busaddr[i] = pci_map_page(dev->pdev, in r600_page_table_init()
202 entry->pagelist[i], 0, in r600_page_table_init()
205 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { in r600_page_table_init()
210 entry_addr = entry->busaddr[i]; in r600_page_table_init()
233 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_vm_flush_gart_range()
235 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_flush_gart_range()
236 …_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1… in r600_vm_flush_gart_range()
241 countdown--; in r600_vm_flush_gart_range()
248 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_vm_init()
254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
255 …EON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1… in r600_vm_init()
304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r600_vm_init()
305 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
306 …EON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1… in r600_vm_init()
323 return -EINVAL; in r600_cp_init_microcode()
326 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_cp_init_microcode()
342 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { in r600_cp_init_microcode()
353 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); in r600_cp_init_microcode()
356 if (dev_priv->pfp_fw->size != pfp_req_size) { in r600_cp_init_microcode()
359 dev_priv->pfp_fw->size, fw_name); in r600_cp_init_microcode()
360 err = -EINVAL; in r600_cp_init_microcode()
365 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); in r600_cp_init_microcode()
368 if (dev_priv->me_fw->size != me_req_size) { in r600_cp_init_microcode()
371 dev_priv->me_fw->size, fw_name); in r600_cp_init_microcode()
372 err = -EINVAL; in r600_cp_init_microcode()
378 if (err != -EINVAL) in r600_cp_init_microcode()
382 release_firmware(dev_priv->pfp_fw); in r600_cp_init_microcode()
383 dev_priv->pfp_fw = NULL; in r600_cp_init_microcode()
384 release_firmware(dev_priv->me_fw); in r600_cp_init_microcode()
385 dev_priv->me_fw = NULL; in r600_cp_init_microcode()
395 if (!dev_priv->me_fw || !dev_priv->pfp_fw) in r600_cp_load_microcode()
413 fw_data = (const __be32 *)dev_priv->me_fw->data; in r600_cp_load_microcode()
419 fw_data = (const __be32 *)dev_priv->pfp_fw->data; in r600_cp_load_microcode()
433 drm_radeon_private_t *dev_priv = dev->dev_private; in r700_vm_init()
439 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
440 …EON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1… in r700_vm_init()
476 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r700_vm_init()
477 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
478 …EON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1… in r700_vm_init()
488 if (!dev_priv->me_fw || !dev_priv->pfp_fw) in r700_cp_load_microcode()
506 fw_data = (const __be32 *)dev_priv->pfp_fw->data; in r700_cp_load_microcode()
512 fw_data = (const __be32 *)dev_priv->me_fw->data; in r700_cp_load_microcode()
529 dev_priv->writeback_works = 0; in r600_test_writeback()
538 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { in r600_test_writeback()
547 if (tmp < dev_priv->usec_timeout) { in r600_test_writeback()
548 dev_priv->writeback_works = 1; in r600_test_writeback()
551 dev_priv->writeback_works = 0; in r600_test_writeback()
555 dev_priv->writeback_works = 0; in r600_test_writeback()
559 if (!dev_priv->writeback_works) { in r600_test_writeback()
573 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_engine_reset()
605 dev_priv->cp_running = 0; in r600_do_engine_reset()
758 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
760 dev_priv->r600_max_pipes = 4; in r600_gfx_init()
761 dev_priv->r600_max_tile_pipes = 8; in r600_gfx_init()
762 dev_priv->r600_max_simds = 4; in r600_gfx_init()
763 dev_priv->r600_max_backends = 4; in r600_gfx_init()
764 dev_priv->r600_max_gprs = 256; in r600_gfx_init()
765 dev_priv->r600_max_threads = 192; in r600_gfx_init()
766 dev_priv->r600_max_stack_entries = 256; in r600_gfx_init()
767 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
768 dev_priv->r600_max_gs_threads = 16; in r600_gfx_init()
769 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
770 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
771 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
772 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
776 dev_priv->r600_max_pipes = 2; in r600_gfx_init()
777 dev_priv->r600_max_tile_pipes = 2; in r600_gfx_init()
778 dev_priv->r600_max_simds = 3; in r600_gfx_init()
779 dev_priv->r600_max_backends = 1; in r600_gfx_init()
780 dev_priv->r600_max_gprs = 128; in r600_gfx_init()
781 dev_priv->r600_max_threads = 192; in r600_gfx_init()
782 dev_priv->r600_max_stack_entries = 128; in r600_gfx_init()
783 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
784 dev_priv->r600_max_gs_threads = 4; in r600_gfx_init()
785 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
786 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
787 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
788 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
794 dev_priv->r600_max_pipes = 1; in r600_gfx_init()
795 dev_priv->r600_max_tile_pipes = 1; in r600_gfx_init()
796 dev_priv->r600_max_simds = 2; in r600_gfx_init()
797 dev_priv->r600_max_backends = 1; in r600_gfx_init()
798 dev_priv->r600_max_gprs = 128; in r600_gfx_init()
799 dev_priv->r600_max_threads = 192; in r600_gfx_init()
800 dev_priv->r600_max_stack_entries = 128; in r600_gfx_init()
801 dev_priv->r600_max_hw_contexts = 4; in r600_gfx_init()
802 dev_priv->r600_max_gs_threads = 4; in r600_gfx_init()
803 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
804 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
805 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
806 dev_priv->r600_sq_num_cf_insts = 1; in r600_gfx_init()
809 dev_priv->r600_max_pipes = 4; in r600_gfx_init()
810 dev_priv->r600_max_tile_pipes = 4; in r600_gfx_init()
811 dev_priv->r600_max_simds = 4; in r600_gfx_init()
812 dev_priv->r600_max_backends = 4; in r600_gfx_init()
813 dev_priv->r600_max_gprs = 192; in r600_gfx_init()
814 dev_priv->r600_max_threads = 192; in r600_gfx_init()
815 dev_priv->r600_max_stack_entries = 256; in r600_gfx_init()
816 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
817 dev_priv->r600_max_gs_threads = 16; in r600_gfx_init()
818 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
819 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
820 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
821 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
843 switch (dev_priv->r600_max_tile_pipes) { in r600_gfx_init()
878 …R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_M… in r600_gfx_init()
882 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); in r600_gfx_init()
884 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); in r600_gfx_init()
886 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, in r600_gfx_init()
887 (R6XX_MAX_BACKENDS - in r600_gfx_init()
897 dev_priv->r600_group_size = 512; in r600_gfx_init()
899 dev_priv->r600_group_size = 256; in r600_gfx_init()
901 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); in r600_gfx_init()
903 dev_priv->r600_nbanks = 8; in r600_gfx_init()
905 dev_priv->r600_nbanks = 4; in r600_gfx_init()
913 …R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> … in r600_gfx_init()
915 …RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MAS… in r600_gfx_init()
929 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) in r600_gfx_init()
934 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) in r600_gfx_init()
938 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || in r600_gfx_init()
939 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || in r600_gfx_init()
940 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
941 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
942 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
943 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) in r600_gfx_init()
959 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
960 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
961 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
962 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { in r600_gfx_init()
967 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || in r600_gfx_init()
968 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { in r600_gfx_init()
989 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { in r600_gfx_init()
1003 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
1004 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
1005 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
1006 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { in r600_gfx_init()
1023 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || in r600_gfx_init()
1024 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { in r600_gfx_init()
1038 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { in r600_gfx_init()
1061 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
1062 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
1063 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
1064 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) in r600_gfx_init()
1099 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
1118 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; in r600_gfx_init()
1120 /* Max value for this is 256 */ in r600_gfx_init()
1140 /* clear render buffer base addresses */ in r600_gfx_init()
1150 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
1227 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_get_tile_pipe_to_backend_map()
1383 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1385 dev_priv->r600_max_pipes = 4; in r700_gfx_init()
1386 dev_priv->r600_max_tile_pipes = 8; in r700_gfx_init()
1387 dev_priv->r600_max_simds = 10; in r700_gfx_init()
1388 dev_priv->r600_max_backends = 4; in r700_gfx_init()
1389 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1390 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1391 dev_priv->r600_max_stack_entries = 512; in r700_gfx_init()
1392 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1393 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1394 dev_priv->r600_sx_max_export_size = 128; in r700_gfx_init()
1395 dev_priv->r600_sx_max_export_pos_size = 16; in r700_gfx_init()
1396 dev_priv->r600_sx_max_export_smx_size = 112; in r700_gfx_init()
1397 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1399 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1400 dev_priv->r700_sc_prim_fifo_size = 0xF9; in r700_gfx_init()
1401 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1402 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1405 dev_priv->r600_max_pipes = 2; in r700_gfx_init()
1406 dev_priv->r600_max_tile_pipes = 4; in r700_gfx_init()
1407 dev_priv->r600_max_simds = 8; in r700_gfx_init()
1408 dev_priv->r600_max_backends = 2; in r700_gfx_init()
1409 dev_priv->r600_max_gprs = 128; in r700_gfx_init()
1410 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1411 dev_priv->r600_max_stack_entries = 256; in r700_gfx_init()
1412 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1413 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1414 dev_priv->r600_sx_max_export_size = 256; in r700_gfx_init()
1415 dev_priv->r600_sx_max_export_pos_size = 32; in r700_gfx_init()
1416 dev_priv->r600_sx_max_export_smx_size = 224; in r700_gfx_init()
1417 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1419 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1420 dev_priv->r700_sc_prim_fifo_size = 0xf9; in r700_gfx_init()
1421 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1422 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1423 if (dev_priv->r600_sx_max_export_pos_size > 16) { in r700_gfx_init()
1424 dev_priv->r600_sx_max_export_pos_size -= 16; in r700_gfx_init()
1425 dev_priv->r600_sx_max_export_smx_size += 16; in r700_gfx_init()
1429 dev_priv->r600_max_pipes = 2; in r700_gfx_init()
1430 dev_priv->r600_max_tile_pipes = 2; in r700_gfx_init()
1431 dev_priv->r600_max_simds = 2; in r700_gfx_init()
1432 dev_priv->r600_max_backends = 1; in r700_gfx_init()
1433 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1434 dev_priv->r600_max_threads = 192; in r700_gfx_init()
1435 dev_priv->r600_max_stack_entries = 256; in r700_gfx_init()
1436 dev_priv->r600_max_hw_contexts = 4; in r700_gfx_init()
1437 dev_priv->r600_max_gs_threads = 8 * 2; in r700_gfx_init()
1438 dev_priv->r600_sx_max_export_size = 128; in r700_gfx_init()
1439 dev_priv->r600_sx_max_export_pos_size = 16; in r700_gfx_init()
1440 dev_priv->r600_sx_max_export_smx_size = 112; in r700_gfx_init()
1441 dev_priv->r600_sq_num_cf_insts = 1; in r700_gfx_init()
1443 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1444 dev_priv->r700_sc_prim_fifo_size = 0x40; in r700_gfx_init()
1445 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1446 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1449 dev_priv->r600_max_pipes = 4; in r700_gfx_init()
1450 dev_priv->r600_max_tile_pipes = 4; in r700_gfx_init()
1451 dev_priv->r600_max_simds = 8; in r700_gfx_init()
1452 dev_priv->r600_max_backends = 4; in r700_gfx_init()
1453 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1454 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1455 dev_priv->r600_max_stack_entries = 512; in r700_gfx_init()
1456 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1457 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1458 dev_priv->r600_sx_max_export_size = 256; in r700_gfx_init()
1459 dev_priv->r600_sx_max_export_pos_size = 32; in r700_gfx_init()
1460 dev_priv->r600_sx_max_export_smx_size = 224; in r700_gfx_init()
1461 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1463 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1464 dev_priv->r700_sc_prim_fifo_size = 0x100; in r700_gfx_init()
1465 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1466 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1468 if (dev_priv->r600_sx_max_export_pos_size > 16) { in r700_gfx_init()
1469 dev_priv->r600_sx_max_export_pos_size -= 16; in r700_gfx_init()
1470 dev_priv->r600_sx_max_export_smx_size += 16; in r700_gfx_init()
1493 switch (dev_priv->r600_max_tile_pipes) { in r700_gfx_init()
1510 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) in r700_gfx_init()
1531 …R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_M… in r700_gfx_init()
1535 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); in r700_gfx_init()
1537 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); in r700_gfx_init()
1539 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) in r700_gfx_init()
1543 dev_priv->r600_max_tile_pipes, in r700_gfx_init()
1544 (R7XX_MAX_BACKENDS - in r700_gfx_init()
1554 dev_priv->r600_group_size = 512; in r700_gfx_init()
1556 dev_priv->r600_group_size = 256; in r700_gfx_init()
1558 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); in r700_gfx_init()
1560 dev_priv->r600_nbanks = 8; in r700_gfx_init()
1562 dev_priv->r600_nbanks = 4; in r700_gfx_init()
1576 …R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> … in r700_gfx_init()
1578 …RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MAS… in r700_gfx_init()
1595 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); in r700_gfx_init()
1598 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) in r700_gfx_init()
1606 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1619 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { in r700_gfx_init()
1625 …R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | in r700_gfx_init()
1626 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | in r700_gfx_init()
1627 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); in r700_gfx_init()
1629 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | in r700_gfx_init()
1630 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | in r700_gfx_init()
1631 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); in r700_gfx_init()
1643 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | in r700_gfx_init()
1646 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1674 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) in r700_gfx_init()
1680 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1681 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1682 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); in r700_gfx_init()
1684 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | in r700_gfx_init()
1685 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); in r700_gfx_init()
1687 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | in r700_gfx_init()
1688 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | in r700_gfx_init()
1689 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); in r700_gfx_init()
1690 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) in r700_gfx_init()
1691 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); in r700_gfx_init()
1693 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); in r700_gfx_init()
1696 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1697 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); in r700_gfx_init()
1699 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1700 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); in r700_gfx_init()
1702 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1703 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1704 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1705 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); in r700_gfx_init()
1719 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) in r700_gfx_init()
1726 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1739 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; in r700_gfx_init()
1741 /* Max value for this is 256 */ in r700_gfx_init()
1763 /* clear render buffer base addresses */ in r700_gfx_init()
1793 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_cp_init_ring_buffer()
1809 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1810 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1814 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1815 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1828 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1829 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1834 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1835 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1842 dev_priv->ring.tail = 0; in r600_cp_init_ring_buffer()
1845 if (dev_priv->flags & RADEON_IS_AGP) { in r600_cp_init_ring_buffer()
1846 rptr_addr = dev_priv->ring_rptr->offset in r600_cp_init_ring_buffer()
1847 - dev->agp->base + in r600_cp_init_ring_buffer()
1848 dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1852 rptr_addr = dev_priv->ring_rptr->offset in r600_cp_init_ring_buffer()
1853 - ((unsigned long) dev->sg->virtual) in r600_cp_init_ring_buffer()
1854 + dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1862 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1863 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1866 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1867 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1871 if (dev_priv->flags & RADEON_IS_AGP) { in r600_cp_init_ring_buffer()
1873 radeon_write_agp_base(dev_priv, dev->agp->base); in r600_cp_init_ring_buffer()
1877 (((dev_priv->gart_vm_start - 1 + in r600_cp_init_ring_buffer()
1878 dev_priv->gart_size) & 0xffff0000) | in r600_cp_init_ring_buffer()
1879 (dev_priv->gart_vm_start >> 16))); in r600_cp_init_ring_buffer()
1881 ring_start = (dev_priv->cp_ring->offset in r600_cp_init_ring_buffer()
1882 - dev->agp->base in r600_cp_init_ring_buffer()
1883 + dev_priv->gart_vm_start); in r600_cp_init_ring_buffer()
1886 ring_start = (dev_priv->cp_ring->offset in r600_cp_init_ring_buffer()
1887 - (unsigned long)dev->sg->virtual in r600_cp_init_ring_buffer()
1888 + dev_priv->gart_vm_start); in r600_cp_init_ring_buffer()
1930 master_priv = file_priv->master->driver_priv; in r600_cp_init_ring_buffer()
1931 if (master_priv->sarea_priv) { in r600_cp_init_ring_buffer()
1932 master_priv->sarea_priv->last_frame = 0; in r600_cp_init_ring_buffer()
1933 master_priv->sarea_priv->last_dispatch = 0; in r600_cp_init_ring_buffer()
1934 master_priv->sarea_priv->last_clear = 0; in r600_cp_init_ring_buffer()
1943 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_cleanup_cp()
1950 if (dev->irq_enabled) in r600_do_cleanup_cp()
1954 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_cleanup_cp()
1955 if (dev_priv->cp_ring != NULL) { in r600_do_cleanup_cp()
1956 drm_core_ioremapfree(dev_priv->cp_ring, dev); in r600_do_cleanup_cp()
1957 dev_priv->cp_ring = NULL; in r600_do_cleanup_cp()
1959 if (dev_priv->ring_rptr != NULL) { in r600_do_cleanup_cp()
1960 drm_core_ioremapfree(dev_priv->ring_rptr, dev); in r600_do_cleanup_cp()
1961 dev_priv->ring_rptr = NULL; in r600_do_cleanup_cp()
1963 if (dev->agp_buffer_map != NULL) { in r600_do_cleanup_cp()
1964 drm_core_ioremapfree(dev->agp_buffer_map, dev); in r600_do_cleanup_cp()
1965 dev->agp_buffer_map = NULL; in r600_do_cleanup_cp()
1971 if (dev_priv->gart_info.bus_addr) in r600_do_cleanup_cp()
1972 r600_page_table_cleanup(dev, &dev_priv->gart_info); in r600_do_cleanup_cp()
1974 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { in r600_do_cleanup_cp()
1975 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); in r600_do_cleanup_cp()
1976 dev_priv->gart_info.addr = NULL; in r600_do_cleanup_cp()
1988 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_init_cp()
1989 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; in r600_do_init_cp()
1993 mutex_init(&dev_priv->cs_mutex); in r600_do_init_cp()
1996 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { in r600_do_init_cp()
1999 return -EINVAL; in r600_do_init_cp()
2002 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { in r600_do_init_cp()
2004 dev_priv->flags &= ~RADEON_IS_AGP; in r600_do_init_cp()
2009 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) in r600_do_init_cp()
2010 && !init->is_pci) { in r600_do_init_cp()
2012 dev_priv->flags |= RADEON_IS_AGP; in r600_do_init_cp()
2015 dev_priv->usec_timeout = init->usec_timeout; in r600_do_init_cp()
2016 if (dev_priv->usec_timeout < 1 || in r600_do_init_cp()
2017 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { in r600_do_init_cp()
2020 return -EINVAL; in r600_do_init_cp()
2025 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; in r600_do_init_cp()
2026 dev_priv->do_boxes = 0; in r600_do_init_cp()
2027 dev_priv->cp_mode = init->cp_mode; in r600_do_init_cp()
2029 /* We don't support anything other than bus-mastering ring mode, in r600_do_init_cp()
2033 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && in r600_do_init_cp()
2034 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { in r600_do_init_cp()
2035 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); in r600_do_init_cp()
2037 return -EINVAL; in r600_do_init_cp()
2040 switch (init->fb_bpp) { in r600_do_init_cp()
2042 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; in r600_do_init_cp()
2046 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; in r600_do_init_cp()
2049 dev_priv->front_offset = init->front_offset; in r600_do_init_cp()
2050 dev_priv->front_pitch = init->front_pitch; in r600_do_init_cp()
2051 dev_priv->back_offset = init->back_offset; in r600_do_init_cp()
2052 dev_priv->back_pitch = init->back_pitch; in r600_do_init_cp()
2054 dev_priv->ring_offset = init->ring_offset; in r600_do_init_cp()
2055 dev_priv->ring_rptr_offset = init->ring_rptr_offset; in r600_do_init_cp()
2056 dev_priv->buffers_offset = init->buffers_offset; in r600_do_init_cp()
2057 dev_priv->gart_textures_offset = init->gart_textures_offset; in r600_do_init_cp()
2059 master_priv->sarea = drm_getsarea(dev); in r600_do_init_cp()
2060 if (!master_priv->sarea) { in r600_do_init_cp()
2063 return -EINVAL; in r600_do_init_cp()
2066 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); in r600_do_init_cp()
2067 if (!dev_priv->cp_ring) { in r600_do_init_cp()
2070 return -EINVAL; in r600_do_init_cp()
2072 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); in r600_do_init_cp()
2073 if (!dev_priv->ring_rptr) { in r600_do_init_cp()
2076 return -EINVAL; in r600_do_init_cp()
2078 dev->agp_buffer_token = init->buffers_offset; in r600_do_init_cp()
2079 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); in r600_do_init_cp()
2080 if (!dev->agp_buffer_map) { in r600_do_init_cp()
2083 return -EINVAL; in r600_do_init_cp()
2086 if (init->gart_textures_offset) { in r600_do_init_cp()
2087 dev_priv->gart_textures = in r600_do_init_cp()
2088 drm_core_findmap(dev, init->gart_textures_offset); in r600_do_init_cp()
2089 if (!dev_priv->gart_textures) { in r600_do_init_cp()
2092 return -EINVAL; in r600_do_init_cp()
2098 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2099 drm_core_ioremap_wc(dev_priv->cp_ring, dev); in r600_do_init_cp()
2100 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); in r600_do_init_cp()
2101 drm_core_ioremap_wc(dev->agp_buffer_map, dev); in r600_do_init_cp()
2102 if (!dev_priv->cp_ring->handle || in r600_do_init_cp()
2103 !dev_priv->ring_rptr->handle || in r600_do_init_cp()
2104 !dev->agp_buffer_map->handle) { in r600_do_init_cp()
2107 return -EINVAL; in r600_do_init_cp()
2112 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; in r600_do_init_cp()
2113 dev_priv->ring_rptr->handle = in r600_do_init_cp()
2114 (void *)(unsigned long)dev_priv->ring_rptr->offset; in r600_do_init_cp()
2115 dev->agp_buffer_map->handle = in r600_do_init_cp()
2116 (void *)(unsigned long)dev->agp_buffer_map->offset; in r600_do_init_cp()
2118 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", in r600_do_init_cp()
2119 dev_priv->cp_ring->handle); in r600_do_init_cp()
2120 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", in r600_do_init_cp()
2121 dev_priv->ring_rptr->handle); in r600_do_init_cp()
2122 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", in r600_do_init_cp()
2123 dev->agp_buffer_map->handle); in r600_do_init_cp()
2126 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; in r600_do_init_cp()
2127 dev_priv->fb_size = in r600_do_init_cp()
2129 - dev_priv->fb_location; in r600_do_init_cp()
2131 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | in r600_do_init_cp()
2132 ((dev_priv->front_offset in r600_do_init_cp()
2133 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
2135 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | in r600_do_init_cp()
2136 ((dev_priv->back_offset in r600_do_init_cp()
2137 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
2139 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | in r600_do_init_cp()
2140 ((dev_priv->depth_offset in r600_do_init_cp()
2141 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
2143 dev_priv->gart_size = init->gart_size; in r600_do_init_cp()
2146 if (dev_priv->new_memmap) { in r600_do_init_cp()
2157 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2158 base = dev->agp->base; in r600_do_init_cp()
2160 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && in r600_do_init_cp()
2161 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { in r600_do_init_cp()
2163 dev->agp->base); in r600_do_init_cp()
2170 base = dev_priv->fb_location + dev_priv->fb_size; in r600_do_init_cp()
2171 if (base < dev_priv->fb_location || in r600_do_init_cp()
2172 ((base + dev_priv->gart_size) & 0xfffffffful) < base) in r600_do_init_cp()
2173 base = dev_priv->fb_location in r600_do_init_cp()
2174 - dev_priv->gart_size; in r600_do_init_cp()
2176 dev_priv->gart_vm_start = base & 0xffc00000u; in r600_do_init_cp()
2177 if (dev_priv->gart_vm_start != base) in r600_do_init_cp()
2179 base, dev_priv->gart_vm_start); in r600_do_init_cp()
2184 if (dev_priv->flags & RADEON_IS_AGP) in r600_do_init_cp()
2185 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in r600_do_init_cp()
2186 - dev->agp->base in r600_do_init_cp()
2187 + dev_priv->gart_vm_start); in r600_do_init_cp()
2190 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in r600_do_init_cp()
2191 - (unsigned long)dev->sg->virtual in r600_do_init_cp()
2192 + dev_priv->gart_vm_start); in r600_do_init_cp()
2195 (unsigned int) dev_priv->fb_location, in r600_do_init_cp()
2196 (unsigned int) dev_priv->fb_size); in r600_do_init_cp()
2197 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); in r600_do_init_cp()
2198 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", in r600_do_init_cp()
2199 (unsigned int) dev_priv->gart_vm_start); in r600_do_init_cp()
2200 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", in r600_do_init_cp()
2201 dev_priv->gart_buffers_offset); in r600_do_init_cp()
2203 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; in r600_do_init_cp()
2204 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle in r600_do_init_cp()
2205 + init->ring_size / sizeof(u32)); in r600_do_init_cp()
2206 dev_priv->ring.size = init->ring_size; in r600_do_init_cp()
2207 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); in r600_do_init_cp()
2209 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; in r600_do_init_cp()
2210 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); in r600_do_init_cp()
2212 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; in r600_do_init_cp()
2213 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); in r600_do_init_cp()
2215 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in r600_do_init_cp()
2217 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; in r600_do_init_cp()
2220 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2225 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); in r600_do_init_cp()
2227 if (!dev_priv->pcigart_offset_set) { in r600_do_init_cp()
2230 return -EINVAL; in r600_do_init_cp()
2233 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); in r600_do_init_cp()
2235 dev_priv->gart_info.bus_addr = in r600_do_init_cp()
2236 dev_priv->pcigart_offset + dev_priv->fb_location; in r600_do_init_cp()
2237 dev_priv->gart_info.mapping.offset = in r600_do_init_cp()
2238 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in r600_do_init_cp()
2239 dev_priv->gart_info.mapping.size = in r600_do_init_cp()
2240 dev_priv->gart_info.table_size; in r600_do_init_cp()
2242 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); in r600_do_init_cp()
2243 if (!dev_priv->gart_info.mapping.handle) { in r600_do_init_cp()
2246 return -EINVAL; in r600_do_init_cp()
2249 dev_priv->gart_info.addr = in r600_do_init_cp()
2250 dev_priv->gart_info.mapping.handle; in r600_do_init_cp()
2253 dev_priv->gart_info.addr, in r600_do_init_cp()
2254 dev_priv->pcigart_offset); in r600_do_init_cp()
2259 return -EINVAL; in r600_do_init_cp()
2262 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_do_init_cp()
2268 if (!dev_priv->me_fw || !dev_priv->pfp_fw) { in r600_do_init_cp()
2276 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_do_init_cp()
2283 dev_priv->last_buf = 0; in r600_do_init_cp()
2293 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_resume_cp()
2296 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { in r600_do_resume_cp()
2321 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); in r600_do_cp_idle()
2341 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) in r600_do_cp_start()
2345 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); in r600_do_cp_start()
2356 dev_priv->cp_running = 1; in r600_do_cp_start()
2368 dev_priv->ring.tail = cur_read_ptr; in r600_do_cp_reset()
2381 dev_priv->cp_running = 0; in r600_do_cp_stop()
2387 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_indirect()
2391 unsigned long offset = (dev_priv->gart_buffers_offset in r600_cp_dispatch_indirect()
2392 + buf->offset + start); in r600_cp_dispatch_indirect()
2393 int dwords = (end - start + 3) / sizeof(u32); in r600_cp_dispatch_indirect()
2400 * pad the data with a Type-2 CP packet. in r600_cp_dispatch_indirect()
2404 ((char *)dev->agp_buffer_map->handle in r600_cp_dispatch_indirect()
2405 + buf->offset + start); in r600_cp_dispatch_indirect()
2423 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_swap()
2424 struct drm_master *master = file_priv->master; in r600_cp_dispatch_swap()
2425 struct drm_radeon_master_private *master_priv = master->driver_priv; in r600_cp_dispatch_swap()
2426 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; in r600_cp_dispatch_swap()
2427 int nbox = sarea_priv->nbox; in r600_cp_dispatch_swap()
2428 struct drm_clip_rect *pbox = sarea_priv->boxes; in r600_cp_dispatch_swap()
2434 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) in r600_cp_dispatch_swap()
2439 if (sarea_priv->pfCurrentPage == 0) { in r600_cp_dispatch_swap()
2440 src_pitch = dev_priv->back_pitch; in r600_cp_dispatch_swap()
2441 dst_pitch = dev_priv->front_pitch; in r600_cp_dispatch_swap()
2442 src = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2443 dst = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2445 src_pitch = dev_priv->front_pitch; in r600_cp_dispatch_swap()
2446 dst_pitch = dev_priv->back_pitch; in r600_cp_dispatch_swap()
2447 src = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2448 dst = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2458 int w = pbox[i].x2 - x; in r600_cp_dispatch_swap()
2459 int h = pbox[i].y2 - y; in r600_cp_dispatch_swap()
2461 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); in r600_cp_dispatch_swap()
2470 /* Increment the frame counter. The client-side 3D driver must in r600_cp_dispatch_swap()
2474 sarea_priv->last_frame++; in r600_cp_dispatch_swap()
2477 R600_FRAME_AGE(sarea_priv->last_frame); in r600_cp_dispatch_swap()
2486 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_texture()
2493 if (!radeon_check_offset(dev_priv, tex->offset)) { in r600_cp_dispatch_texture()
2495 return -EINVAL; in r600_cp_dispatch_texture()
2498 /* this might fail for zero-sized uploads - are those illegal? */ in r600_cp_dispatch_texture()
2499 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { in r600_cp_dispatch_texture()
2501 return -EINVAL; in r600_cp_dispatch_texture()
2504 size = tex->height * tex->pitch; in r600_cp_dispatch_texture()
2509 dst_offset = tex->offset; in r600_cp_dispatch_texture()
2513 return -EAGAIN; in r600_cp_dispatch_texture()
2516 data = (const u8 __user *)image->data; in r600_cp_dispatch_texture()
2522 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) in r600_cp_dispatch_texture()
2523 return -EFAULT; in r600_cp_dispatch_texture()
2524 return -EAGAIN; in r600_cp_dispatch_texture()
2527 if (pass_size > buf->total) in r600_cp_dispatch_texture()
2528 pass_size = buf->total; in r600_cp_dispatch_texture()
2533 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); in r600_cp_dispatch_texture()
2537 return -EFAULT; in r600_cp_dispatch_texture()
2540 buf->file_priv = file_priv; in r600_cp_dispatch_texture()
2541 buf->used = pass_size; in r600_cp_dispatch_texture()
2542 src_offset = dev_priv->gart_buffers_offset + buf->offset; in r600_cp_dispatch_texture()
2546 radeon_cp_discard_buffer(dev, file_priv->master, buf); in r600_cp_dispatch_texture()
2549 image->data = (const u8 __user *)image->data + pass_size; in r600_cp_dispatch_texture()
2551 size -= pass_size; in r600_cp_dispatch_texture()
2564 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; in radeon_cs_id_get()
2565 if (!radeon->cs_id_scnt) { in radeon_cs_id_get()
2567 radeon->cs_id_wcnt += 0x01000000; in radeon_cs_id_get()
2569 radeon->cs_id_scnt = 1; in radeon_cs_id_get()
2571 return (radeon->cs_id_scnt | radeon->cs_id_wcnt); in radeon_cs_id_get()
2596 return -EBUSY; in r600_ib_get()
2598 buf->file_priv = fpriv; in r600_ib_get()
2606 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_ib_free()
2611 radeon_cp_discard_buffer(dev, fpriv->master, buf); in r600_ib_free()
2618 struct drm_radeon_private *dev_priv = dev->dev_private; in r600_cs_legacy_ioctl()
2627 return -EINVAL; in r600_cs_legacy_ioctl()
2629 family = dev_priv->flags & RADEON_FAMILY_MASK; in r600_cs_legacy_ioctl()
2632 return -EINVAL; in r600_cs_legacy_ioctl()
2634 mutex_lock(&dev_priv->cs_mutex); in r600_cs_legacy_ioctl()
2641 ib = dev->agp_buffer_map->handle + buf->offset; in r600_cs_legacy_ioctl()
2652 cs->cs_id = cs_id; in r600_cs_legacy_ioctl()
2653 mutex_unlock(&dev_priv->cs_mutex); in r600_cs_legacy_ioctl()
2659 struct drm_radeon_private *dev_priv = dev->dev_private; in r600_cs_legacy_get_tiling_conf()
2661 *npipes = dev_priv->r600_npipes; in r600_cs_legacy_get_tiling_conf()
2662 *nbanks = dev_priv->r600_nbanks; in r600_cs_legacy_get_tiling_conf()
2663 *group_size = dev_priv->r600_group_size; in r600_cs_legacy_get_tiling_conf()