Lines Matching +full:render +full:- +full:max
2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
16 * - hardware accelerated clear and move
19 * - wait for vertical retrace before writing to cr67
21 * - use synchronization registers cr23 and cr26
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
33 * - first working version
37 * - clock validations in decode_var
40 * - white margin on bootup
70 /* --------------------------------------------------------------------- */
77 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
84 /* --------------------------------------------------------------------- */
126 VGAwMISC(reg->MiscOutReg, par); in vgaHWRestore()
129 VGAwSEQ(i, reg->Sequencer[i], par); in vgaHWRestore()
131 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or in vgaHWRestore()
133 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore()
136 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore()
139 VGAwGR(i, reg->Graphics[i], par); in vgaHWRestore()
144 VGAwATTR(i, reg->Attribute[i], par); in vgaHWRestore()
154 reg->MiscOutReg = 0x23; in vgaHWInit()
156 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT)) in vgaHWInit()
157 reg->MiscOutReg |= 0x40; in vgaHWInit()
159 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT)) in vgaHWInit()
160 reg->MiscOutReg |= 0x80; in vgaHWInit()
165 reg->Sequencer[0x00] = 0x00; in vgaHWInit()
166 reg->Sequencer[0x01] = 0x01; in vgaHWInit()
167 reg->Sequencer[0x02] = 0x0F; in vgaHWInit()
168 reg->Sequencer[0x03] = 0x00; /* Font select */ in vgaHWInit()
169 reg->Sequencer[0x04] = 0x0E; /* Misc */ in vgaHWInit()
174 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
175 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
176 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
177 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
178 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
179 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
180 (((timings->HSyncEnd >> 3)) & 0x1f); in vgaHWInit()
181 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; in vgaHWInit()
182 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | in vgaHWInit()
183 (((timings->VDisplay - 1) & 0x100) >> 7) | in vgaHWInit()
184 ((timings->VSyncStart & 0x100) >> 6) | in vgaHWInit()
185 (((timings->VSyncStart - 1) & 0x100) >> 5) | in vgaHWInit()
187 (((timings->VTotal - 2) & 0x200) >> 4) | in vgaHWInit()
188 (((timings->VDisplay - 1) & 0x200) >> 3) | in vgaHWInit()
189 ((timings->VSyncStart & 0x200) >> 2); in vgaHWInit()
190 reg->CRTC[0x08] = 0x00; in vgaHWInit()
191 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; in vgaHWInit()
193 if (timings->dblscan) in vgaHWInit()
194 reg->CRTC[0x09] |= 0x80; in vgaHWInit()
196 reg->CRTC[0x0a] = 0x00; in vgaHWInit()
197 reg->CRTC[0x0b] = 0x00; in vgaHWInit()
198 reg->CRTC[0x0c] = 0x00; in vgaHWInit()
199 reg->CRTC[0x0d] = 0x00; in vgaHWInit()
200 reg->CRTC[0x0e] = 0x00; in vgaHWInit()
201 reg->CRTC[0x0f] = 0x00; in vgaHWInit()
202 reg->CRTC[0x10] = timings->VSyncStart & 0xff; in vgaHWInit()
203 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; in vgaHWInit()
204 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; in vgaHWInit()
205 reg->CRTC[0x13] = var->xres_virtual >> 4; in vgaHWInit()
206 reg->CRTC[0x14] = 0x00; in vgaHWInit()
207 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; in vgaHWInit()
208 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; in vgaHWInit()
209 reg->CRTC[0x17] = 0xc3; in vgaHWInit()
210 reg->CRTC[0x18] = 0xff; in vgaHWInit()
221 reg->Graphics[0x00] = 0x00; in vgaHWInit()
222 reg->Graphics[0x01] = 0x00; in vgaHWInit()
223 reg->Graphics[0x02] = 0x00; in vgaHWInit()
224 reg->Graphics[0x03] = 0x00; in vgaHWInit()
225 reg->Graphics[0x04] = 0x00; in vgaHWInit()
226 reg->Graphics[0x05] = 0x40; in vgaHWInit()
227 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ in vgaHWInit()
228 reg->Graphics[0x07] = 0x0F; in vgaHWInit()
229 reg->Graphics[0x08] = 0xFF; in vgaHWInit()
232 reg->Attribute[0x00] = 0x00; /* standard colormap translation */ in vgaHWInit()
233 reg->Attribute[0x01] = 0x01; in vgaHWInit()
234 reg->Attribute[0x02] = 0x02; in vgaHWInit()
235 reg->Attribute[0x03] = 0x03; in vgaHWInit()
236 reg->Attribute[0x04] = 0x04; in vgaHWInit()
237 reg->Attribute[0x05] = 0x05; in vgaHWInit()
238 reg->Attribute[0x06] = 0x06; in vgaHWInit()
239 reg->Attribute[0x07] = 0x07; in vgaHWInit()
240 reg->Attribute[0x08] = 0x08; in vgaHWInit()
241 reg->Attribute[0x09] = 0x09; in vgaHWInit()
242 reg->Attribute[0x0a] = 0x0A; in vgaHWInit()
243 reg->Attribute[0x0b] = 0x0B; in vgaHWInit()
244 reg->Attribute[0x0c] = 0x0C; in vgaHWInit()
245 reg->Attribute[0x0d] = 0x0D; in vgaHWInit()
246 reg->Attribute[0x0e] = 0x0E; in vgaHWInit()
247 reg->Attribute[0x0f] = 0x0F; in vgaHWInit()
248 reg->Attribute[0x10] = 0x41; in vgaHWInit()
249 reg->Attribute[0x11] = 0xFF; in vgaHWInit()
250 reg->Attribute[0x12] = 0x0F; in vgaHWInit()
251 reg->Attribute[0x13] = 0x00; in vgaHWInit()
252 reg->Attribute[0x14] = 0x00; in vgaHWInit()
255 /* -------------------- Hardware specific routines ------------------------- */
265 int slots = MAXFIFO - space; in savage3D_waitfifo()
273 int slots = MAXFIFO - space; in savage4_waitfifo()
281 int slots = MAXFIFO - space; in savage2000_waitfifo()
312 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth); in SavageSetup2DEngine()
313 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth); in SavageSetup2DEngine()
315 switch(par->chip) { in SavageSetup2DEngine()
322 (par->cob_offset >> 11) | (par->cob_index << 29), in SavageSetup2DEngine()
348 (par->cob_offset >> 7) | (par->cob_index), in SavageSetup2DEngine()
359 /* Turn on 16-bit register access. */ in SavageSetup2DEngine()
381 par->bci_ptr = 0; in SavageSetup2DEngine()
382 par->SavageWaitFifo(par, 4); in SavageSetup2DEngine()
392 * --Tony in SavageSetup2DEngine()
394 par->bci_ptr = 0; in SavageSetup2DEngine()
395 par->SavageWaitFifo(par, 4); in SavageSetup2DEngine()
405 struct savagefb_par *par = info->par; in savagefb_set_clip()
409 par->bci_ptr = 0; in savagefb_set_clip()
410 par->SavageWaitFifo(par,3); in savagefb_set_clip()
449 diff = freq * (1 << n2) * n1 - BASE_FREQ * m; in SavageCalcClock()
451 diff = -diff; in SavageCalcClock()
462 *ndiv = best_n1 - 2; in SavageCalcClock()
464 *mdiv = best_m - 2; in SavageCalcClock()
487 diff = freq * (1 << n2) * n1 - BASE_FREQ * m; in common_calc_clock()
489 diff = -diff; in common_calc_clock()
501 *ndiv = (best_n1 - 2) | (best_n2 << 6); in common_calc_clock()
503 *ndiv = (best_n1 - 2) | (best_n2 << 5); in common_calc_clock()
505 *mdiv = best_m - 2; in common_calc_clock()
543 /* --------------------------------------------------------------------- */
575 reg->SR08 = vga_in8(0x3c5, par); in savage_get_default_par()
580 reg->CR31 = vga_in8(0x3d5, par); in savage_get_default_par()
582 reg->CR32 = vga_in8(0x3d5, par); in savage_get_default_par()
584 reg->CR34 = vga_in8(0x3d5, par); in savage_get_default_par()
586 reg->CR36 = vga_in8(0x3d5, par); in savage_get_default_par()
588 reg->CR3A = vga_in8(0x3d5, par); in savage_get_default_par()
590 reg->CR40 = vga_in8(0x3d5, par); in savage_get_default_par()
592 reg->CR42 = vga_in8(0x3d5, par); in savage_get_default_par()
594 reg->CR45 = vga_in8(0x3d5, par); in savage_get_default_par()
596 reg->CR50 = vga_in8(0x3d5, par); in savage_get_default_par()
598 reg->CR51 = vga_in8(0x3d5, par); in savage_get_default_par()
600 reg->CR53 = vga_in8(0x3d5, par); in savage_get_default_par()
602 reg->CR58 = vga_in8(0x3d5, par); in savage_get_default_par()
604 reg->CR60 = vga_in8(0x3d5, par); in savage_get_default_par()
606 reg->CR66 = vga_in8(0x3d5, par); in savage_get_default_par()
608 reg->CR67 = vga_in8(0x3d5, par); in savage_get_default_par()
610 reg->CR68 = vga_in8(0x3d5, par); in savage_get_default_par()
612 reg->CR69 = vga_in8(0x3d5, par); in savage_get_default_par()
614 reg->CR6F = vga_in8(0x3d5, par); in savage_get_default_par()
617 reg->CR33 = vga_in8(0x3d5, par); in savage_get_default_par()
619 reg->CR86 = vga_in8(0x3d5, par); in savage_get_default_par()
621 reg->CR88 = vga_in8(0x3d5, par); in savage_get_default_par()
623 reg->CR90 = vga_in8(0x3d5, par); in savage_get_default_par()
625 reg->CR91 = vga_in8(0x3d5, par); in savage_get_default_par()
627 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; in savage_get_default_par()
631 reg->CR3B = vga_in8(0x3d5, par); in savage_get_default_par()
633 reg->CR3C = vga_in8(0x3d5, par); in savage_get_default_par()
635 reg->CR43 = vga_in8(0x3d5, par); in savage_get_default_par()
637 reg->CR5D = vga_in8(0x3d5, par); in savage_get_default_par()
639 reg->CR5E = vga_in8(0x3d5, par); in savage_get_default_par()
641 reg->CR65 = vga_in8(0x3d5, par); in savage_get_default_par()
645 reg->SR0E = vga_in8(0x3c5, par); in savage_get_default_par()
647 reg->SR0F = vga_in8(0x3c5, par); in savage_get_default_par()
649 reg->SR10 = vga_in8(0x3c5, par); in savage_get_default_par()
651 reg->SR11 = vga_in8(0x3c5, par); in savage_get_default_par()
653 reg->SR12 = vga_in8(0x3c5, par); in savage_get_default_par()
655 reg->SR13 = vga_in8(0x3c5, par); in savage_get_default_par()
657 reg->SR29 = vga_in8(0x3c5, par); in savage_get_default_par()
660 reg->SR15 = vga_in8(0x3c5, par); in savage_get_default_par()
662 reg->SR30 = vga_in8(0x3c5, par); in savage_get_default_par()
664 reg->SR18 = vga_in8(0x3c5, par); in savage_get_default_par()
667 if (par->chip == S3_SAVAGE_MX) { in savage_get_default_par()
672 reg->SR54[i] = vga_in8(0x3c5, par); in savage_get_default_par()
684 if (par->chip != S3_SAVAGE_MX) { in savage_get_default_par()
685 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); in savage_get_default_par()
686 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); in savage_get_default_par()
687 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); in savage_get_default_par()
688 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); in savage_get_default_par()
728 vga_out8(0x3c5, reg->SR08, par); in savage_set_default_par()
733 vga_out8(0x3d5, reg->CR31, par); in savage_set_default_par()
735 vga_out8(0x3d5, reg->CR32, par); in savage_set_default_par()
737 vga_out8(0x3d5, reg->CR34, par); in savage_set_default_par()
739 vga_out8(0x3d5,reg->CR36, par); in savage_set_default_par()
741 vga_out8(0x3d5, reg->CR3A, par); in savage_set_default_par()
743 vga_out8(0x3d5, reg->CR40, par); in savage_set_default_par()
745 vga_out8(0x3d5, reg->CR42, par); in savage_set_default_par()
747 vga_out8(0x3d5, reg->CR45, par); in savage_set_default_par()
749 vga_out8(0x3d5, reg->CR50, par); in savage_set_default_par()
751 vga_out8(0x3d5, reg->CR51, par); in savage_set_default_par()
753 vga_out8(0x3d5, reg->CR53, par); in savage_set_default_par()
755 vga_out8(0x3d5, reg->CR58, par); in savage_set_default_par()
757 vga_out8(0x3d5, reg->CR60, par); in savage_set_default_par()
759 vga_out8(0x3d5, reg->CR66, par); in savage_set_default_par()
761 vga_out8(0x3d5, reg->CR67, par); in savage_set_default_par()
763 vga_out8(0x3d5, reg->CR68, par); in savage_set_default_par()
765 vga_out8(0x3d5, reg->CR69, par); in savage_set_default_par()
767 vga_out8(0x3d5, reg->CR6F, par); in savage_set_default_par()
770 vga_out8(0x3d5, reg->CR33, par); in savage_set_default_par()
772 vga_out8(0x3d5, reg->CR86, par); in savage_set_default_par()
774 vga_out8(0x3d5, reg->CR88, par); in savage_set_default_par()
776 vga_out8(0x3d5, reg->CR90, par); in savage_set_default_par()
778 vga_out8(0x3d5, reg->CR91, par); in savage_set_default_par()
780 vga_out8(0x3d5, reg->CRB0, par); in savage_set_default_par()
784 vga_out8(0x3d5, reg->CR3B, par); in savage_set_default_par()
786 vga_out8(0x3d5, reg->CR3C, par); in savage_set_default_par()
788 vga_out8(0x3d5, reg->CR43, par); in savage_set_default_par()
790 vga_out8(0x3d5, reg->CR5D, par); in savage_set_default_par()
792 vga_out8(0x3d5, reg->CR5E, par); in savage_set_default_par()
794 vga_out8(0x3d5, reg->CR65, par); in savage_set_default_par()
798 vga_out8(0x3c5, reg->SR0E, par); in savage_set_default_par()
800 vga_out8(0x3c5, reg->SR0F, par); in savage_set_default_par()
802 vga_out8(0x3c5, reg->SR10, par); in savage_set_default_par()
804 vga_out8(0x3c5, reg->SR11, par); in savage_set_default_par()
806 vga_out8(0x3c5, reg->SR12, par); in savage_set_default_par()
808 vga_out8(0x3c5, reg->SR13, par); in savage_set_default_par()
810 vga_out8(0x3c5, reg->SR29, par); in savage_set_default_par()
813 vga_out8(0x3c5, reg->SR15, par); in savage_set_default_par()
815 vga_out8(0x3c5, reg->SR30, par); in savage_set_default_par()
817 vga_out8(0x3c5, reg->SR18, par); in savage_set_default_par()
820 if (par->chip == S3_SAVAGE_MX) { in savage_set_default_par()
825 vga_out8(0x3c5, reg->SR54[i], par); in savage_set_default_par()
837 if (par->chip != S3_SAVAGE_MX) { in savage_set_default_par()
838 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); in savage_set_default_par()
839 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); in savage_set_default_par()
840 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); in savage_set_default_par()
841 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); in savage_set_default_par()
853 var->xres = var->xres_virtual = modedb->xres; in savage_update_var()
854 var->yres = modedb->yres; in savage_update_var()
855 if (var->yres_virtual < var->yres) in savage_update_var()
856 var->yres_virtual = var->yres; in savage_update_var()
857 var->xoffset = var->yoffset = 0; in savage_update_var()
858 var->pixclock = modedb->pixclock; in savage_update_var()
859 var->left_margin = modedb->left_margin; in savage_update_var()
860 var->right_margin = modedb->right_margin; in savage_update_var()
861 var->upper_margin = modedb->upper_margin; in savage_update_var()
862 var->lower_margin = modedb->lower_margin; in savage_update_var()
863 var->hsync_len = modedb->hsync_len; in savage_update_var()
864 var->vsync_len = modedb->vsync_len; in savage_update_var()
865 var->sync = modedb->sync; in savage_update_var()
866 var->vmode = modedb->vmode; in savage_update_var()
872 struct savagefb_par *par = info->par; in savagefb_check_var()
877 var->transp.offset = 0; in savagefb_check_var()
878 var->transp.length = 0; in savagefb_check_var()
879 switch (var->bits_per_pixel) { in savagefb_check_var()
881 var->red.offset = var->green.offset = in savagefb_check_var()
882 var->blue.offset = 0; in savagefb_check_var()
883 var->red.length = var->green.length = in savagefb_check_var()
884 var->blue.length = var->bits_per_pixel; in savagefb_check_var()
887 var->red.offset = 11; in savagefb_check_var()
888 var->red.length = 5; in savagefb_check_var()
889 var->green.offset = 5; in savagefb_check_var()
890 var->green.length = 6; in savagefb_check_var()
891 var->blue.offset = 0; in savagefb_check_var()
892 var->blue.length = 5; in savagefb_check_var()
895 var->transp.offset = 24; in savagefb_check_var()
896 var->transp.length = 8; in savagefb_check_var()
897 var->red.offset = 16; in savagefb_check_var()
898 var->red.length = 8; in savagefb_check_var()
899 var->green.offset = 8; in savagefb_check_var()
900 var->green.length = 8; in savagefb_check_var()
901 var->blue.offset = 0; in savagefb_check_var()
902 var->blue.length = 8; in savagefb_check_var()
906 return -EINVAL; in savagefb_check_var()
909 if (!info->monspecs.hfmax || !info->monspecs.vfmax || in savagefb_check_var()
910 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) in savagefb_check_var()
914 if (!mode_valid && info->monspecs.gtf) { in savagefb_check_var()
922 mode = fb_find_best_mode(var, &info->modelist); in savagefb_check_var()
929 if (!mode_valid && info->monspecs.modedb_len) in savagefb_check_var()
930 return -EINVAL; in savagefb_check_var()
933 if (par->SavagePanelWidth && in savagefb_check_var()
934 (var->xres > par->SavagePanelWidth || in savagefb_check_var()
935 var->yres > par->SavagePanelHeight)) { in savagefb_check_var()
937 "(%dx%d)\n", var->xres, var->yres, in savagefb_check_var()
938 par->SavagePanelWidth, in savagefb_check_var()
939 par->SavagePanelHeight); in savagefb_check_var()
940 return -1; in savagefb_check_var()
943 if (var->yres_virtual < var->yres) in savagefb_check_var()
944 var->yres_virtual = var->yres; in savagefb_check_var()
945 if (var->xres_virtual < var->xres) in savagefb_check_var()
946 var->xres_virtual = var->xres; in savagefb_check_var()
948 vramlen = info->fix.smem_len; in savagefb_check_var()
950 memlen = var->xres_virtual * var->bits_per_pixel * in savagefb_check_var()
951 var->yres_virtual / 8; in savagefb_check_var()
953 var->yres_virtual = vramlen * 8 / in savagefb_check_var()
954 (var->xres_virtual * var->bits_per_pixel); in savagefb_check_var()
955 memlen = var->xres_virtual * var->bits_per_pixel * in savagefb_check_var()
956 var->yres_virtual / 8; in savagefb_check_var()
960 if it was possible. We should return -EINVAL, but I disagree */ in savagefb_check_var()
961 if (var->yres_virtual < var->yres) in savagefb_check_var()
962 var->yres = var->yres_virtual; in savagefb_check_var()
963 if (var->xres_virtual < var->xres) in savagefb_check_var()
964 var->xres = var->xres_virtual; in savagefb_check_var()
965 if (var->xoffset + var->xres > var->xres_virtual) in savagefb_check_var()
966 var->xoffset = var->xres_virtual - var->xres; in savagefb_check_var()
967 if (var->yoffset + var->yres > var->yres_virtual) in savagefb_check_var()
968 var->yoffset = var->yres_virtual - var->yres; in savagefb_check_var()
982 unsigned int pixclock = var->pixclock; in savagefb_decode_var()
991 timings.dblscan = var->vmode & FB_VMODE_DOUBLE; in savagefb_decode_var()
992 timings.interlaced = var->vmode & FB_VMODE_INTERLACED; in savagefb_decode_var()
993 timings.HDisplay = var->xres; in savagefb_decode_var()
994 timings.HSyncStart = timings.HDisplay + var->right_margin; in savagefb_decode_var()
995 timings.HSyncEnd = timings.HSyncStart + var->hsync_len; in savagefb_decode_var()
996 timings.HTotal = timings.HSyncEnd + var->left_margin; in savagefb_decode_var()
997 timings.VDisplay = var->yres; in savagefb_decode_var()
998 timings.VSyncStart = timings.VDisplay + var->lower_margin; in savagefb_decode_var()
999 timings.VSyncEnd = timings.VSyncStart + var->vsync_len; in savagefb_decode_var()
1000 timings.VTotal = timings.VSyncEnd + var->upper_margin; in savagefb_decode_var()
1001 timings.sync = var->sync; in savagefb_decode_var()
1004 par->depth = var->bits_per_pixel; in savagefb_decode_var()
1005 par->vwidth = var->xres_virtual; in savagefb_decode_var()
1007 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) { in savagefb_decode_var()
1023 reg->CR67 = 0x00; in savagefb_decode_var()
1025 switch(var->bits_per_pixel) { in savagefb_decode_var()
1027 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) in savagefb_decode_var()
1028 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ in savagefb_decode_var()
1030 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ in savagefb_decode_var()
1033 if (S3_SAVAGE_MOBILE_SERIES(par->chip) || in savagefb_decode_var()
1034 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1035 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ in savagefb_decode_var()
1037 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ in savagefb_decode_var()
1040 if (S3_SAVAGE_MOBILE_SERIES(par->chip) || in savagefb_decode_var()
1041 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1042 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ in savagefb_decode_var()
1044 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ in savagefb_decode_var()
1047 reg->CR67 = 0x70; in savagefb_decode_var()
1050 reg->CR67 = 0xd0; in savagefb_decode_var()
1056 * match. Fall back to traditional register-crunching. in savagefb_decode_var()
1061 if (1 /*FIXME:psav->pci_burst*/) in savagefb_decode_var()
1062 reg->CR3A = (tmp & 0x7f) | 0x15; in savagefb_decode_var()
1064 reg->CR3A = tmp | 0x95; in savagefb_decode_var()
1066 reg->CR53 = 0x00; in savagefb_decode_var()
1067 reg->CR31 = 0x8c; in savagefb_decode_var()
1068 reg->CR66 = 0x89; in savagefb_decode_var()
1071 reg->CR58 = vga_in8(0x3d5, par) & 0x80; in savagefb_decode_var()
1072 reg->CR58 |= 0x13; in savagefb_decode_var()
1074 reg->SR15 = 0x03 | 0x80; in savagefb_decode_var()
1075 reg->SR18 = 0x00; in savagefb_decode_var()
1076 reg->CR43 = reg->CR45 = reg->CR65 = 0x00; in savagefb_decode_var()
1079 reg->CR40 = vga_in8(0x3d5, par) & ~0x01; in savagefb_decode_var()
1081 reg->MMPR0 = 0x010400; in savagefb_decode_var()
1082 reg->MMPR1 = 0x00; in savagefb_decode_var()
1083 reg->MMPR2 = 0x0808; in savagefb_decode_var()
1084 reg->MMPR3 = 0x08080810; in savagefb_decode_var()
1089 if (par->MCLK <= 0) { in savagefb_decode_var()
1090 reg->SR10 = 255; in savagefb_decode_var()
1091 reg->SR11 = 255; in savagefb_decode_var()
1093 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, in savagefb_decode_var()
1094 ®->SR11, ®->SR10); in savagefb_decode_var()
1095 /* reg->SR10 = 80; // MCLK == 286000 */ in savagefb_decode_var()
1096 /* reg->SR11 = 125; */ in savagefb_decode_var()
1099 reg->SR12 = (r << 6) | (n & 0x3f); in savagefb_decode_var()
1100 reg->SR13 = m & 0xff; in savagefb_decode_var()
1101 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; in savagefb_decode_var()
1103 if (var->bits_per_pixel < 24) in savagefb_decode_var()
1104 reg->MMPR0 -= 0x8000; in savagefb_decode_var()
1106 reg->MMPR0 -= 0x4000; in savagefb_decode_var()
1109 reg->CR42 = 0x20; in savagefb_decode_var()
1111 reg->CR42 = 0x00; in savagefb_decode_var()
1113 reg->CR34 = 0x10; /* display fifo */ in savagefb_decode_var()
1115 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) | in savagefb_decode_var()
1116 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) | in savagefb_decode_var()
1117 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) | in savagefb_decode_var()
1120 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64) in savagefb_decode_var()
1122 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32) in savagefb_decode_var()
1125 j = (reg->CRTC[0] + ((i & 0x01) << 8) + in savagefb_decode_var()
1126 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; in savagefb_decode_var()
1128 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { in savagefb_decode_var()
1129 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= in savagefb_decode_var()
1130 reg->CRTC[0] + ((i & 0x01) << 8)) in savagefb_decode_var()
1131 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; in savagefb_decode_var()
1133 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; in savagefb_decode_var()
1136 reg->CR3B = j & 0xff; in savagefb_decode_var()
1138 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; in savagefb_decode_var()
1139 reg->CR5D = i; in savagefb_decode_var()
1140 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | in savagefb_decode_var()
1141 (((timings.VDisplay - 1) & 0x400) >> 9) | in savagefb_decode_var()
1144 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3; in savagefb_decode_var()
1145 reg->CR91 = reg->CRTC[19] = 0xff & width; in savagefb_decode_var()
1146 reg->CR51 = (0x300 & width) >> 4; in savagefb_decode_var()
1147 reg->CR90 = 0x80 | (width >> 8); in savagefb_decode_var()
1148 reg->MiscOutReg |= 0x0c; in savagefb_decode_var()
1152 if (var->bits_per_pixel <= 8) in savagefb_decode_var()
1153 reg->CR50 = 0; in savagefb_decode_var()
1154 else if (var->bits_per_pixel <= 16) in savagefb_decode_var()
1155 reg->CR50 = 0x10; in savagefb_decode_var()
1157 reg->CR50 = 0x30; in savagefb_decode_var()
1159 if (var->xres_virtual <= 640) in savagefb_decode_var()
1160 reg->CR50 |= 0x40; in savagefb_decode_var()
1161 else if (var->xres_virtual == 800) in savagefb_decode_var()
1162 reg->CR50 |= 0x80; in savagefb_decode_var()
1163 else if (var->xres_virtual == 1024) in savagefb_decode_var()
1164 reg->CR50 |= 0x00; in savagefb_decode_var()
1165 else if (var->xres_virtual == 1152) in savagefb_decode_var()
1166 reg->CR50 |= 0x01; in savagefb_decode_var()
1167 else if (var->xres_virtual == 1280) in savagefb_decode_var()
1168 reg->CR50 |= 0xc0; in savagefb_decode_var()
1169 else if (var->xres_virtual == 1600) in savagefb_decode_var()
1170 reg->CR50 |= 0x81; in savagefb_decode_var()
1172 reg->CR50 |= 0xc1; /* Use GBD */ in savagefb_decode_var()
1174 if (par->chip == S3_SAVAGE2000) in savagefb_decode_var()
1175 reg->CR33 = 0x08; in savagefb_decode_var()
1177 reg->CR33 = 0x20; in savagefb_decode_var()
1179 reg->CRTC[0x17] = 0xeb; in savagefb_decode_var()
1181 reg->CR67 |= 1; in savagefb_decode_var()
1184 reg->CR36 = vga_in8(0x3d5, par); in savagefb_decode_var()
1186 reg->CR68 = vga_in8(0x3d5, par); in savagefb_decode_var()
1187 reg->CR69 = 0; in savagefb_decode_var()
1189 reg->CR6F = vga_in8(0x3d5, par); in savagefb_decode_var()
1191 reg->CR86 = vga_in8(0x3d5, par); in savagefb_decode_var()
1193 reg->CR88 = vga_in8(0x3d5, par) | 0x08; in savagefb_decode_var()
1195 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; in savagefb_decode_var()
1200 /* --------------------------------------------------------------------- */
1212 struct savagefb_par *par = info->par; in savagefb_setcolreg()
1215 return -EINVAL; in savagefb_setcolreg()
1217 par->palette[regno].red = red; in savagefb_setcolreg()
1218 par->palette[regno].green = green; in savagefb_setcolreg()
1219 par->palette[regno].blue = blue; in savagefb_setcolreg()
1220 par->palette[regno].transp = transp; in savagefb_setcolreg()
1222 switch (info->var.bits_per_pixel) { in savagefb_setcolreg()
1233 ((u32 *)info->pseudo_palette)[regno] = in savagefb_setcolreg()
1241 ((u32 *)info->pseudo_palette)[regno] = in savagefb_setcolreg()
1248 ((u32 *)info->pseudo_palette)[regno] = in savagefb_setcolreg()
1268 par->SavageWaitIdle(par); in savagefb_set_par_int()
1281 * haven't been able to find what causes it, but a non-destructive in savagefb_set_par_int()
1288 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */ in savagefb_set_par_int()
1297 vga_out8(0x3d5, reg->CR66, par); in savagefb_set_par_int()
1299 vga_out8(0x3d5, reg->CR3A, par); in savagefb_set_par_int()
1301 vga_out8(0x3d5, reg->CR31, par); in savagefb_set_par_int()
1303 vga_out8(0x3d5, reg->CR32, par); in savagefb_set_par_int()
1305 vga_out8(0x3d5, reg->CR58, par); in savagefb_set_par_int()
1307 vga_out8(0x3d5, reg->CR53 & 0x7f, par); in savagefb_set_par_int()
1314 vga_out8(0x3c5, reg->SR0E, par); in savagefb_set_par_int()
1316 vga_out8(0x3c5, reg->SR0F, par); in savagefb_set_par_int()
1318 vga_out8(0x3c5, reg->SR29, par); in savagefb_set_par_int()
1320 vga_out8(0x3c5, reg->SR15, par); in savagefb_set_par_int()
1323 if (par->chip == S3_SAVAGE_MX) { in savagefb_set_par_int()
1328 vga_out8(0x3c5, reg->SR54[i], par); in savagefb_set_par_int()
1336 vga_out8(0x3d5, reg->CR53, par); in savagefb_set_par_int()
1338 vga_out8(0x3d5, reg->CR5D, par); in savagefb_set_par_int()
1340 vga_out8(0x3d5, reg->CR5E, par); in savagefb_set_par_int()
1342 vga_out8(0x3d5, reg->CR3B, par); in savagefb_set_par_int()
1344 vga_out8(0x3d5, reg->CR3C, par); in savagefb_set_par_int()
1346 vga_out8(0x3d5, reg->CR43, par); in savagefb_set_par_int()
1348 vga_out8(0x3d5, reg->CR65, par); in savagefb_set_par_int()
1358 vga_out8(0x3d5, reg->CR67 & ~0x0c, par); in savagefb_set_par_int()
1362 vga_out8(0x3d5, reg->CR34, par); in savagefb_set_par_int()
1364 vga_out8(0x3d5, reg->CR40, par); in savagefb_set_par_int()
1366 vga_out8(0x3d5, reg->CR42, par); in savagefb_set_par_int()
1368 vga_out8(0x3d5, reg->CR45, par); in savagefb_set_par_int()
1370 vga_out8(0x3d5, reg->CR50, par); in savagefb_set_par_int()
1372 vga_out8(0x3d5, reg->CR51, par); in savagefb_set_par_int()
1376 vga_out8(0x3d5, reg->CR36, par); in savagefb_set_par_int()
1378 vga_out8(0x3d5, reg->CR60, par); in savagefb_set_par_int()
1380 vga_out8(0x3d5, reg->CR68, par); in savagefb_set_par_int()
1382 vga_out8(0x3d5, reg->CR69, par); in savagefb_set_par_int()
1384 vga_out8(0x3d5, reg->CR6F, par); in savagefb_set_par_int()
1387 vga_out8(0x3d5, reg->CR33, par); in savagefb_set_par_int()
1389 vga_out8(0x3d5, reg->CR86, par); in savagefb_set_par_int()
1391 vga_out8(0x3d5, reg->CR88, par); in savagefb_set_par_int()
1393 vga_out8(0x3d5, reg->CR90, par); in savagefb_set_par_int()
1395 vga_out8(0x3d5, reg->CR91, par); in savagefb_set_par_int()
1397 if (par->chip == S3_SAVAGE4) { in savagefb_set_par_int()
1399 vga_out8(0x3d5, reg->CRB0, par); in savagefb_set_par_int()
1403 vga_out8(0x3d5, reg->CR32, par); in savagefb_set_par_int()
1412 if (reg->SR10 != 255) { in savagefb_set_par_int()
1414 vga_out8(0x3c5, reg->SR10, par); in savagefb_set_par_int()
1416 vga_out8(0x3c5, reg->SR11, par); in savagefb_set_par_int()
1421 vga_out8(0x3c5, reg->SR0E, par); in savagefb_set_par_int()
1423 vga_out8(0x3c5, reg->SR0F, par); in savagefb_set_par_int()
1425 vga_out8(0x3c5, reg->SR12, par); in savagefb_set_par_int()
1427 vga_out8(0x3c5, reg->SR13, par); in savagefb_set_par_int()
1429 vga_out8(0x3c5, reg->SR29, par); in savagefb_set_par_int()
1431 vga_out8(0x3c5, reg->SR18, par); in savagefb_set_par_int()
1440 vga_out8(0x3c5, reg->SR15, par); in savagefb_set_par_int()
1444 vga_out8(0x3c5, reg->SR30, par); in savagefb_set_par_int()
1446 vga_out8(0x3c5, reg->SR08, par); in savagefb_set_par_int()
1451 vga_out8(0x3d5, reg->CR67, par); in savagefb_set_par_int()
1460 if (par->chip != S3_SAVAGE_MX) { in savagefb_set_par_int()
1462 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); in savagefb_set_par_int()
1463 par->SavageWaitIdle(par); in savagefb_set_par_int()
1464 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); in savagefb_set_par_int()
1465 par->SavageWaitIdle(par); in savagefb_set_par_int()
1466 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); in savagefb_set_par_int()
1467 par->SavageWaitIdle(par); in savagefb_set_par_int()
1468 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); in savagefb_set_par_int()
1492 info->fix.line_length = info->var.xres_virtual * in savagefb_set_fix()
1493 info->var.bits_per_pixel / 8; in savagefb_set_fix()
1495 if (info->var.bits_per_pixel == 8) { in savagefb_set_fix()
1496 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in savagefb_set_fix()
1497 info->fix.xpanstep = 4; in savagefb_set_fix()
1499 info->fix.visual = FB_VISUAL_TRUECOLOR; in savagefb_set_fix()
1500 info->fix.xpanstep = 2; in savagefb_set_fix()
1507 struct savagefb_par *par = info->par; in savagefb_set_par()
1508 struct fb_var_screeninfo *var = &info->var; in savagefb_set_par()
1512 err = savagefb_decode_var(var, par, &par->state); in savagefb_set_par()
1516 if (par->dacSpeedBpp <= 0) { in savagefb_set_par()
1517 if (var->bits_per_pixel > 24) in savagefb_set_par()
1518 par->dacSpeedBpp = par->clock[3]; in savagefb_set_par()
1519 else if (var->bits_per_pixel >= 24) in savagefb_set_par()
1520 par->dacSpeedBpp = par->clock[2]; in savagefb_set_par()
1521 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24)) in savagefb_set_par()
1522 par->dacSpeedBpp = par->clock[1]; in savagefb_set_par()
1523 else if (var->bits_per_pixel <= 8) in savagefb_set_par()
1524 par->dacSpeedBpp = par->clock[0]; in savagefb_set_par()
1528 par->maxClock = par->dacSpeedBpp; in savagefb_set_par()
1529 par->minClock = 10000; in savagefb_set_par()
1531 savagefb_set_par_int(par, &par->state); in savagefb_set_par()
1532 fb_set_cmap(&info->cmap, info); in savagefb_set_par()
1546 struct savagefb_par *par = info->par; in savagefb_pan_display()
1549 base = (var->yoffset * info->fix.line_length in savagefb_pan_display()
1550 + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2; in savagefb_pan_display()
1558 struct savagefb_par *par = info->par; in savagefb_blank()
1561 if (par->display_type == DISP_CRT) { in savagefb_blank()
1589 if (par->display_type == DISP_LCD || in savagefb_blank()
1590 par->display_type == DISP_DFP) { in savagefb_blank()
1594 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ in savagefb_blank()
1600 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ in savagefb_blank()
1611 struct savagefb_par *par = info->par; in savagefb_open()
1613 mutex_lock(&par->open_lock); in savagefb_open()
1615 if (!par->open_count) { in savagefb_open()
1616 memset(&par->vgastate, 0, sizeof(par->vgastate)); in savagefb_open()
1617 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS | in savagefb_open()
1619 par->vgastate.vgabase = par->mmio.vbase + 0x8000; in savagefb_open()
1620 save_vga(&par->vgastate); in savagefb_open()
1621 savage_get_default_par(par, &par->initial); in savagefb_open()
1624 par->open_count++; in savagefb_open()
1625 mutex_unlock(&par->open_lock); in savagefb_open()
1631 struct savagefb_par *par = info->par; in savagefb_release()
1633 mutex_lock(&par->open_lock); in savagefb_release()
1635 if (par->open_count == 1) { in savagefb_release()
1636 savage_set_default_par(par, &par->initial); in savagefb_release()
1637 restore_vga(&par->vgastate); in savagefb_release()
1640 par->open_count--; in savagefb_release()
1641 mutex_unlock(&par->open_lock); in savagefb_release()
1666 /* --------------------------------------------------------------------- */
1697 if (par->chip >= S3_SAVAGE4) { in savage_enable_mmio()
1711 if (par->chip >= S3_SAVAGE4) { in savage_disable_mmio()
1721 struct savagefb_par *par = info->par; in savage_map_mmio()
1724 if (S3_SAVAGE3D_SERIES(par->chip)) in savage_map_mmio()
1725 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + in savage_map_mmio()
1728 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + in savage_map_mmio()
1731 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE; in savage_map_mmio()
1733 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len); in savage_map_mmio()
1734 if (!par->mmio.vbase) { in savage_map_mmio()
1736 return -ENOMEM; in savage_map_mmio()
1739 par->mmio.vbase); in savage_map_mmio()
1741 info->fix.mmio_start = par->mmio.pbase; in savage_map_mmio()
1742 info->fix.mmio_len = par->mmio.len; in savage_map_mmio()
1744 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET); in savage_map_mmio()
1745 par->bci_ptr = 0; in savage_map_mmio()
1754 struct savagefb_par *par = info->par; in savage_unmap_mmio()
1759 if (par->mmio.vbase) { in savage_unmap_mmio()
1760 iounmap(par->mmio.vbase); in savage_unmap_mmio()
1761 par->mmio.vbase = NULL; in savage_unmap_mmio()
1768 struct savagefb_par *par = info->par; in savage_map_video()
1773 if (S3_SAVAGE3D_SERIES(par->chip)) in savage_map_video()
1778 par->video.pbase = pci_resource_start(par->pcidev, resource); in savage_map_video()
1779 par->video.len = video_len; in savage_map_video()
1780 par->video.vbase = ioremap(par->video.pbase, par->video.len); in savage_map_video()
1782 if (!par->video.vbase) { in savage_map_video()
1784 return -ENOMEM; in savage_map_video()
1787 "pbase == %x\n", par->video.vbase, par->video.pbase); in savage_map_video()
1789 info->fix.smem_start = par->video.pbase; in savage_map_video()
1790 info->fix.smem_len = par->video.len - par->cob_size; in savage_map_video()
1791 info->screen_base = par->video.vbase; in savage_map_video()
1794 par->video.mtrr = mtrr_add(par->video.pbase, video_len, in savage_map_video()
1799 memset_io(par->video.vbase, 0, par->video.len); in savage_map_video()
1806 struct savagefb_par *par = info->par; in savage_unmap_video()
1810 if (par->video.vbase) { in savage_unmap_video()
1812 mtrr_del(par->video.mtrr, par->video.pbase, par->video.len); in savage_unmap_video()
1815 iounmap(par->video.vbase); in savage_unmap_video()
1816 par->video.vbase = NULL; in savage_unmap_video()
1817 info->screen_base = NULL; in savage_unmap_video()
1833 /* unprotect CRTC[0-7] */ in savage_init_hw()
1861 switch (par->chip) { in savage_init_hw()
1929 par->numClocks = 4; in savage_init_hw()
1930 par->clock[0] = 250000; in savage_init_hw()
1931 par->clock[1] = 250000; in savage_init_hw()
1932 par->clock[2] = 220000; in savage_init_hw()
1933 par->clock[3] = 220000; in savage_init_hw()
1948 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; in savage_init_hw()
1950 par->MCLK); in savage_init_hw()
1955 if (par->chip == S3_SAVAGE4) { in savage_init_hw()
1968 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) || in savage_init_hw()
1969 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly) in savage_init_hw()
1970 par->display_type = DISP_LCD; in savage_init_hw()
1971 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi)) in savage_init_hw()
1972 par->display_type = DISP_DFP; in savage_init_hw()
1974 par->display_type = DISP_CRT; in savage_init_hw()
1978 if (par->display_type == DISP_LCD) { in savage_init_hw()
1988 /* OK, I admit it. I don't know how to limit the max dot clock in savage_init_hw()
2027 par->SavagePanelWidth = panelX; in savage_init_hw()
2028 par->SavagePanelHeight = panelY; in savage_init_hw()
2031 par->display_type = DISP_CRT; in savage_init_hw()
2034 savage_get_default_par(par, &par->state); in savage_init_hw()
2035 par->save = par->state; in savage_init_hw()
2037 if (S3_SAVAGE4_SERIES(par->chip)) { in savage_init_hw()
2040 * render the buffer useless. We disable it. in savage_init_hw()
2042 par->cob_index = 2; in savage_init_hw()
2043 par->cob_size = 0x8000 << par->cob_index; in savage_init_hw()
2044 par->cob_offset = videoRambytes; in savage_init_hw()
2048 par->cob_index = 7; in savage_init_hw()
2049 par->cob_size = 0x400 << par->cob_index; in savage_init_hw()
2050 par->cob_offset = videoRambytes - par->cob_size; in savage_init_hw()
2060 struct savagefb_par *par = info->par; in savage_init_fb_info()
2063 par->pcidev = dev; in savage_init_fb_info()
2065 info->fix.type = FB_TYPE_PACKED_PIXELS; in savage_init_fb_info()
2066 info->fix.type_aux = 0; in savage_init_fb_info()
2067 info->fix.ypanstep = 1; in savage_init_fb_info()
2068 info->fix.ywrapstep = 0; in savage_init_fb_info()
2069 info->fix.accel = id->driver_data; in savage_init_fb_info()
2071 switch (info->fix.accel) { in savage_init_fb_info()
2073 par->chip = S3_SUPERSAVAGE; in savage_init_fb_info()
2074 snprintf(info->fix.id, 16, "SuperSavage"); in savage_init_fb_info()
2077 par->chip = S3_SAVAGE4; in savage_init_fb_info()
2078 snprintf(info->fix.id, 16, "Savage4"); in savage_init_fb_info()
2081 par->chip = S3_SAVAGE3D; in savage_init_fb_info()
2082 snprintf(info->fix.id, 16, "Savage3D"); in savage_init_fb_info()
2085 par->chip = S3_SAVAGE3D; in savage_init_fb_info()
2086 snprintf(info->fix.id, 16, "Savage3D-MV"); in savage_init_fb_info()
2089 par->chip = S3_SAVAGE2000; in savage_init_fb_info()
2090 snprintf(info->fix.id, 16, "Savage2000"); in savage_init_fb_info()
2093 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2094 snprintf(info->fix.id, 16, "Savage/MX-MV"); in savage_init_fb_info()
2097 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2098 snprintf(info->fix.id, 16, "Savage/MX"); in savage_init_fb_info()
2101 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2102 snprintf(info->fix.id, 16, "Savage/IX-MV"); in savage_init_fb_info()
2105 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2106 snprintf(info->fix.id, 16, "Savage/IX"); in savage_init_fb_info()
2109 par->chip = S3_PROSAVAGE; in savage_init_fb_info()
2110 snprintf(info->fix.id, 16, "ProSavagePM"); in savage_init_fb_info()
2113 par->chip = S3_PROSAVAGE; in savage_init_fb_info()
2114 snprintf(info->fix.id, 16, "ProSavageKM"); in savage_init_fb_info()
2117 par->chip = S3_TWISTER; in savage_init_fb_info()
2118 snprintf(info->fix.id, 16, "TwisterP"); in savage_init_fb_info()
2121 par->chip = S3_TWISTER; in savage_init_fb_info()
2122 snprintf(info->fix.id, 16, "TwisterK"); in savage_init_fb_info()
2125 par->chip = S3_PROSAVAGEDDR; in savage_init_fb_info()
2126 snprintf(info->fix.id, 16, "ProSavageDDR"); in savage_init_fb_info()
2129 par->chip = S3_PROSAVAGEDDR; in savage_init_fb_info()
2130 snprintf(info->fix.id, 16, "ProSavage8"); in savage_init_fb_info()
2134 if (S3_SAVAGE3D_SERIES(par->chip)) { in savage_init_fb_info()
2135 par->SavageWaitIdle = savage3D_waitidle; in savage_init_fb_info()
2136 par->SavageWaitFifo = savage3D_waitfifo; in savage_init_fb_info()
2137 } else if (S3_SAVAGE4_SERIES(par->chip) || in savage_init_fb_info()
2138 S3_SUPERSAVAGE == par->chip) { in savage_init_fb_info()
2139 par->SavageWaitIdle = savage4_waitidle; in savage_init_fb_info()
2140 par->SavageWaitFifo = savage4_waitfifo; in savage_init_fb_info()
2142 par->SavageWaitIdle = savage2000_waitidle; in savage_init_fb_info()
2143 par->SavageWaitFifo = savage2000_waitfifo; in savage_init_fb_info()
2146 info->var.nonstd = 0; in savage_init_fb_info()
2147 info->var.activate = FB_ACTIVATE_NOW; in savage_init_fb_info()
2148 info->var.width = -1; in savage_init_fb_info()
2149 info->var.height = -1; in savage_init_fb_info()
2150 info->var.accel_flags = 0; in savage_init_fb_info()
2152 info->fbops = &savagefb_ops; in savage_init_fb_info()
2153 info->flags = FBINFO_DEFAULT | in savage_init_fb_info()
2157 info->pseudo_palette = par->pseudo_palette; in savage_init_fb_info()
2161 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL); in savage_init_fb_info()
2163 err = -ENOMEM; in savage_init_fb_info()
2164 if (info->pixmap.addr) { in savage_init_fb_info()
2165 info->pixmap.size = 8*1024; in savage_init_fb_info()
2166 info->pixmap.scan_align = 4; in savage_init_fb_info()
2167 info->pixmap.buf_align = 4; in savage_init_fb_info()
2168 info->pixmap.access_align = 32; in savage_init_fb_info()
2170 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0); in savage_init_fb_info()
2172 info->flags |= FBINFO_HWACCEL_COPYAREA | in savage_init_fb_info()
2180 /* --------------------------------------------------------------------- */
2193 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev); in savagefb_probe()
2195 return -ENOMEM; in savagefb_probe()
2196 par = info->par; in savagefb_probe()
2197 mutex_init(&par->open_lock); in savagefb_probe()
2207 err = -ENOMEM; in savagefb_probe()
2227 INIT_LIST_HEAD(&info->modelist); in savagefb_probe()
2230 savagefb_probe_i2c_connector(info, &par->edid); in savagefb_probe()
2231 fb_edid_to_monspecs(par->edid, &info->monspecs); in savagefb_probe()
2232 kfree(par->edid); in savagefb_probe()
2233 fb_videomode_to_modelist(info->monspecs.modedb, in savagefb_probe()
2234 info->monspecs.modedb_len, in savagefb_probe()
2235 &info->modelist); in savagefb_probe()
2237 info->var = savagefb_var800x600x8; in savagefb_probe()
2239 if (par->SavagePanelWidth) { in savagefb_probe()
2243 cvt_mode.xres = par->SavagePanelWidth; in savagefb_probe()
2244 cvt_mode.yres = par->SavagePanelHeight; in savagefb_probe()
2250 else if (fb_find_mode(&info->var, info, NULL, NULL, 0, in savagefb_probe()
2252 info->var = savagefb_var800x600x8; in savagefb_probe()
2256 fb_find_mode(&info->var, info, mode_option, in savagefb_probe()
2257 info->monspecs.modedb, info->monspecs.modedb_len, in savagefb_probe()
2259 } else if (info->monspecs.modedb != NULL) { in savagefb_probe()
2262 mode = fb_find_best_display(&info->monspecs, &info->modelist); in savagefb_probe()
2263 savage_update_var(&info->var, mode); in savagefb_probe()
2267 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3); in savagefb_probe()
2268 info->var.yres_virtual = info->fix.smem_len/lpitch; in savagefb_probe()
2270 if (info->var.yres_virtual < info->var.yres) in savagefb_probe()
2278 if (info->var.yres_virtual > 0x1000) in savagefb_probe()
2279 info->var.yres_virtual = 0x1000; in savagefb_probe()
2281 if (info->var.xres_virtual > 0x1000) in savagefb_probe()
2282 info->var.xres_virtual = 0x1000; in savagefb_probe()
2284 savagefb_check_var(&info->var, info); in savagefb_probe()
2290 * the precision and fit the results into 32-bit registers. in savagefb_probe()
2293 h_sync = 1953125000 / info->var.pixclock; in savagefb_probe()
2294 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin + in savagefb_probe()
2295 info->var.right_margin + in savagefb_probe()
2296 info->var.hsync_len); in savagefb_probe()
2297 v_sync = h_sync / (info->var.yres + info->var.upper_margin + in savagefb_probe()
2298 info->var.lower_margin + info->var.vsync_len); in savagefb_probe()
2302 info->fix.smem_len >> 10, in savagefb_probe()
2303 info->var.xres, info->var.yres, in savagefb_probe()
2307 fb_destroy_modedb(info->monspecs.modedb); in savagefb_probe()
2308 info->monspecs.modedb = NULL; in savagefb_probe()
2315 info->fix.id); in savagefb_probe()
2328 fb_alloc_cmap(&info->cmap, 0, 0); in savagefb_probe()
2333 kfree(info->pixmap.addr); in savagefb_probe()
2361 fb_alloc_cmap(&info->cmap, 0, 0); in savagefb_remove()
2364 kfree(info->pixmap.addr); in savagefb_remove()
2379 struct savagefb_par *par = info->par; in savagefb_suspend()
2385 par->pm_state = mesg.event; in savagefb_suspend()
2386 dev->dev.power.power_state = mesg; in savagefb_suspend()
2398 if (info->fbops->fb_sync) in savagefb_suspend()
2399 info->fbops->fb_sync(info); in savagefb_suspend()
2402 savage_set_default_par(par, &par->save); in savagefb_suspend()
2415 struct savagefb_par *par = info->par; in savagefb_resume()
2416 int cur_state = par->pm_state; in savagefb_resume()
2420 par->pm_state = PM_EVENT_ON; in savagefb_resume()
2535 /* **************************** exit-time only **************************** */
2544 /* ************************* init in-kernel code ************************** */
2568 return -ENODEV; in savagefb_init()