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/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-video.c3 * Driver for Renesas RZ/G2L CRU
22 #include "rzg2l-cru.h"
23 #include "rzg2l-cru-regs.h"
48 static void __rzg2l_cru_write(struct rzg2l_cru_dev *cru, u32 offset, u32 value) in __rzg2l_cru_write() argument
50 const u16 *regs = cru->info->regs; in __rzg2l_cru_write()
53 * CRUnCTRL is a first register on all CRU supported SoCs so validate in __rzg2l_cru_write()
54 * rest of the registers have valid offset being set in cru->info->regs. in __rzg2l_cru_write()
60 iowrite32(value, cru->base + regs[offset]); in __rzg2l_cru_write()
63 static u32 __rzg2l_cru_read(struct rzg2l_cru_dev *cru, u32 offset) in __rzg2l_cru_read() argument
65 const u16 *regs = cru in __rzg2l_cru_read()
79 __rzg2l_cru_write_constant(struct rzg2l_cru_dev * cru,u32 offset,u32 value) __rzg2l_cru_write_constant() argument
89 __rzg2l_cru_read_constant(struct rzg2l_cru_dev * cru,u32 offset) __rzg2l_cru_read_constant() argument
98 rzg2l_cru_write(cru,offset,value) global() argument
103 rzg2l_cru_read(cru,offset) global() argument
109 return_unused_buffers(struct rzg2l_cru_dev * cru,enum vb2_buffer_state state) return_unused_buffers() argument
136 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); rzg2l_cru_queue_setup() local
150 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vb->vb2_queue); rzg2l_cru_buffer_prepare() local
167 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vb->vb2_queue); rzg2l_cru_buffer_queue() local
177 rzg2l_cru_set_slot_addr(struct rzg2l_cru_dev * cru,int slot,dma_addr_t addr) rzg2l_cru_set_slot_addr() argument
200 rzg2l_cru_fill_hw_slot(struct rzg2l_cru_dev * cru,int slot) rzg2l_cru_fill_hw_slot() argument
230 rzg2l_cru_initialize_axi(struct rzg2l_cru_dev * cru) rzg2l_cru_initialize_axi() argument
260 rzg3e_cru_csi2_setup(struct rzg2l_cru_dev * cru,const struct rzg2l_cru_ip_format * ip_fmt,u8 csi_vc) rzg3e_cru_csi2_setup() argument
278 rzg2l_cru_csi2_setup(struct rzg2l_cru_dev * cru,const struct rzg2l_cru_ip_format * ip_fmt,u8 csi_vc) rzg2l_cru_csi2_setup() argument
293 rzg2l_cru_initialize_image_conv(struct rzg2l_cru_dev * cru,struct v4l2_mbus_framefmt * ip_sd_fmt,u8 csi_vc) rzg2l_cru_initialize_image_conv() argument
326 rzg3e_fifo_empty(struct rzg2l_cru_dev * cru) rzg3e_fifo_empty() argument
339 rzg2l_fifo_empty(struct rzg2l_cru_dev * cru) rzg2l_fifo_empty() argument
352 rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev * cru) rzg2l_cru_stop_image_processing() argument
419 rzg2l_cru_get_virtual_channel(struct rzg2l_cru_dev * cru) rzg2l_cru_get_virtual_channel() argument
448 rzg3e_cru_enable_interrupts(struct rzg2l_cru_dev * cru) rzg3e_cru_enable_interrupts() argument
454 rzg3e_cru_disable_interrupts(struct rzg2l_cru_dev * cru) rzg3e_cru_disable_interrupts() argument
462 rzg2l_cru_enable_interrupts(struct rzg2l_cru_dev * cru) rzg2l_cru_enable_interrupts() argument
467 rzg2l_cru_disable_interrupts(struct rzg2l_cru_dev * cru) rzg2l_cru_disable_interrupts() argument
473 rzg2l_cru_start_image_processing(struct rzg2l_cru_dev * cru) rzg2l_cru_start_image_processing() argument
518 rzg2l_cru_set_stream(struct rzg2l_cru_dev * cru,int on) rzg2l_cru_set_stream() argument
573 rzg2l_cru_stop_streaming(struct rzg2l_cru_dev * cru) rzg2l_cru_stop_streaming() argument
582 struct rzg2l_cru_dev *cru = data; rzg2l_cru_irq() local
663 rzg3e_cru_get_current_slot(struct rzg2l_cru_dev * cru) rzg3e_cru_get_current_slot() argument
690 struct rzg2l_cru_dev *cru = data; rzg3e_cru_irq() local
763 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); rzg2l_cru_start_streaming_vq() local
831 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); rzg2l_cru_stop_streaming_vq() local
854 rzg2l_cru_dma_unregister(struct rzg2l_cru_dev * cru) rzg2l_cru_dma_unregister() argument
862 rzg2l_cru_dma_register(struct rzg2l_cru_dev * cru) rzg2l_cru_dma_register() argument
913 rzg2l_cru_format_align(struct rzg2l_cru_dev * cru,struct v4l2_pix_format * pix) rzg2l_cru_format_align() argument
948 rzg2l_cru_try_format(struct rzg2l_cru_dev * cru,struct v4l2_pix_format * pix) rzg2l_cru_try_format() argument
978 struct rzg2l_cru_dev *cru = video_drvdata(file); rzg2l_cru_try_fmt_vid_cap() local
988 struct rzg2l_cru_dev *cru = video_drvdata(file); rzg2l_cru_s_fmt_vid_cap() local
1003 struct rzg2l_cru_dev *cru = video_drvdata(file); rzg2l_cru_g_fmt_vid_cap() local
1027 struct rzg2l_cru_dev *cru = video_drvdata(file); rzg2l_cru_enum_framesizes() local
1074 struct rzg2l_cru_dev *cru = video_drvdata(file); rzg2l_cru_open() local
1098 struct rzg2l_cru_dev *cru = video_drvdata(file); rzg2l_cru_release() local
1132 struct rzg2l_cru_dev *cru; rzg2l_cru_video_link_validate() local
1158 rzg2l_cru_v4l2_init(struct rzg2l_cru_dev * cru) rzg2l_cru_v4l2_init() argument
1182 rzg2l_cru_video_unregister(struct rzg2l_cru_dev * cru) rzg2l_cru_video_unregister() argument
1188 rzg2l_cru_video_register(struct rzg2l_cru_dev * cru) rzg2l_cru_video_register() argument
[all...]
H A Drzg2l-core.c3 * Driver for Renesas RZ/G2L CRU
24 #include "rzg2l-cru.h"
25 #include "rzg2l-cru-regs.h"
42 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); in rzg2l_cru_group_notify_complete() local
46 ret = rzg2l_cru_ip_subdev_register(cru); in rzg2l_cru_group_notify_complete()
50 ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); in rzg2l_cru_group_notify_complete()
52 dev_err(cru->dev, "Failed to register subdev nodes\n"); in rzg2l_cru_group_notify_complete()
56 ret = rzg2l_cru_video_register(cru); in rzg2l_cru_group_notify_complete()
61 * CRU can be connected either to CSI2 or PARALLEL device in rzg2l_cru_group_notify_complete()
64 * Create media device link between CSI-2 <-> CRU I in rzg2l_cru_group_notify_complete()
97 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); rzg2l_cru_group_notify_unbind() local
115 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); rzg2l_cru_group_notify_bound() local
135 rzg2l_cru_mc_parse_of(struct rzg2l_cru_dev * cru) rzg2l_cru_mc_parse_of() argument
181 rzg2l_cru_mc_parse_of_graph(struct rzg2l_cru_dev * cru) rzg2l_cru_mc_parse_of_graph() argument
206 rzg2l_cru_media_init(struct rzg2l_cru_dev * cru) rzg2l_cru_media_init() argument
245 struct rzg2l_cru_dev *cru; rzg2l_cru_probe() local
309 struct rzg2l_cru_dev *cru = platform_get_drvdata(pdev); rzg2l_cru_remove() local
[all...]
H A Drzg2l-cru-regs.h3 * rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions
11 /* HW CRU Registers Definition */
26 /* Memory Bank Base Address (Lower) Register for CRU Image Data */
29 /* Memory Bank Base Address (Higher) Register for CRU Image Data */
70 CRUnCTRL, /* CRU Control */
71 CRUnIE, /* CRU Interrupt Enable */
72 CRUnIE2, /* CRU Interrupt Enable(2) */
73 CRUnINTS, /* CRU Interrupt Status */
74 CRUnINTS2, /* CRU Interrup
[all...]
H A Drzg2l-cru.h3 * Driver for Renesas RZ/G2L CRU
66 * struct rzg2l_cru_ip_format - CRU IP format
92 void (*enable_interrupts)(struct rzg2l_cru_dev *cru);
93 void (*disable_interrupts)(struct rzg2l_cru_dev *cru);
94 bool (*fifo_empty)(struct rzg2l_cru_dev *cru);
95 void (*csi_setup)(struct rzg2l_cru_dev *cru,
101 * struct rzg2l_cru_dev - Renesas CRU device structure
104 * @info: info about CRU instance
109 * @vclk: CRU Main clock
111 * @vdev: V4L2 video device associated with CRU
[all...]
H A Drzg2l-ip.c3 * Driver for Renesas RZ/G2L CRU
11 #include "rzg2l-cru.h"
12 #include "rzg2l-cru-regs.h"
143 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru) in rzg2l_cru_ip_get_src_fmt() argument
148 state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev); in rzg2l_cru_ip_get_src_fmt()
157 struct rzg2l_cru_dev *cru; in rzg2l_cru_ip_s_stream() local
161 cru = v4l2_get_subdevdata(sd); in rzg2l_cru_ip_s_stream()
164 ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); in rzg2l_cru_ip_s_stream()
168 ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff); in rzg2l_cru_ip_s_stream()
173 rzg2l_cru_stop_image_processing(cru); in rzg2l_cru_ip_s_stream()
206 struct rzg2l_cru_dev *cru = v4l2_get_subdevdata(sd); rzg2l_cru_ip_set_format() local
272 struct rzg2l_cru_dev *cru = v4l2_get_subdevdata(sd); rzg2l_cru_ip_enum_frame_size() local
330 rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev * cru) rzg2l_cru_ip_subdev_register() argument
372 rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev * cru) rzg2l_cru_ip_subdev_unregister() argument
[all...]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-extra.dtsi54 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
55 <&cru ACLK_USB3OTG1>;
62 resets = <&cru SRST_A_USB3OTG1>;
95 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
99 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
118 assigned-clock-parents = <&cru PLL_AUPLL>;
119 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
121 clocks = <&cru MCLK_SPDIF
[all...]
H A Drk3588-base.dtsi6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
11 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
455 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
456 <&cru CLK_GPU_STACKS>;
471 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
472 <&cru ACLK_USB3OTG0>;
479 resets = <&cru SRST_A_USB3OTG0>;
493 clocks = <&cru HCLK_HOST
732 cru: clock-controller@fd7c0000 { global() label
[all...]
H A Drk3576.dtsi6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
442 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
454 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
466 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
478 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO
841 cru: clock-controller@27200000 { global() label
[all...]
H A Drk3528.dtsi11 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
138 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
150 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
162 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
174 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO
424 cru: clock-controller@ff4a0000 { global() label
[all...]
H A Drk356x-base.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
217 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
218 <&cru CLK_SATA1_RXOOB>;
231 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
232 <&cru CLK_SATA2_RXOOB>;
246 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
247 <&cru ACLK_USB3OTG
390 cru: clock-controller@fdd20000 { global() label
[all...]
H A Drk3399-base.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
85 clocks = <&cru ARMCLKL>;
104 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKL>;
142 clocks = <&cru ARMCLKL>;
161 clocks = <&cru ARMCLKB>;
186 clocks = <&cru ARMCLKB>;
255 clocks = <&cru SCLK_DDRC>;
302 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCI
1565 cru: clock-controller@ff760000 { global() label
[all...]
H A Drk3562.dtsi6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
232 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
244 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
256 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
268 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO
565 cru: clock-controller@ff100000 { global() label
[all...]
H A Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
101 clocks = <&cru ARMCLK>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
270 clocks = <&cru SCLK_I2S
811 cru: clock-controller@ff440000 { global() label
[all...]
H A Drk3368.dtsi6 #include <dt-bindings/clock/rk3368-cru.h>
186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
191 resets = <&cru SRST_MMC0>;
200 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPL
750 cru: clock-controller@ff760000 { global() label
[all...]
H A Drk3568.dtsi102 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
103 <&cru CLK_SATA0_RXOOB>;
143 <&cru PCLK_PCIE30PHY>;
145 resets = <&cru SRST_PCIE30PHY>;
156 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
157 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
158 <&cru CLK_PCIE30X1_AUX_NDF
[all...]
H A Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
201 assigned-clocks = <&cru USB480M>;
203 clocks = <&cru SCLK_USBPHY_REF>;
245 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
258 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
271 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C
823 cru: clock-controller@ff500000 { global() label
[all...]
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
36 resets = <&cru SRST_CORE0>;
39 clocks = <&cru ARMCLK>;
47 resets = <&cru SRST_CORE1>;
57 resets = <&cru SRST_CORE2>;
67 resets = <&cru SRST_CORE3>;
143 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
156 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8C
487 cru: clock-controller@110e0000 { global() label
[all...]
H A Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
70 resets = <&cru SRST_CORE0>;
73 clocks = <&cru ARMCLK>;
80 resets = <&cru SRST_CORE1>;
83 clocks = <&cru ARMCLK>;
90 resets = <&cru SRST_CORE2>;
93 clocks = <&cru ARMCLK>;
100 resets = <&cru SRST_CORE3>;
103 clocks = <&cru ARMCLK>;
205 clocks = <&cru PCLK_TIME
868 cru: clock-controller@ff760000 { global() label
[all...]
H A Drk3128.dtsi6 #include <dt-bindings/clock/rk3128-cru.h>
51 clocks = <&cru ARMCLK>;
52 resets = <&cru SRST_CORE0>;
61 resets = <&cru SRST_CORE1>;
69 resets = <&cru SRST_CORE2>;
77 resets = <&cru SRST_CORE3>;
196 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
199 resets = <&cru SRST_GPU>;
216 clocks = <&cru ACLK_CI
542 cru: clock-controller@20000000 { global() label
[all...]
H A Drk3xxx.dtsi46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
48 assigned-clocks = <&cru ACLK_GPU>;
50 resets = <&cru SRST_GPU>;
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
82 clocks = <&cru CORE_PERI>;
96 clocks = <&cru CORE_PER
[all...]
H A Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
41 clocks = <&cru ARMCLK>;
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC
224 cru: clock-controller@20000000 { global() label
[all...]
H A Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
44 resets = <&cru SRST_CORE0>;
50 clocks = <&cru ARMCLK>;
57 resets = <&cru SRST_CORE1>;
114 assigned-clocks = <&cru SCLK_GPU>;
116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
119 resets = <&cru SRST_GPU>;
128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODE
334 cru: clock-controller@20000000 { global() label
[all...]
H A Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
35 clocks = <&cru ARMCLK>;
102 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
117 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
132 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
146 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C
440 cru: clock-controller@20200000 { global() label
[all...]
H A Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
26 clocks = <&cru ARMCLK>;
28 resets = <&cru SRST_CORE0>;
36 resets = <&cru SRST_CORE1>;
44 resets = <&cru SRST_CORE2>;
52 resets = <&cru SRST_CORE3>;
118 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
121 resets = <&cru SRST_LCDC0_AX
194 cru: clock-controller@20000000 { global() label
[all...]
/linux/Documentation/devicetree/bindings/media/
H A Drenesas,rzg2l-cru.yaml5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing
14 The CRU image processing module is a data conversion module equipped with pixel
23 - renesas,r9a07g043-cru # RZ/G2UL
24 - renesas,r9a07g044-cru # RZ/G2{L,LC}
25 - renesas,r9a07g054-cru # RZ/V2L
26 - const: renesas,rzg2l-cru
27 - const: renesas,r9a09g047-cru # RZ/G3E
35 - description: CRU Interrupt for image_conv
36 - description: CRU Interrup
[all...]

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