Lines Matching full:cru
11 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
138 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
150 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
162 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
174 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
186 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
424 cru: clock-controller@ff4a0000 {
425 compatible = "rockchip,rk3528-cru";
428 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
429 <&cru PLL_PPLL>, <&cru PLL_CPLL>,
430 <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
431 <&cru CLK_MATRIX_500M_SRC>,
432 <&cru CLK_MATRIX_50M_SRC>,
433 <&cru CLK_MATRIX_100M_SRC>,
434 <&cru CLK_MATRIX_150M_SRC>,
435 <&cru CLK_MATRIX_200M_SRC>,
436 <&cru CLK_MATRIX_300M_SRC>,
437 <&cru CLK_MATRIX_339M_SRC>,
438 <&cru CLK_MATRIX_400M_SRC>,
439 <&cru CLK_MATRIX_600M_SRC>,
440 <&cru CLK_PPLL_50M_MATRIX>,
441 <&cru CLK_PPLL_100M_MATRIX>,
442 <&cru CLK_PPLL_125M_MATRIX>,
443 <&cru ACLK_BUS_VOPGL_ROOT>;
485 clocks = <&cru ACLK_GPU_MALI>,
486 <&cru PCLK_GPU_ROOT>;
539 assigned-clocks = <&cru ACLK_GPU_MALI>,
542 clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>;
560 resets = <&cru SRST_A_GPU>;
568 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
582 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
595 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
607 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
619 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
631 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
643 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
655 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
667 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
679 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
692 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
704 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
716 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
730 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
742 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
756 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
768 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
780 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
794 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
804 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
814 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
824 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
834 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
844 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
854 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
864 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
873 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
876 resets = <&cru SRST_P_SARADC>;
885 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
886 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
887 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
896 resets = <&cru SRST_A_MAC_VO>;
914 clocks = <&cru CLK_MACPHY>;
919 resets = <&cru SRST_MACPHY>;
943 clocks = <&cru CLK_GMAC1_SRC_VPU>,
944 <&cru CLK_GMAC1_RMII_VPU>,
945 <&cru PCLK_MAC_VPU>,
946 <&cru ACLK_MAC_VPU>;
954 resets = <&cru SRST_A_MAC>;
991 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
992 <&cru CCLK_SRC_EMMC>;
995 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
996 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
997 <&cru TCLK_EMMC>;
1004 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1005 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1006 <&cru SRST_T_EMMC>;
1015 clocks = <&cru HCLK_SDIO0>,
1016 <&cru CCLK_SRC_SDIO0>,
1017 <&cru SCLK_SDIO0_DRV>,
1018 <&cru SCLK_SDIO0_SAMPLE>;
1025 resets = <&cru SRST_H_SDIO0>;
1034 clocks = <&cru HCLK_SDIO1>,
1035 <&cru CCLK_SRC_SDIO1>,
1036 <&cru SCLK_SDIO1_DRV>,
1037 <&cru SCLK_SDIO1_SAMPLE>;
1044 resets = <&cru SRST_H_SDIO1>;
1053 clocks = <&cru HCLK_SDMMC0>,
1054 <&cru CCLK_SRC_SDMMC0>,
1055 <&cru SCLK_SDMMC_DRV>,
1056 <&cru SCLK_SDMMC_SAMPLE>;
1064 resets = <&cru SRST_H_SDMMC0>;
1073 clocks = <&cru ACLK_DMAC>;