1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rockchip,rk3528-cru.h> 12#include <dt-bindings/reset/rockchip,rk3528-cru.h> 13 14/ { 15 compatible = "rockchip,rk3528"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 core2 { 42 cpu = <&cpu2>; 43 }; 44 core3 { 45 cpu = <&cpu3>; 46 }; 47 }; 48 }; 49 50 cpu0: cpu@0 { 51 compatible = "arm,cortex-a53"; 52 reg = <0x0>; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 clocks = <&scmi_clk SCMI_CLK_CPU>; 56 }; 57 58 cpu1: cpu@1 { 59 compatible = "arm,cortex-a53"; 60 reg = <0x1>; 61 device_type = "cpu"; 62 enable-method = "psci"; 63 clocks = <&scmi_clk SCMI_CLK_CPU>; 64 }; 65 66 cpu2: cpu@2 { 67 compatible = "arm,cortex-a53"; 68 reg = <0x2>; 69 device_type = "cpu"; 70 enable-method = "psci"; 71 clocks = <&scmi_clk SCMI_CLK_CPU>; 72 }; 73 74 cpu3: cpu@3 { 75 compatible = "arm,cortex-a53"; 76 reg = <0x3>; 77 device_type = "cpu"; 78 enable-method = "psci"; 79 clocks = <&scmi_clk SCMI_CLK_CPU>; 80 }; 81 }; 82 83 firmware { 84 scmi: scmi { 85 compatible = "arm,scmi-smc"; 86 arm,smc-id = <0x82000010>; 87 shmem = <&scmi_shmem>; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 scmi_clk: protocol@14 { 92 reg = <0x14>; 93 #clock-cells = <1>; 94 }; 95 }; 96 }; 97 98 gpu_opp_table: opp-table-gpu { 99 compatible = "operating-points-v2"; 100 101 opp-300000000 { 102 opp-hz = /bits/ 64 <300000000>; 103 opp-microvolt = <875000 875000 1000000>; 104 opp-suspend; 105 }; 106 107 opp-500000000 { 108 opp-hz = /bits/ 64 <500000000>; 109 opp-microvolt = <875000 875000 1000000>; 110 }; 111 112 opp-600000000 { 113 opp-hz = /bits/ 64 <600000000>; 114 opp-microvolt = <875000 875000 1000000>; 115 }; 116 117 opp-700000000 { 118 opp-hz = /bits/ 64 <700000000>; 119 opp-microvolt = <900000 900000 1000000>; 120 }; 121 122 opp-800000000 { 123 opp-hz = /bits/ 64 <800000000>; 124 opp-microvolt = <950000 950000 1000000>; 125 }; 126 }; 127 128 pinctrl: pinctrl { 129 compatible = "rockchip,rk3528-pinctrl"; 130 rockchip,grf = <&ioc_grf>; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 gpio0: gpio@ff610000 { 136 compatible = "rockchip,gpio-bank"; 137 reg = <0x0 0xff610000 0x0 0x200>; 138 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 139 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 140 gpio-controller; 141 #gpio-cells = <2>; 142 gpio-ranges = <&pinctrl 0 0 32>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 }; 146 147 gpio1: gpio@ffaf0000 { 148 compatible = "rockchip,gpio-bank"; 149 reg = <0x0 0xffaf0000 0x0 0x200>; 150 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 151 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 152 gpio-controller; 153 #gpio-cells = <2>; 154 gpio-ranges = <&pinctrl 0 32 32>; 155 interrupt-controller; 156 #interrupt-cells = <2>; 157 }; 158 159 gpio2: gpio@ffb00000 { 160 compatible = "rockchip,gpio-bank"; 161 reg = <0x0 0xffb00000 0x0 0x200>; 162 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 164 gpio-controller; 165 #gpio-cells = <2>; 166 gpio-ranges = <&pinctrl 0 64 32>; 167 interrupt-controller; 168 #interrupt-cells = <2>; 169 }; 170 171 gpio3: gpio@ffb10000 { 172 compatible = "rockchip,gpio-bank"; 173 reg = <0x0 0xffb10000 0x0 0x200>; 174 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 175 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 176 gpio-controller; 177 #gpio-cells = <2>; 178 gpio-ranges = <&pinctrl 0 96 32>; 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 }; 182 183 gpio4: gpio@ffb20000 { 184 compatible = "rockchip,gpio-bank"; 185 reg = <0x0 0xffb20000 0x0 0x200>; 186 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 187 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 188 gpio-controller; 189 #gpio-cells = <2>; 190 gpio-ranges = <&pinctrl 0 128 32>; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 }; 194 }; 195 196 psci { 197 compatible = "arm,psci-1.0", "arm,psci-0.2"; 198 method = "smc"; 199 }; 200 201 reserved-memory { 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 scmi_shmem: shmem@10f000 { 207 compatible = "arm,scmi-shmem"; 208 reg = <0x0 0x0010f000 0x0 0x100>; 209 no-map; 210 }; 211 }; 212 213 timer { 214 compatible = "arm,armv8-timer"; 215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219 }; 220 221 xin24m: clock-xin24m { 222 compatible = "fixed-clock"; 223 clock-frequency = <24000000>; 224 clock-output-names = "xin24m"; 225 #clock-cells = <0>; 226 }; 227 228 gmac0_clk: clock-gmac50m { 229 compatible = "fixed-clock"; 230 clock-frequency = <50000000>; 231 clock-output-names = "gmac0"; 232 #clock-cells = <0>; 233 }; 234 235 soc { 236 compatible = "simple-bus"; 237 ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; 238 #address-cells = <2>; 239 #size-cells = <2>; 240 241 gic: interrupt-controller@fed01000 { 242 compatible = "arm,gic-400"; 243 reg = <0x0 0xfed01000 0 0x1000>, 244 <0x0 0xfed02000 0 0x2000>, 245 <0x0 0xfed04000 0 0x2000>, 246 <0x0 0xfed06000 0 0x2000>; 247 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 248 IRQ_TYPE_LEVEL_LOW)>; 249 interrupt-controller; 250 #address-cells = <0>; 251 #interrupt-cells = <3>; 252 }; 253 254 qos_crypto_a: qos@ff200000 { 255 compatible = "rockchip,rk3528-qos", "syscon"; 256 reg = <0x0 0xff200000 0x0 0x20>; 257 }; 258 259 qos_crypto_p: qos@ff200080 { 260 compatible = "rockchip,rk3528-qos", "syscon"; 261 reg = <0x0 0xff200080 0x0 0x20>; 262 }; 263 264 qos_dcf: qos@ff200100 { 265 compatible = "rockchip,rk3528-qos", "syscon"; 266 reg = <0x0 0xff200100 0x0 0x20>; 267 }; 268 269 qos_dft2apb: qos@ff200200 { 270 compatible = "rockchip,rk3528-qos", "syscon"; 271 reg = <0x0 0xff200200 0x0 0x20>; 272 }; 273 274 qos_dma2ddr: qos@ff200280 { 275 compatible = "rockchip,rk3528-qos", "syscon"; 276 reg = <0x0 0xff200280 0x0 0x20>; 277 }; 278 279 qos_dmac: qos@ff200300 { 280 compatible = "rockchip,rk3528-qos", "syscon"; 281 reg = <0x0 0xff200300 0x0 0x20>; 282 }; 283 284 qos_keyreader: qos@ff200380 { 285 compatible = "rockchip,rk3528-qos", "syscon"; 286 reg = <0x0 0xff200380 0x0 0x20>; 287 }; 288 289 qos_cpu: qos@ff210000 { 290 compatible = "rockchip,rk3528-qos", "syscon"; 291 reg = <0x0 0xff210000 0x0 0x20>; 292 }; 293 294 qos_debug: qos@ff210080 { 295 compatible = "rockchip,rk3528-qos", "syscon"; 296 reg = <0x0 0xff210080 0x0 0x20>; 297 }; 298 299 qos_gpu_m0: qos@ff220000 { 300 compatible = "rockchip,rk3528-qos", "syscon"; 301 reg = <0x0 0xff220000 0x0 0x20>; 302 }; 303 304 qos_gpu_m1: qos@ff220080 { 305 compatible = "rockchip,rk3528-qos", "syscon"; 306 reg = <0x0 0xff220080 0x0 0x20>; 307 }; 308 309 qos_pmu_mcu: qos@ff240000 { 310 compatible = "rockchip,rk3528-qos", "syscon"; 311 reg = <0x0 0xff240000 0x0 0x20>; 312 }; 313 314 qos_rkvdec: qos@ff250000 { 315 compatible = "rockchip,rk3528-qos", "syscon"; 316 reg = <0x0 0xff250000 0x0 0x20>; 317 }; 318 319 qos_rkvenc: qos@ff260000 { 320 compatible = "rockchip,rk3528-qos", "syscon"; 321 reg = <0x0 0xff260000 0x0 0x20>; 322 }; 323 324 qos_gmac0: qos@ff270000 { 325 compatible = "rockchip,rk3528-qos", "syscon"; 326 reg = <0x0 0xff270000 0x0 0x20>; 327 }; 328 329 qos_hdcp: qos@ff270080 { 330 compatible = "rockchip,rk3528-qos", "syscon"; 331 reg = <0x0 0xff270080 0x0 0x20>; 332 }; 333 334 qos_jpegdec: qos@ff270100 { 335 compatible = "rockchip,rk3528-qos", "syscon"; 336 reg = <0x0 0xff270100 0x0 0x20>; 337 }; 338 339 qos_rga2_m0ro: qos@ff270200 { 340 compatible = "rockchip,rk3528-qos", "syscon"; 341 reg = <0x0 0xff270200 0x0 0x20>; 342 }; 343 344 qos_rga2_m0wo: qos@ff270280 { 345 compatible = "rockchip,rk3528-qos", "syscon"; 346 reg = <0x0 0xff270280 0x0 0x20>; 347 }; 348 349 qos_sdmmc0: qos@ff270300 { 350 compatible = "rockchip,rk3528-qos", "syscon"; 351 reg = <0x0 0xff270300 0x0 0x20>; 352 }; 353 354 qos_usb2host: qos@ff270380 { 355 compatible = "rockchip,rk3528-qos", "syscon"; 356 reg = <0x0 0xff270380 0x0 0x20>; 357 }; 358 359 qos_vdpp: qos@ff270480 { 360 compatible = "rockchip,rk3528-qos", "syscon"; 361 reg = <0x0 0xff270480 0x0 0x20>; 362 }; 363 364 qos_vop: qos@ff270500 { 365 compatible = "rockchip,rk3528-qos", "syscon"; 366 reg = <0x0 0xff270500 0x0 0x20>; 367 }; 368 369 qos_emmc: qos@ff280000 { 370 compatible = "rockchip,rk3528-qos", "syscon"; 371 reg = <0x0 0xff280000 0x0 0x20>; 372 }; 373 374 qos_fspi: qos@ff280080 { 375 compatible = "rockchip,rk3528-qos", "syscon"; 376 reg = <0x0 0xff280080 0x0 0x20>; 377 }; 378 379 qos_gmac1: qos@ff280100 { 380 compatible = "rockchip,rk3528-qos", "syscon"; 381 reg = <0x0 0xff280100 0x0 0x20>; 382 }; 383 384 qos_pcie: qos@ff280180 { 385 compatible = "rockchip,rk3528-qos", "syscon"; 386 reg = <0x0 0xff280180 0x0 0x20>; 387 }; 388 389 qos_sdio0: qos@ff280200 { 390 compatible = "rockchip,rk3528-qos", "syscon"; 391 reg = <0x0 0xff280200 0x0 0x20>; 392 }; 393 394 qos_sdio1: qos@ff280280 { 395 compatible = "rockchip,rk3528-qos", "syscon"; 396 reg = <0x0 0xff280280 0x0 0x20>; 397 }; 398 399 qos_tsp: qos@ff280300 { 400 compatible = "rockchip,rk3528-qos", "syscon"; 401 reg = <0x0 0xff280300 0x0 0x20>; 402 }; 403 404 qos_usb3otg: qos@ff280380 { 405 compatible = "rockchip,rk3528-qos", "syscon"; 406 reg = <0x0 0xff280380 0x0 0x20>; 407 }; 408 409 qos_vpu: qos@ff280400 { 410 compatible = "rockchip,rk3528-qos", "syscon"; 411 reg = <0x0 0xff280400 0x0 0x20>; 412 }; 413 414 vpu_grf: syscon@ff340000 { 415 compatible = "rockchip,rk3528-vpu-grf", "syscon"; 416 reg = <0x0 0xff340000 0x0 0x8000>; 417 }; 418 419 vo_grf: syscon@ff360000 { 420 compatible = "rockchip,rk3528-vo-grf", "syscon"; 421 reg = <0x0 0xff360000 0x0 0x10000>; 422 }; 423 424 cru: clock-controller@ff4a0000 { 425 compatible = "rockchip,rk3528-cru"; 426 reg = <0x0 0xff4a0000 0x0 0x30000>; 427 assigned-clocks = 428 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, 429 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 430 <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, 431 <&cru CLK_MATRIX_500M_SRC>, 432 <&cru CLK_MATRIX_50M_SRC>, 433 <&cru CLK_MATRIX_100M_SRC>, 434 <&cru CLK_MATRIX_150M_SRC>, 435 <&cru CLK_MATRIX_200M_SRC>, 436 <&cru CLK_MATRIX_300M_SRC>, 437 <&cru CLK_MATRIX_339M_SRC>, 438 <&cru CLK_MATRIX_400M_SRC>, 439 <&cru CLK_MATRIX_600M_SRC>, 440 <&cru CLK_PPLL_50M_MATRIX>, 441 <&cru CLK_PPLL_100M_MATRIX>, 442 <&cru CLK_PPLL_125M_MATRIX>, 443 <&cru ACLK_BUS_VOPGL_ROOT>; 444 assigned-clock-rates = 445 <32768>, <1188000000>, 446 <1000000000>, <996000000>, 447 <408000000>, <250000000>, 448 <500000000>, 449 <50000000>, 450 <100000000>, 451 <150000000>, 452 <200000000>, 453 <300000000>, 454 <340000000>, 455 <400000000>, 456 <600000000>, 457 <50000000>, 458 <100000000>, 459 <125000000>, 460 <500000000>; 461 clocks = <&xin24m>, <&gmac0_clk>; 462 clock-names = "xin24m", "gmac0"; 463 #clock-cells = <1>; 464 #reset-cells = <1>; 465 }; 466 467 ioc_grf: syscon@ff540000 { 468 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 469 reg = <0x0 0xff540000 0x0 0x40000>; 470 }; 471 472 pmu: power-management@ff600000 { 473 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; 474 reg = <0x0 0xff600000 0x0 0x2000>; 475 476 power: power-controller { 477 compatible = "rockchip,rk3528-power-controller"; 478 #power-domain-cells = <1>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 482 /* These power domains are grouped by VD_GPU */ 483 power-domain@4 { 484 reg = <4>; 485 clocks = <&cru ACLK_GPU_MALI>, 486 <&cru PCLK_GPU_ROOT>; 487 pm_qos = <&qos_gpu_m0>, 488 <&qos_gpu_m1>; 489 #power-domain-cells = <0>; 490 }; 491 492 /* These power domains are grouped by VD_LOGIC */ 493 power-domain@5 { 494 reg = <5>; 495 pm_qos = <&qos_rkvdec>; 496 #power-domain-cells = <0>; 497 status = "disabled"; 498 }; 499 power-domain@6 { 500 reg = <6>; 501 pm_qos = <&qos_rkvenc>; 502 #power-domain-cells = <0>; 503 status = "disabled"; 504 }; 505 power-domain@7 { 506 reg = <7>; 507 pm_qos = <&qos_gmac0>, 508 <&qos_hdcp>, 509 <&qos_jpegdec>, 510 <&qos_rga2_m0ro>, 511 <&qos_rga2_m0wo>, 512 <&qos_sdmmc0>, 513 <&qos_usb2host>, 514 <&qos_vdpp>, 515 <&qos_vop>; 516 #power-domain-cells = <0>; 517 status = "disabled"; 518 }; 519 power-domain@8 { 520 reg = <8>; 521 pm_qos = <&qos_emmc>, 522 <&qos_fspi>, 523 <&qos_gmac1>, 524 <&qos_pcie>, 525 <&qos_sdio0>, 526 <&qos_sdio1>, 527 <&qos_tsp>, 528 <&qos_usb3otg>, 529 <&qos_vpu>; 530 #power-domain-cells = <0>; 531 status = "disabled"; 532 }; 533 }; 534 }; 535 536 gpu: gpu@ff700000 { 537 compatible = "rockchip,rk3528-mali", "arm,mali-450"; 538 reg = <0x0 0xff700000 0x0 0x40000>; 539 assigned-clocks = <&cru ACLK_GPU_MALI>, 540 <&scmi_clk SCMI_CLK_GPU>; 541 assigned-clock-rates = <297000000>, <300000000>; 542 clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>; 543 clock-names = "bus", "core"; 544 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "gp", 552 "gpmmu", 553 "pp", 554 "pp0", 555 "ppmmu0", 556 "pp1", 557 "ppmmu1"; 558 operating-points-v2 = <&gpu_opp_table>; 559 power-domains = <&power 4>; 560 resets = <&cru SRST_A_GPU>; 561 status = "disabled"; 562 }; 563 564 spi0: spi@ff9c0000 { 565 compatible = "rockchip,rk3528-spi", 566 "rockchip,rk3066-spi"; 567 reg = <0x0 0xff9c0000 0x0 0x1000>; 568 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 569 clock-names = "spiclk", "apb_pclk"; 570 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 571 dmas = <&dmac 25>, <&dmac 24>; 572 dma-names = "tx", "rx"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 spi1: spi@ff9d0000 { 579 compatible = "rockchip,rk3528-spi", 580 "rockchip,rk3066-spi"; 581 reg = <0x0 0xff9d0000 0x0 0x1000>; 582 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 583 clock-names = "spiclk", "apb_pclk"; 584 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 585 dmas = <&dmac 31>, <&dmac 30>; 586 dma-names = "tx", "rx"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 uart0: serial@ff9f0000 { 593 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 594 reg = <0x0 0xff9f0000 0x0 0x100>; 595 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 596 clock-names = "baudclk", "apb_pclk"; 597 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 598 dmas = <&dmac 9>, <&dmac 8>; 599 reg-io-width = <4>; 600 reg-shift = <2>; 601 status = "disabled"; 602 }; 603 604 uart1: serial@ff9f8000 { 605 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 606 reg = <0x0 0xff9f8000 0x0 0x100>; 607 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 608 clock-names = "baudclk", "apb_pclk"; 609 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 610 dmas = <&dmac 11>, <&dmac 10>; 611 reg-io-width = <4>; 612 reg-shift = <2>; 613 status = "disabled"; 614 }; 615 616 uart2: serial@ffa00000 { 617 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 618 reg = <0x0 0xffa00000 0x0 0x100>; 619 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 620 clock-names = "baudclk", "apb_pclk"; 621 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 622 dmas = <&dmac 13>, <&dmac 12>; 623 reg-io-width = <4>; 624 reg-shift = <2>; 625 status = "disabled"; 626 }; 627 628 uart3: serial@ffa08000 { 629 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 630 reg = <0x0 0xffa08000 0x0 0x100>; 631 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 632 clock-names = "baudclk", "apb_pclk"; 633 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 634 dmas = <&dmac 15>, <&dmac 14>; 635 reg-io-width = <4>; 636 reg-shift = <2>; 637 status = "disabled"; 638 }; 639 640 uart4: serial@ffa10000 { 641 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 642 reg = <0x0 0xffa10000 0x0 0x100>; 643 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 644 clock-names = "baudclk", "apb_pclk"; 645 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 646 dmas = <&dmac 17>, <&dmac 16>; 647 reg-io-width = <4>; 648 reg-shift = <2>; 649 status = "disabled"; 650 }; 651 652 uart5: serial@ffa18000 { 653 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 654 reg = <0x0 0xffa18000 0x0 0x100>; 655 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 656 clock-names = "baudclk", "apb_pclk"; 657 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 658 dmas = <&dmac 19>, <&dmac 18>; 659 reg-io-width = <4>; 660 reg-shift = <2>; 661 status = "disabled"; 662 }; 663 664 uart6: serial@ffa20000 { 665 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 666 reg = <0x0 0xffa20000 0x0 0x100>; 667 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 668 clock-names = "baudclk", "apb_pclk"; 669 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 670 dmas = <&dmac 21>, <&dmac 20>; 671 reg-io-width = <4>; 672 reg-shift = <2>; 673 status = "disabled"; 674 }; 675 676 uart7: serial@ffa28000 { 677 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 678 reg = <0x0 0xffa28000 0x0 0x100>; 679 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 680 clock-names = "baudclk", "apb_pclk"; 681 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 682 dmas = <&dmac 23>, <&dmac 22>; 683 reg-io-width = <4>; 684 reg-shift = <2>; 685 status = "disabled"; 686 }; 687 688 i2c0: i2c@ffa50000 { 689 compatible = "rockchip,rk3528-i2c", 690 "rockchip,rk3399-i2c"; 691 reg = <0x0 0xffa50000 0x0 0x1000>; 692 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 693 clock-names = "i2c", "pclk"; 694 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 i2c1: i2c@ffa58000 { 701 compatible = "rockchip,rk3528-i2c", 702 "rockchip,rk3399-i2c"; 703 reg = <0x0 0xffa58000 0x0 0x1000>; 704 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 705 clock-names = "i2c", "pclk"; 706 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 }; 711 712 i2c2: i2c@ffa60000 { 713 compatible = "rockchip,rk3528-i2c", 714 "rockchip,rk3399-i2c"; 715 reg = <0x0 0xffa60000 0x0 0x1000>; 716 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 717 clock-names = "i2c", "pclk"; 718 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&i2c2m1_xfer>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 i2c3: i2c@ffa68000 { 727 compatible = "rockchip,rk3528-i2c", 728 "rockchip,rk3399-i2c"; 729 reg = <0x0 0xffa68000 0x0 0x1000>; 730 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 731 clock-names = "i2c", "pclk"; 732 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 status = "disabled"; 736 }; 737 738 i2c4: i2c@ffa70000 { 739 compatible = "rockchip,rk3528-i2c", 740 "rockchip,rk3399-i2c"; 741 reg = <0x0 0xffa70000 0x0 0x1000>; 742 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 743 clock-names = "i2c", "pclk"; 744 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&i2c4_xfer>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 status = "disabled"; 750 }; 751 752 i2c5: i2c@ffa78000 { 753 compatible = "rockchip,rk3528-i2c", 754 "rockchip,rk3399-i2c"; 755 reg = <0x0 0xffa78000 0x0 0x1000>; 756 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 757 clock-names = "i2c", "pclk"; 758 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 i2c6: i2c@ffa80000 { 765 compatible = "rockchip,rk3528-i2c", 766 "rockchip,rk3399-i2c"; 767 reg = <0x0 0xffa80000 0x0 0x1000>; 768 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 769 clock-names = "i2c", "pclk"; 770 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 i2c7: i2c@ffa88000 { 777 compatible = "rockchip,rk3528-i2c", 778 "rockchip,rk3399-i2c"; 779 reg = <0x0 0xffa88000 0x0 0x1000>; 780 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 781 clock-names = "i2c", "pclk"; 782 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&i2c7_xfer>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "disabled"; 788 }; 789 790 pwm0: pwm@ffa90000 { 791 compatible = "rockchip,rk3528-pwm", 792 "rockchip,rk3328-pwm"; 793 reg = <0x0 0xffa90000 0x0 0x10>; 794 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 795 clock-names = "pwm", "pclk"; 796 #pwm-cells = <3>; 797 status = "disabled"; 798 }; 799 800 pwm1: pwm@ffa90010 { 801 compatible = "rockchip,rk3528-pwm", 802 "rockchip,rk3328-pwm"; 803 reg = <0x0 0xffa90010 0x0 0x10>; 804 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 805 clock-names = "pwm", "pclk"; 806 #pwm-cells = <3>; 807 status = "disabled"; 808 }; 809 810 pwm2: pwm@ffa90020 { 811 compatible = "rockchip,rk3528-pwm", 812 "rockchip,rk3328-pwm"; 813 reg = <0x0 0xffa90020 0x0 0x10>; 814 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 815 clock-names = "pwm", "pclk"; 816 #pwm-cells = <3>; 817 status = "disabled"; 818 }; 819 820 pwm3: pwm@ffa90030 { 821 compatible = "rockchip,rk3528-pwm", 822 "rockchip,rk3328-pwm"; 823 reg = <0x0 0xffa90030 0x0 0x10>; 824 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 825 clock-names = "pwm", "pclk"; 826 #pwm-cells = <3>; 827 status = "disabled"; 828 }; 829 830 pwm4: pwm@ffa98000 { 831 compatible = "rockchip,rk3528-pwm", 832 "rockchip,rk3328-pwm"; 833 reg = <0x0 0xffa98000 0x0 0x10>; 834 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 835 clock-names = "pwm", "pclk"; 836 #pwm-cells = <3>; 837 status = "disabled"; 838 }; 839 840 pwm5: pwm@ffa98010 { 841 compatible = "rockchip,rk3528-pwm", 842 "rockchip,rk3328-pwm"; 843 reg = <0x0 0xffa98010 0x0 0x10>; 844 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 845 clock-names = "pwm", "pclk"; 846 #pwm-cells = <3>; 847 status = "disabled"; 848 }; 849 850 pwm6: pwm@ffa98020 { 851 compatible = "rockchip,rk3528-pwm", 852 "rockchip,rk3328-pwm"; 853 reg = <0x0 0xffa98020 0x0 0x10>; 854 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 855 clock-names = "pwm", "pclk"; 856 #pwm-cells = <3>; 857 status = "disabled"; 858 }; 859 860 pwm7: pwm@ffa98030 { 861 compatible = "rockchip,rk3528-pwm", 862 "rockchip,rk3328-pwm"; 863 reg = <0x0 0xffa98030 0x0 0x10>; 864 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 865 clock-names = "pwm", "pclk"; 866 #pwm-cells = <3>; 867 status = "disabled"; 868 }; 869 870 saradc: adc@ffae0000 { 871 compatible = "rockchip,rk3528-saradc"; 872 reg = <0x0 0xffae0000 0x0 0x10000>; 873 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 874 clock-names = "saradc", "apb_pclk"; 875 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 876 resets = <&cru SRST_P_SARADC>; 877 reset-names = "saradc-apb"; 878 #io-channel-cells = <1>; 879 status = "disabled"; 880 }; 881 882 gmac0: ethernet@ffbd0000 { 883 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 884 reg = <0x0 0xffbd0000 0x0 0x10000>; 885 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 886 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 887 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 888 clock-names = "stmmaceth", "clk_mac_ref", 889 "mac_clk_rx", "mac_clk_tx", 890 "pclk_mac", "aclk_mac"; 891 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 893 interrupt-names = "macirq", "eth_wake_irq"; 894 phy-handle = <&rmii0_phy>; 895 phy-mode = "rmii"; 896 resets = <&cru SRST_A_MAC_VO>; 897 reset-names = "stmmaceth"; 898 rockchip,grf = <&vo_grf>; 899 snps,axi-config = <&gmac0_stmmac_axi_setup>; 900 snps,mixed-burst; 901 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 902 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 903 snps,tso; 904 status = "disabled"; 905 906 mdio0: mdio { 907 compatible = "snps,dwmac-mdio"; 908 #address-cells = <0x1>; 909 #size-cells = <0x0>; 910 911 rmii0_phy: ethernet-phy@2 { 912 compatible = "ethernet-phy-ieee802.3-c22"; 913 reg = <0x2>; 914 clocks = <&cru CLK_MACPHY>; 915 phy-is-integrated; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&fephym0_led_link>, 918 <&fephym0_led_spd>; 919 resets = <&cru SRST_MACPHY>; 920 }; 921 }; 922 923 gmac0_stmmac_axi_setup: stmmac-axi-config { 924 snps,blen = <0 0 0 0 16 8 4>; 925 snps,rd_osr_lmt = <8>; 926 snps,wr_osr_lmt = <4>; 927 }; 928 929 gmac0_mtl_rx_setup: rx-queues-config { 930 snps,rx-queues-to-use = <1>; 931 queue0 {}; 932 }; 933 934 gmac0_mtl_tx_setup: tx-queues-config { 935 snps,tx-queues-to-use = <1>; 936 queue0 {}; 937 }; 938 }; 939 940 gmac1: ethernet@ffbe0000 { 941 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 942 reg = <0x0 0xffbe0000 0x0 0x10000>; 943 clocks = <&cru CLK_GMAC1_SRC_VPU>, 944 <&cru CLK_GMAC1_RMII_VPU>, 945 <&cru PCLK_MAC_VPU>, 946 <&cru ACLK_MAC_VPU>; 947 clock-names = "stmmaceth", 948 "clk_mac_ref", 949 "pclk_mac", 950 "aclk_mac"; 951 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "macirq", "eth_wake_irq"; 954 resets = <&cru SRST_A_MAC>; 955 reset-names = "stmmaceth"; 956 rockchip,grf = <&vpu_grf>; 957 snps,axi-config = <&gmac1_stmmac_axi_setup>; 958 snps,mixed-burst; 959 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 960 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 961 snps,tso; 962 status = "disabled"; 963 964 mdio1: mdio { 965 compatible = "snps,dwmac-mdio"; 966 #address-cells = <0x1>; 967 #size-cells = <0x0>; 968 }; 969 970 gmac1_stmmac_axi_setup: stmmac-axi-config { 971 snps,blen = <0 0 0 0 16 8 4>; 972 snps,rd_osr_lmt = <8>; 973 snps,wr_osr_lmt = <4>; 974 }; 975 976 gmac1_mtl_rx_setup: rx-queues-config { 977 snps,rx-queues-to-use = <1>; 978 queue0 {}; 979 }; 980 981 gmac1_mtl_tx_setup: tx-queues-config { 982 snps,tx-queues-to-use = <1>; 983 queue0 {}; 984 }; 985 }; 986 987 sdhci: mmc@ffbf0000 { 988 compatible = "rockchip,rk3528-dwcmshc", 989 "rockchip,rk3588-dwcmshc"; 990 reg = <0x0 0xffbf0000 0x0 0x10000>; 991 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, 992 <&cru CCLK_SRC_EMMC>; 993 assigned-clock-rates = <200000000>, <24000000>, 994 <200000000>; 995 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 996 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 997 <&cru TCLK_EMMC>; 998 clock-names = "core", "bus", "axi", "block", "timer"; 999 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1000 max-frequency = <200000000>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, 1003 <&emmc_strb>; 1004 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1005 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1006 <&cru SRST_T_EMMC>; 1007 reset-names = "core", "bus", "axi", "block", "timer"; 1008 status = "disabled"; 1009 }; 1010 1011 sdio0: mmc@ffc10000 { 1012 compatible = "rockchip,rk3528-dw-mshc", 1013 "rockchip,rk3288-dw-mshc"; 1014 reg = <0x0 0xffc10000 0x0 0x4000>; 1015 clocks = <&cru HCLK_SDIO0>, 1016 <&cru CCLK_SRC_SDIO0>, 1017 <&cru SCLK_SDIO0_DRV>, 1018 <&cru SCLK_SDIO0_SAMPLE>; 1019 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1020 fifo-depth = <0x100>; 1021 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1022 max-frequency = <200000000>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; 1025 resets = <&cru SRST_H_SDIO0>; 1026 reset-names = "reset"; 1027 status = "disabled"; 1028 }; 1029 1030 sdio1: mmc@ffc20000 { 1031 compatible = "rockchip,rk3528-dw-mshc", 1032 "rockchip,rk3288-dw-mshc"; 1033 reg = <0x0 0xffc20000 0x0 0x4000>; 1034 clocks = <&cru HCLK_SDIO1>, 1035 <&cru CCLK_SRC_SDIO1>, 1036 <&cru SCLK_SDIO1_DRV>, 1037 <&cru SCLK_SDIO1_SAMPLE>; 1038 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1039 fifo-depth = <0x100>; 1040 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1041 max-frequency = <200000000>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; 1044 resets = <&cru SRST_H_SDIO1>; 1045 reset-names = "reset"; 1046 status = "disabled"; 1047 }; 1048 1049 sdmmc: mmc@ffc30000 { 1050 compatible = "rockchip,rk3528-dw-mshc", 1051 "rockchip,rk3288-dw-mshc"; 1052 reg = <0x0 0xffc30000 0x0 0x4000>; 1053 clocks = <&cru HCLK_SDMMC0>, 1054 <&cru CCLK_SRC_SDMMC0>, 1055 <&cru SCLK_SDMMC_DRV>, 1056 <&cru SCLK_SDMMC_SAMPLE>; 1057 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1058 fifo-depth = <0x100>; 1059 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1060 max-frequency = <150000000>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, 1063 <&sdmmc_det>; 1064 resets = <&cru SRST_H_SDMMC0>; 1065 reset-names = "reset"; 1066 rockchip,default-sample-phase = <90>; 1067 status = "disabled"; 1068 }; 1069 1070 dmac: dma-controller@ffd60000 { 1071 compatible = "arm,pl330", "arm,primecell"; 1072 reg = <0x0 0xffd60000 0x0 0x4000>; 1073 clocks = <&cru ACLK_DMAC>; 1074 clock-names = "apb_pclk"; 1075 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1084 #dma-cells = <1>; 1085 arm,pl330-periph-burst; 1086 }; 1087 }; 1088}; 1089 1090#include "rk3528-pinctrl.dtsi" 1091