Lines Matching full:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
101 clocks = <&cru ARMCLK>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
336 clocks = <&cru SCLK_VENC_CORE>;
341 clocks = <&cru ACLK_RKVDEC>,
342 <&cru HCLK_RKVDEC>,
343 <&cru SCLK_VDEC_CABAC>,
344 <&cru SCLK_VDEC_CORE>;
349 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
368 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
383 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
398 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
415 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
428 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
441 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
454 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
467 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
480 clocks = <&cru PCLK_WDT>;
486 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
497 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
508 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
519 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
533 clocks = <&cru ACLK_DMAC>;
582 assigned-clocks = <&cru SCLK_TSADC>;
584 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
590 resets = <&cru SRST_TSADC>;
603 clocks = <&cru SCLK_EFUSE>;
628 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
630 resets = <&cru SRST_SARADC_P>;
652 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
654 resets = <&cru SRST_GPU_A>;
661 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
671 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
682 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
692 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
702 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
703 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
705 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
706 <&cru SCLK_VDEC_CORE>;
716 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
726 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
728 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
744 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
755 clocks = <&cru PCLK_HDMI>,
756 <&cru SCLK_HDMI_SFC>,
757 <&cru SCLK_RTC32K>;
790 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
801 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
811 cru: clock-controller@ff440000 {
812 compatible = "rockchip,rk3328-cru";
826 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
827 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
828 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
829 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
830 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
831 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
832 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
833 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
834 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
835 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
836 <&cru SCLK_WIFI>, <&cru ARMCLK>,
837 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
838 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
839 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
841 <&cru SCLK_RTC32K>;
843 <&cru HDMIPHY>, <&cru PLL_APLL>,
844 <&cru PLL_GPLL>, <&xin24m>,
879 assigned-clocks = <&cru USB480M>;
906 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
907 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
911 resets = <&cru SRST_MMC0>;
920 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
921 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
925 resets = <&cru SRST_SDIO>;
934 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
935 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
939 resets = <&cru SRST_EMMC>;
949 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
950 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
951 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
952 <&cru PCLK_MAC2IO>;
957 resets = <&cru SRST_GMAC2IO_A>;
972 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
973 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
974 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
975 <&cru SCLK_MAC2PHY_OUT>;
980 resets = <&cru SRST_GMAC2PHY_A>;
998 clocks = <&cru SCLK_MAC2PHY_OUT>;
999 resets = <&cru SRST_MACPHY>;
1012 clocks = <&cru HCLK_OTG>;
1027 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1037 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1047 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
1048 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
1052 resets = <&cru SRST_SDMMCEXT>;
1061 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1062 <&cru ACLK_USB3OTG>;
1093 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1094 <&cru SCLK_CRYPTO>;
1096 resets = <&cru SRST_CRYPTO>;
1111 clocks = <&cru PCLK_GPIO0>;
1124 clocks = <&cru PCLK_GPIO1>;
1137 clocks = <&cru PCLK_GPIO2>;
1150 clocks = <&cru PCLK_GPIO3>;