dts/rockchip/rk3562.dtsi

6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
232 			clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
244 			clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
256 			clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
268 			clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
280 			clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
328 			clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
329 				 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
330 				 <&cru CLK_PCIE20_AUX>;
359 			resets = <&cru SRST_PCIE20_POWERUP>;
565 		cru: clock-controller@ff100000 {
566 			compatible = "rockchip,rk3562-cru";
571 			assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
572 					  <&cru PLL_HPLL>;
580 			clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>;
594 			clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>;
605 			clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>;
620 			clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
631 			clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
642 			clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
653 			clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
732 			clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>,
733 				 <&cru ACLK_GPU_PRE>;
750 			clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
766 			clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
782 			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
793 			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
804 			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
815 			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
826 			clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
837 			clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
848 			clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
859 			clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
870 			clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
880 			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
891 			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
902 			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
913 			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
924 			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
935 			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
946 			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
957 			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
968 			clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
979 			clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
990 			clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1001 			clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1013 			clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1015 			resets = <&cru SRST_P_SARADC>;
1025 			clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>,
1026 				 <&cru PCLK_PHP>;
1028 			assigned-clocks = <&cru CLK_PIPEPHY_REF>;
1030 			resets = <&cru SRST_PIPEPHY>;
1041 			clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1052 			assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
1054 			clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1055 				 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1056 				 <&cru TMCLK_EMMC>;
1058 			resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1059 				 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1060 				 <&cru SRST_T_EMMC>;
1071 			clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>,
1072 				 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1076 			resets = <&cru SRST_H_SDMMC0>;
1086 			clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>,
1087 				 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1091 			resets = <&cru SRST_H_SDMMC1>;
1100 			clocks = <&cru ACLK_DMAC>;
1110 			clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1123 			clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1136 			clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1149 			clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1162 			clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1176 			clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>;
1178 			resets = <&cru SRST_P_SARADC_VCCIO156>;