dts/rockchip/rk3036.dtsi

7 #include <dt-bindings/clock/rk3036-cru.h>
44 			resets = <&cru SRST_CORE0>;
50 			clocks = <&cru ARMCLK>;
57 			resets = <&cru SRST_CORE1>;
114 		assigned-clocks = <&cru SCLK_GPU>;
116 		clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
119 		resets = <&cru SRST_GPU>;
128 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
138 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
148 		clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
150 		resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
170 		clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
210 		clocks = <&cru HCLK_OTG0>;
226 		clocks = <&cru HCLK_OTG1>;
239 		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
246 		assigned-clocks = <&cru SCLK_MACPLL>;
247 		assigned-clock-parents = <&cru PLL_DPLL>;
258 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
262 		resets = <&cru SRST_MMC0>;
271 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
272 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
276 		resets = <&cru SRST_SDIO>;
289 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
290 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
300 		resets = <&cru SRST_EMMC>;
310 		clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
324 		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
326 		assigned-clocks = <&cru SCLK_NANDC>;
334 	cru: clock-controller@20000000 {
335 		compatible = "rockchip,rk3036-cru";
342 		assigned-clocks = <&cru PLL_GPLL>;
355 			clocks = <&cru SCLK_OTGPHY0>;
358 			assigned-clocks = <&cru SCLK_USB480M>;
389 				clocks = <&cru ACLK_LCDC>,
390 					 <&cru HCLK_LCDC>,
391 					 <&cru SCLK_LCDC>;
398 				clocks = <&cru ACLK_VCODEC>,
399 					 <&cru HCLK_VCODEC>;
406 				clocks = <&cru SCLK_GPU>;
426 		clocks = <&cru PCLK_ACODEC>;
436 		clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>;
466 		clocks = <&cru PCLK_TIMER>, <&xin24m>;
474 		clocks = <&cru PCLK_PWM>;
484 		clocks = <&cru PCLK_PWM>;
494 		clocks = <&cru PCLK_PWM>;
504 		clocks = <&cru PCLK_PWM>;
517 		clocks = <&cru PCLK_I2C1>;
530 		clocks = <&cru PCLK_I2C2>;
543 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
557 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
571 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
585 		clocks = <&cru PCLK_I2C0>;
595 		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
614 		clocks = <&cru ACLK_DMAC2>;
629 			clocks = <&cru PCLK_GPIO0>;
642 			clocks = <&cru PCLK_GPIO1>;
655 			clocks = <&cru PCLK_GPIO2>;