Lines Matching full:cru
102 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
103 <&cru CLK_SATA0_RXOOB>;
143 <&cru PCLK_PCIE30PHY>;
145 resets = <&cru SRST_PCIE30PHY>;
156 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
157 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
158 <&cru CLK_PCIE30X1_AUX_NDFT>;
190 resets = <&cru SRST_PCIE30X1_POWERUP>;
209 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
210 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
211 <&cru CLK_PCIE30X2_AUX_NDFT>;
243 resets = <&cru SRST_PCIE30X2_POWERUP>;
263 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
264 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
265 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
266 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
271 resets = <&cru SRST_A_GMAC0>;
308 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
310 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
321 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
323 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
334 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
336 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
347 <&cru PCLK_PIPEPHY0>,
348 <&cru PCLK_PIPE>;
352 resets = <&cru SRST_PIPEPHY0>;
388 clocks = <&cru PCLK_PIPE>;