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Searched refs:fpscr (Results 1 – 25 of 30) sorted by relevance

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/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c330 TCGv_i32 fpscr; in gen_M_fp_sysreg_write() local
344 fpscr = load_cpu_field_low32(vfp.fpsr); in gen_M_fp_sysreg_write()
345 tcg_gen_andi_i32(fpscr, fpscr, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
346 tcg_gen_or_i32(fpscr, fpscr, tmp); in gen_M_fp_sysreg_write()
347 store_cpu_field_low32(fpscr, vfp.fpsr); in gen_M_fp_sysreg_write()
474 TCGv_i32 control, sfpa, fpscr; in gen_M_fp_sysreg_read() local
495 fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); in gen_M_fp_sysreg_read()
496 gen_helper_vfp_set_fpscr(tcg_env, fpscr); in gen_M_fp_sysreg_read()
502 TCGv_i32 control, sfpa, fpscr, fpdscr; in gen_M_fp_sysreg_read() local
530 fpscr = tcg_temp_new_i32(); in gen_M_fp_sysreg_read()
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H A Dm_helper.c1143 uint32_t fpscr; in HELPER() local
1164 fpscr = cpu_ldl_data_ra(env, fptr + 0x40, ra); in HELPER()
1165 vfp_set_fpscr(env, fpscr); in HELPER()
1761 uint32_t fpscr; in do_v7m_exception_exit() local
1811 v7m_stack_read(cpu, &fpscr, frameptr + 0x60, mmu_idx); in do_v7m_exception_exit()
1813 vfp_set_fpscr(env, fpscr); in do_v7m_exception_exit()
/qemu/target/ppc/
H A Dfpu_helper.c163 env->fpscr = (env->fpscr & ~FP_FPRF) | fprf; \
175 env->fpscr |= FP_VX; in COMPUTE_FPRF()
177 env->fpscr |= FP_FX; in COMPUTE_FPRF()
178 if (env->fpscr & FP_VE) { in COMPUTE_FPRF()
180 env->fpscr |= FP_FEX; in COMPUTE_FPRF()
191 env->fpscr &= ~(FP_FR | FP_FI); in finish_invalid_op_arith()
192 if (!(env->fpscr & FP_VE)) { in finish_invalid_op_arith()
194 env->fpscr &= ~FP_FPCC; in finish_invalid_op_arith()
195 env->fpscr |= (FP_C | FP_FU); in finish_invalid_op_arith()
204 env->fpscr |= FP_VXSNAN; in float_invalid_op_vxsnan()
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H A Dcpu.c219 switch (env->fpscr & FP_RN) { in fpscr_set_rounding_mode()
250 env->fpscr = val; in ppc_store_fpscr()
251 env->fp_status.rebias_overflow = (FP_OE & env->fpscr) ? true : false; in ppc_store_fpscr()
252 env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false; in ppc_store_fpscr()
H A Ddfp_helper.c70 static void dfp_prepare_rounding_mode(decContext *context, uint64_t fpscr) in dfp_prepare_rounding_mode() argument
74 switch ((fpscr & FP_DRN) >> FPSCR_DRN0) { in dfp_prepare_rounding_mode()
151 dfp_prepare_rounding_mode(&dfp->context, env->fpscr); in dfp_prepare_decimal64()
175 dfp_prepare_rounding_mode(&dfp->context, env->fpscr); in dfp_prepare_decimal128()
208 dfp->env->fpscr |= (flag | FP_FX); in dfp_set_FPSCR_flag()
209 if (dfp->env->fpscr & enabled) { in dfp_set_FPSCR_flag()
210 dfp->env->fpscr |= FP_FEX; in dfp_set_FPSCR_flag()
254 dfp->env->fpscr &= ~FP_FPRF; in dfp_set_FPRF_from_FRT_with_context()
255 dfp->env->fpscr |= (fprf << FPSCR_FPRF); in dfp_set_FPRF_from_FRT_with_context()
403 dfp->env->fpscr &= ~FP_FPCC; in dfp_set_FPCC_from_CRBF()
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H A Darch_dump.c63 reg_t fpscr; member
152 fpregset->fpscr = cpu_to_dump_reg(s, cpu->env.fpscr); in ppc_write_elf_fpregset()
H A Dppc-qmp-cmds.c96 { "fpscr", offsetof(CPUPPCState, fpscr) },
H A Dgdbstub.c196 gdb_get_reg64(buf, env->fpscr); in ppc_cpu_gdb_read_register_apple()
452 gdb_get_reg32(buf, env->fpscr); in gdb_get_float_reg()
H A Dkvm.c638 uint64_t fpscr = env->fpscr; in kvm_put_fp() local
642 reg.addr = (uintptr_t)&fpscr; in kvm_put_fp()
704 uint64_t fpscr; in kvm_get_fp() local
708 reg.addr = (uintptr_t)&fpscr; in kvm_get_fp()
714 env->fpscr = fpscr; in kvm_get_fp()
H A Dmachine.c295 VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
/qemu/tests/tcg/ppc64/
H A Dmffsce.c20 uint64_t frt, fpscr; in main() local
25 MFFS(fpscr); /* read the value that mffsce stored to cpu fpscr */ in main()
34 assert((fpscr & 0xff) == (test_value & 0x7)); in main()
H A Dmtfsf.c28 uint64_t fpscr; in main() local
45 MFFS(fpscr); in main()
46 assert((fpscr & FP_FI) != 0); in main()
/qemu/target/sh4/
H A Dop_helper.c206 env->fpscr = val & FPSCR_MASK; in helper_ld_fpscr()
222 env->fpscr &= ~FPSCR_CAUSE_MASK; in update_fpscr()
226 env->fpscr |= FPSCR_CAUSE_V; in update_fpscr()
229 env->fpscr |= FPSCR_CAUSE_Z; in update_fpscr()
232 env->fpscr |= FPSCR_CAUSE_O; in update_fpscr()
235 env->fpscr |= FPSCR_CAUSE_U; in update_fpscr()
238 env->fpscr |= FPSCR_CAUSE_I; in update_fpscr()
242 env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK) in update_fpscr()
246 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; in update_fpscr()
247 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; in update_fpscr()
H A Dgdbstub.c57 return gdb_get_regl(mem_buf, env->fpscr); in superh_cpu_gdb_read_register()
59 if (env->fpscr & FPSCR_FR) { in superh_cpu_gdb_read_register()
116 env->fpscr = ldl_p(mem_buf); in superh_cpu_gdb_write_register()
119 if (env->fpscr & FPSCR_FR) { in superh_cpu_gdb_write_register()
H A Dcpu.c52 | (env->fpscr & TB_FLAG_FPSCR_MASK) in superh_get_tb_cpu_state()
144 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ in superh_cpu_reset_hold()
149 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ in superh_cpu_reset_hold()
H A Dcpu.h159 uint32_t fpscr; /* floating point status/control register */ member
/qemu/target/ppc/translate/
H A Dfp-impl.c.inc483 /* FEX and VX need to be updated, so don't set fpscr directly */
490 TCGv_i64 fpscr = tcg_temp_new_i64();
493 tcg_gen_extu_tl_i64(fpscr, cpu_fpscr);
494 tcg_gen_andi_i64(fpscr_masked, fpscr, mask);
497 return fpscr;
500 static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask,
506 tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask);
541 TCGv_i64 fpscr;
546 fpscr = place_from_fpscr(a->rt, UINT64_MAX);
547 store_fpscr_masked(fpscr, FP_ENABLES, tcg_constant_i64(0), 0x0003);
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/qemu/linux-user/ppc/
H A Dsignal.c302 __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); in save_user_regs()
405 uint64_t fpscr; in restore_user_regs() local
410 __get_user(fpscr, &frame->mc_fregs[32]); in restore_user_regs()
411 env->fpscr = (uint32_t) fpscr; in restore_user_regs()
452 env->fpscr = 0; in setup_frame()
525 env->fpscr = 0; in setup_rt_frame()
/qemu/bsd-user/arm/
H A Dsignal.c145 uint32_t fpscr, mask; in set_mcontext() local
201 __get_user(fpscr, &vfp->mcv_fpscr); in set_mcontext()
202 vfp_set_fpscr(env, fpscr); in set_mcontext()
/qemu/linux-user/arm/
H A Dsignal.c63 abi_ulong fpscr; member
263 __put_user(vfp_get_fpscr(env), &vfpframe->ufp.fpscr); in setup_sigframe_vfp()
412 uint32_t fpscr, fpexc; in restore_sigframe_vfp() local
424 __get_user(fpscr, &vfpframe->ufp.fpscr); in restore_sigframe_vfp()
425 vfp_set_fpscr(env, fpscr); in restore_sigframe_vfp()
/qemu/linux-user/sh4/
H A Dsignal.c140 __put_user(regs->fpscr, &sc->sc_fpscr); in setup_sigcontext()
168 __get_user(regs->fpscr, &sc->sc_fpscr); in restore_sigcontext()
/qemu/target/arm/
H A Darch_dump.c304 uint32_t fpscr; member
349 note.vfp.fpscr = cpu_to_dump32(s, vfp_get_fpscr(env)); in arm_write_elf32_vfp()
H A Dmachine.c70 uint32_t fpscr = vfp_fpcr_fpsr_needed(opaque) ? 0 : vfp_get_fpscr(env); in put_fpscr() local
72 qemu_put_be32(f, fpscr); in put_fpscr()
/qemu/include/hw/ppc/
H A Dspapr_nested.h543 uint64_t fpscr; member
/qemu/hw/ppc/
H A Dspapr_nested.c214 save->fpscr = env->fpscr; in nested_save_state()
313 ppc_store_fpscr(env, load->fpscr); in nested_load_state()
1015 GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr),

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