Lines Matching refs:fpscr
163 env->fpscr = (env->fpscr & ~FP_FPRF) | fprf; \
175 env->fpscr |= FP_VX; in COMPUTE_FPRF()
177 env->fpscr |= FP_FX; in COMPUTE_FPRF()
178 if (env->fpscr & FP_VE) { in COMPUTE_FPRF()
180 env->fpscr |= FP_FEX; in COMPUTE_FPRF()
191 env->fpscr &= ~(FP_FR | FP_FI); in finish_invalid_op_arith()
192 if (!(env->fpscr & FP_VE)) { in finish_invalid_op_arith()
194 env->fpscr &= ~FP_FPCC; in finish_invalid_op_arith()
195 env->fpscr |= (FP_C | FP_FU); in finish_invalid_op_arith()
204 env->fpscr |= FP_VXSNAN; in float_invalid_op_vxsnan()
212 env->fpscr |= FP_VXISI; in float_invalid_op_vxisi()
220 env->fpscr |= FP_VXIDI; in float_invalid_op_vxidi()
228 env->fpscr |= FP_VXZDZ; in float_invalid_op_vxzdz()
236 env->fpscr |= FP_VXIMZ; in float_invalid_op_vximz()
244 env->fpscr |= FP_VXSQRT; in float_invalid_op_vxsqrt()
252 env->fpscr |= FP_VXVC; in float_invalid_op_vxvc()
254 env->fpscr &= ~FP_FPCC; in float_invalid_op_vxvc()
255 env->fpscr |= (FP_C | FP_FU); in float_invalid_op_vxvc()
258 env->fpscr |= FP_VX; in float_invalid_op_vxvc()
260 env->fpscr |= FP_FX; in float_invalid_op_vxvc()
262 if (env->fpscr & FP_VE) { in float_invalid_op_vxvc()
268 env->fpscr |= FP_FEX; in float_invalid_op_vxvc()
277 env->fpscr |= FP_VXCVI; in float_invalid_op_vxcvi()
278 env->fpscr &= ~(FP_FR | FP_FI); in float_invalid_op_vxcvi()
279 if (!(env->fpscr & FP_VE)) { in float_invalid_op_vxcvi()
281 env->fpscr &= ~FP_FPCC; in float_invalid_op_vxcvi()
282 env->fpscr |= (FP_C | FP_FU); in float_invalid_op_vxcvi()
290 env->fpscr |= FP_ZX; in float_zero_divide_excp()
291 env->fpscr &= ~(FP_FR | FP_FI); in float_zero_divide_excp()
293 env->fpscr |= FP_FX; in float_zero_divide_excp()
294 if (env->fpscr & FP_ZE) { in float_zero_divide_excp()
296 env->fpscr |= FP_FEX; in float_zero_divide_excp()
309 env->fpscr |= FP_OX; in float_overflow_excp()
311 env->fpscr |= FP_FX; in float_overflow_excp()
313 bool overflow_enabled = !!(env->fpscr & FP_OE); in float_overflow_excp()
316 env->fpscr |= FP_FEX; in float_overflow_excp()
329 env->fpscr |= FP_UX; in float_underflow_excp()
331 env->fpscr |= FP_FX; in float_underflow_excp()
332 if (env->fpscr & FP_UE) { in float_underflow_excp()
334 env->fpscr |= FP_FEX; in float_underflow_excp()
345 env->fpscr |= FP_XX; in float_inexact_excp()
347 env->fpscr |= FP_FX; in float_inexact_excp()
348 if (env->fpscr & FP_XE) { in float_inexact_excp()
350 env->fpscr |= FP_FEX; in float_inexact_excp()
360 if (env->fpscr & mask) { in helper_fpscr_clrbit()
361 ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask); in helper_fpscr_clrbit()
368 if (!(env->fpscr & mask)) { in helper_fpscr_setbit()
369 ppc_store_fpscr(env, env->fpscr | mask); in helper_fpscr_setbit()
384 val = (val & mask) | (env->fpscr & ~mask); in helper_store_fpscr()
391 target_ulong fpscr = env->fpscr; in do_fpscr_check_status() local
394 if ((fpscr & FP_OX) && (fpscr & FP_OE)) { in do_fpscr_check_status()
396 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { in do_fpscr_check_status()
398 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { in do_fpscr_check_status()
400 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { in do_fpscr_check_status()
402 } else if (fpscr & FP_VE) { in do_fpscr_check_status()
403 if (fpscr & FP_VXSOFT) { in do_fpscr_check_status()
405 } else if (fpscr & FP_VXSNAN) { in do_fpscr_check_status()
407 } else if (fpscr & FP_VXISI) { in do_fpscr_check_status()
409 } else if (fpscr & FP_VXIDI) { in do_fpscr_check_status()
411 } else if (fpscr & FP_VXZDZ) { in do_fpscr_check_status()
413 } else if (fpscr & FP_VXIMZ) { in do_fpscr_check_status()
415 } else if (fpscr & FP_VXVC) { in do_fpscr_check_status()
417 } else if (fpscr & FP_VXSQRT) { in do_fpscr_check_status()
419 } else if (fpscr & FP_VXCVI) { in do_fpscr_check_status()
429 env->fpscr |= FP_FEX; in do_fpscr_check_status()
457 env->fpscr = FIELD_DP64(env->fpscr, FPSCR, FI, in do_float_check_status()
547 env->fpscr |= FP_VXSNAN; in float_invalid_cvt()
894 env->fpscr &= ~FP_FPCC; in helper_fcmpu()
895 env->fpscr |= ret << FPSCR_FPCC; in helper_fcmpu()
925 env->fpscr &= ~FP_FPCC; in helper_fcmpo()
926 env->fpscr |= ret << FPSCR_FPCC; in helper_fcmpo()
2150 vxvc &= !(env->fpscr & FP_VE); \
2191 env->fpscr &= ~FP_FPCC; in helper_xscmpexpdp()
2192 env->fpscr |= cc << FPSCR_FPCC; in helper_xscmpexpdp()
2220 env->fpscr &= ~FP_FPCC; in helper_xscmpexpqp()
2221 env->fpscr |= cc << FPSCR_FPCC; in helper_xscmpexpqp()
2251 if (!(env->fpscr & FP_VE) && ordered) { in do_scalar_cmp()
2266 env->fpscr &= ~FP_FPCC; in do_scalar_cmp()
2267 env->fpscr |= cc << FPSCR_FPCC; in do_scalar_cmp()
2316 if (!(env->fpscr & FP_VE) && ordered) { in do_scalar_cmpq()
2331 env->fpscr &= ~FP_FPCC; in do_scalar_cmpq()
2332 env->fpscr |= cc << FPSCR_FPCC; in do_scalar_cmpq()
2466 vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \
3171 env->fpscr &= ~FP_FPCC; \
3172 env->fpscr |= cc << FPSCR_FPCC; \
3188 env->fpscr &= ~FP_FPCC; in VSX_XS_TSTDC()
3189 env->fpscr |= cc << FPSCR_FPCC; in VSX_XS_TSTDC()
3208 rmode = env->fpscr & FP_RN; in helper_xsrqpi()
3262 rmode = env->fpscr & FP_RN; in helper_xsrqpxp()
3358 enable = env->fpscr & (FP_ENABLES | FP_FI | FP_FR); in vsxger_excp()
3359 env->fpscr &= ~(FP_ENABLES | FP_FI | FP_FR); in vsxger_excp()
3373 env->fpscr |= enable; in vsxger_excp()