1 /*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "qemu/osdep.h"
18 #include <dirent.h>
19 #include <sys/ioctl.h>
20 #include <sys/vfs.h>
21
22 #include <linux/kvm.h>
23
24 #include "qapi/error.h"
25 #include "qemu/error-report.h"
26 #include "cpu.h"
27 #include "cpu-models.h"
28 #include "qemu/timer.h"
29 #include "system/hw_accel.h"
30 #include "kvm_ppc.h"
31 #include "system/cpus.h"
32 #include "system/device_tree.h"
33 #include "mmu-hash64.h"
34
35 #include "hw/ppc/spapr.h"
36 #include "hw/ppc/spapr_cpu_core.h"
37 #include "hw/hw.h"
38 #include "hw/ppc/ppc.h"
39 #include "migration/qemu-file-types.h"
40 #include "system/watchdog.h"
41 #include "trace.h"
42 #include "gdbstub/enums.h"
43 #include "exec/memattrs.h"
44 #include "system/ram_addr.h"
45 #include "system/hostmem.h"
46 #include "qemu/cutils.h"
47 #include "qemu/main-loop.h"
48 #include "qemu/mmap-alloc.h"
49 #include "elf.h"
50 #include "system/kvm_int.h"
51 #include "system/kvm.h"
52 #include "accel/accel-cpu-target.h"
53
54 #include CONFIG_DEVICES
55
56 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
57
58 #define DEBUG_RETURN_GUEST 0
59 #define DEBUG_RETURN_GDB 1
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_LAST_INFO
63 };
64
65 static int cap_interrupt_unset;
66 static int cap_segstate;
67 static int cap_booke_sregs;
68 static int cap_ppc_smt;
69 static int cap_ppc_smt_possible;
70 static int cap_spapr_tce;
71 static int cap_spapr_tce_64;
72 static int cap_spapr_multitce;
73 static int cap_spapr_vfio;
74 static int cap_hior;
75 static int cap_one_reg;
76 static int cap_epr;
77 static int cap_ppc_watchdog;
78 static int cap_htab_fd;
79 static int cap_fixup_hcalls;
80 static int cap_htm; /* Hardware transactional memory support */
81 static int cap_mmu_radix;
82 static int cap_mmu_hash_v3;
83 static int cap_xive;
84 static int cap_resize_hpt;
85 static int cap_ppc_pvr_compat;
86 static int cap_ppc_safe_cache;
87 static int cap_ppc_safe_bounds_check;
88 static int cap_ppc_safe_indirect_branch;
89 static int cap_ppc_count_cache_flush_assist;
90 static int cap_ppc_nested_kvm_hv;
91 static int cap_large_decr;
92 static int cap_fwnmi;
93 static int cap_rpt_invalidate;
94 static int cap_ail_mode_3;
95 static int cap_dawr1;
96
97 #ifdef CONFIG_PSERIES
98 static int cap_papr;
99 #else
100 #define cap_papr (0)
101 #endif
102
103 static uint32_t debug_inst_opcode;
104
105 /*
106 * Check whether we are running with KVM-PR (instead of KVM-HV). This
107 * should only be used for fallback tests - generally we should use
108 * explicit capabilities for the features we want, rather than
109 * assuming what is/isn't available depending on the KVM variant.
110 */
kvmppc_is_pr(KVMState * ks)111 static bool kvmppc_is_pr(KVMState *ks)
112 {
113 /* Assume KVM-PR if the GET_PVINFO capability is available */
114 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
115 }
116
117 static int kvm_ppc_register_host_cpu_type(void);
118 static void kvmppc_get_cpu_characteristics(KVMState *s);
119 static int kvmppc_get_dec_bits(void);
120
kvm_arch_get_default_type(MachineState * ms)121 int kvm_arch_get_default_type(MachineState *ms)
122 {
123 return 0;
124 }
125
kvm_arch_init(MachineState * ms,KVMState * s)126 int kvm_arch_init(MachineState *ms, KVMState *s)
127 {
128 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
129 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
130 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
131 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
132 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
133 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
134 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
135 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
136 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
137 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
138 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
139 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
140 /*
141 * Note: we don't set cap_papr here, because this capability is
142 * only activated after this by kvmppc_set_papr()
143 */
144 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
145 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
146 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
147 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
148 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
149 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
150 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
151 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
152 kvmppc_get_cpu_characteristics(s);
153 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
154 cap_large_decr = kvmppc_get_dec_bits();
155 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
156 cap_dawr1 = kvm_vm_check_extension(s, KVM_CAP_PPC_DAWR1);
157 /*
158 * Note: setting it to false because there is not such capability
159 * in KVM at this moment.
160 *
161 * TODO: call kvm_vm_check_extension() with the right capability
162 * after the kernel starts implementing it.
163 */
164 cap_ppc_pvr_compat = false;
165
166 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
167 error_report("KVM: Host kernel doesn't have level irq capability");
168 exit(1);
169 }
170
171 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
172 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3);
173 kvm_ppc_register_host_cpu_type();
174
175 return 0;
176 }
177
kvm_arch_irqchip_create(KVMState * s)178 int kvm_arch_irqchip_create(KVMState *s)
179 {
180 return 0;
181 }
182
kvm_arch_sync_sregs(PowerPCCPU * cpu)183 static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
184 {
185 CPUPPCState *cenv = &cpu->env;
186 CPUState *cs = CPU(cpu);
187 struct kvm_sregs sregs;
188 int ret;
189
190 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
191 /*
192 * What we're really trying to say is "if we're on BookE, we
193 * use the native PVR for now". This is the only sane way to
194 * check it though, so we potentially confuse users that they
195 * can run BookE guests on BookS. Let's hope nobody dares
196 * enough :)
197 */
198 return 0;
199 } else {
200 if (!cap_segstate) {
201 fprintf(stderr, "kvm error: missing PVR setting capability\n");
202 return -ENOSYS;
203 }
204 }
205
206 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
207 if (ret) {
208 return ret;
209 }
210
211 sregs.pvr = cenv->spr[SPR_PVR];
212 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
213 }
214
215 /* Set up a shared TLB array with KVM */
kvm_booke206_tlb_init(PowerPCCPU * cpu)216 static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
217 {
218 CPUPPCState *env = &cpu->env;
219 CPUState *cs = CPU(cpu);
220 struct kvm_book3e_206_tlb_params params = {};
221 struct kvm_config_tlb cfg = {};
222 unsigned int entries = 0;
223 int ret, i;
224
225 if (!kvm_enabled() ||
226 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
227 return 0;
228 }
229
230 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
231
232 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
233 params.tlb_sizes[i] = booke206_tlb_size(env, i);
234 params.tlb_ways[i] = booke206_tlb_ways(env, i);
235 entries += params.tlb_sizes[i];
236 }
237
238 assert(entries == env->nb_tlb);
239 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
240
241 env->tlb_dirty = true;
242
243 cfg.array = (uintptr_t)env->tlb.tlbm;
244 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
245 cfg.params = (uintptr_t)¶ms;
246 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
247
248 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
249 if (ret < 0) {
250 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
251 __func__, strerror(-ret));
252 return ret;
253 }
254
255 env->kvm_sw_tlb = true;
256 return 0;
257 }
258
259
260 #if defined(TARGET_PPC64)
kvm_get_smmu_info(struct kvm_ppc_smmu_info * info,Error ** errp)261 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
262 {
263 int ret;
264
265 assert(kvm_state != NULL);
266
267 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
268 error_setg(errp, "KVM doesn't expose the MMU features it supports");
269 error_append_hint(errp, "Consider switching to a newer KVM\n");
270 return;
271 }
272
273 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
274 if (ret == 0) {
275 return;
276 }
277
278 error_setg_errno(errp, -ret,
279 "KVM failed to provide the MMU features it supports");
280 }
281
kvmppc_get_radix_page_info(void)282 static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void)
283 {
284 KVMState *s = KVM_STATE(current_accel());
285 struct ppc_radix_page_info *radix_page_info;
286 struct kvm_ppc_rmmu_info rmmu_info = { };
287 int i;
288
289 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
290 return NULL;
291 }
292 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
293 return NULL;
294 }
295 radix_page_info = g_malloc0(sizeof(*radix_page_info));
296 radix_page_info->count = 0;
297 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
298 if (rmmu_info.ap_encodings[i]) {
299 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
300 radix_page_info->count++;
301 }
302 }
303 return radix_page_info;
304 }
305
kvmppc_configure_v3_mmu(PowerPCCPU * cpu,bool radix,bool gtse,uint64_t proc_tbl)306 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
307 bool radix, bool gtse,
308 uint64_t proc_tbl)
309 {
310 CPUState *cs = CPU(cpu);
311 int ret;
312 uint64_t flags = 0;
313 struct kvm_ppc_mmuv3_cfg cfg = {
314 .process_table = proc_tbl,
315 };
316
317 if (radix) {
318 flags |= KVM_PPC_MMUV3_RADIX;
319 }
320 if (gtse) {
321 flags |= KVM_PPC_MMUV3_GTSE;
322 }
323 cfg.flags = flags;
324 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
325 switch (ret) {
326 case 0:
327 return H_SUCCESS;
328 case -EINVAL:
329 return H_PARAMETER;
330 case -ENODEV:
331 return H_NOT_AVAILABLE;
332 default:
333 return H_HARDWARE;
334 }
335 }
336
kvmppc_hpt_needs_host_contiguous_pages(void)337 bool kvmppc_hpt_needs_host_contiguous_pages(void)
338 {
339 static struct kvm_ppc_smmu_info smmu_info;
340
341 if (!kvm_enabled()) {
342 return false;
343 }
344
345 kvm_get_smmu_info(&smmu_info, &error_fatal);
346 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
347 }
348
kvm_check_mmu(PowerPCCPU * cpu,Error ** errp)349 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
350 {
351 struct kvm_ppc_smmu_info smmu_info;
352 int iq, ik, jq, jk;
353 Error *local_err = NULL;
354
355 /* For now, we only have anything to check on hash64 MMUs */
356 if (!cpu->hash64_opts || !kvm_enabled()) {
357 return;
358 }
359
360 kvm_get_smmu_info(&smmu_info, &local_err);
361 if (local_err) {
362 error_propagate(errp, local_err);
363 return;
364 }
365
366 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
367 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
368 error_setg(errp,
369 "KVM does not support 1TiB segments which guest expects");
370 return;
371 }
372
373 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
374 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
375 smmu_info.slb_size, cpu->hash64_opts->slb_size);
376 return;
377 }
378
379 /*
380 * Verify that every pagesize supported by the cpu model is
381 * supported by KVM with the same encodings
382 */
383 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
384 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
385 struct kvm_ppc_one_seg_page_size *ksps;
386
387 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
388 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
389 break;
390 }
391 }
392 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
393 error_setg(errp, "KVM doesn't support for base page shift %u",
394 qsps->page_shift);
395 return;
396 }
397
398 ksps = &smmu_info.sps[ik];
399 if (ksps->slb_enc != qsps->slb_enc) {
400 error_setg(errp,
401 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
402 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
403 return;
404 }
405
406 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
407 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
408 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
409 break;
410 }
411 }
412
413 if (jk >= ARRAY_SIZE(ksps->enc)) {
414 error_setg(errp, "KVM doesn't support page shift %u/%u",
415 qsps->enc[jq].page_shift, qsps->page_shift);
416 return;
417 }
418 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
419 error_setg(errp,
420 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
421 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
422 qsps->page_shift, qsps->enc[jq].pte_enc);
423 return;
424 }
425 }
426 }
427
428 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
429 /*
430 * Mostly what guest pagesizes we can use are related to the
431 * host pages used to map guest RAM, which is handled in the
432 * platform code. Cache-Inhibited largepages (64k) however are
433 * used for I/O, so if they're mapped to the host at all it
434 * will be a normal mapping, not a special hugepage one used
435 * for RAM.
436 */
437 if (qemu_real_host_page_size() < 0x10000) {
438 error_setg(errp,
439 "KVM can't supply 64kiB CI pages, which guest expects");
440 }
441 }
442 }
443 #endif /* !defined (TARGET_PPC64) */
444
kvm_arch_vcpu_id(CPUState * cpu)445 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
446 {
447 return POWERPC_CPU(cpu)->vcpu_id;
448 }
449
450 /*
451 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
452 * only 1 watchpoint, so array size of 4 is sufficient for now.
453 */
454 #define MAX_HW_BKPTS 4
455
456 static struct HWBreakpoint {
457 target_ulong addr;
458 int type;
459 } hw_debug_points[MAX_HW_BKPTS];
460
461 static CPUWatchpoint hw_watchpoint;
462
463 /* Default there is no breakpoint and watchpoint supported */
464 static int max_hw_breakpoint;
465 static int max_hw_watchpoint;
466 static int nb_hw_breakpoint;
467 static int nb_hw_watchpoint;
468
kvmppc_hw_debug_points_init(CPUPPCState * cenv)469 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
470 {
471 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
472 max_hw_breakpoint = 2;
473 max_hw_watchpoint = 2;
474 }
475
476 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
477 fprintf(stderr, "Error initializing h/w breakpoints\n");
478 return;
479 }
480 }
481
kvm_arch_pre_create_vcpu(CPUState * cpu,Error ** errp)482 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp)
483 {
484 return 0;
485 }
486
kvm_arch_init_vcpu(CPUState * cs)487 int kvm_arch_init_vcpu(CPUState *cs)
488 {
489 PowerPCCPU *cpu = POWERPC_CPU(cs);
490 CPUPPCState *cenv = &cpu->env;
491 int ret;
492
493 /* Synchronize sregs with kvm */
494 ret = kvm_arch_sync_sregs(cpu);
495 if (ret) {
496 if (ret == -EINVAL) {
497 error_report("Register sync failed... If you're using kvm-hv.ko,"
498 " only \"-cpu host\" is possible");
499 }
500 return ret;
501 }
502
503 switch (cenv->mmu_model) {
504 case POWERPC_MMU_BOOKE206:
505 /* This target supports access to KVM's guest TLB */
506 ret = kvm_booke206_tlb_init(cpu);
507 break;
508 case POWERPC_MMU_2_07:
509 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
510 /*
511 * KVM-HV has transactional memory on POWER8 also without
512 * the KVM_CAP_PPC_HTM extension, so enable it here
513 * instead as long as it's available to userspace on the
514 * host.
515 */
516 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
517 cap_htm = true;
518 }
519 }
520 break;
521 default:
522 break;
523 }
524
525 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
526 kvmppc_hw_debug_points_init(cenv);
527
528 return ret;
529 }
530
kvm_arch_destroy_vcpu(CPUState * cs)531 int kvm_arch_destroy_vcpu(CPUState *cs)
532 {
533 return 0;
534 }
535
kvm_sw_tlb_put(PowerPCCPU * cpu)536 static void kvm_sw_tlb_put(PowerPCCPU *cpu)
537 {
538 CPUPPCState *env = &cpu->env;
539 CPUState *cs = CPU(cpu);
540 struct kvm_dirty_tlb dirty_tlb;
541 unsigned char *bitmap;
542 int ret;
543
544 if (!env->kvm_sw_tlb) {
545 return;
546 }
547
548 bitmap = g_malloc((env->nb_tlb + 7) / 8);
549 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
550
551 dirty_tlb.bitmap = (uintptr_t)bitmap;
552 dirty_tlb.num_dirty = env->nb_tlb;
553
554 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
555 if (ret) {
556 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
557 __func__, strerror(-ret));
558 }
559
560 g_free(bitmap);
561 }
562
kvm_get_one_spr(CPUState * cs,uint64_t id,int spr)563 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
564 {
565 CPUPPCState *env = cpu_env(cs);
566 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */
567 union {
568 uint32_t u32;
569 uint64_t u64;
570 } val = { };
571 struct kvm_one_reg reg = {
572 .id = id,
573 .addr = (uintptr_t) &val,
574 };
575 int ret;
576
577 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
578 if (ret != 0) {
579 trace_kvm_failed_spr_get(spr, strerror(errno));
580 } else {
581 switch (id & KVM_REG_SIZE_MASK) {
582 case KVM_REG_SIZE_U32:
583 env->spr[spr] = val.u32;
584 break;
585
586 case KVM_REG_SIZE_U64:
587 env->spr[spr] = val.u64;
588 break;
589
590 default:
591 /* Don't handle this size yet */
592 abort();
593 }
594 }
595 }
596
kvm_put_one_spr(CPUState * cs,uint64_t id,int spr)597 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
598 {
599 CPUPPCState *env = cpu_env(cs);
600 union {
601 uint32_t u32;
602 uint64_t u64;
603 } val;
604 struct kvm_one_reg reg = {
605 .id = id,
606 .addr = (uintptr_t) &val,
607 };
608 int ret;
609
610 switch (id & KVM_REG_SIZE_MASK) {
611 case KVM_REG_SIZE_U32:
612 val.u32 = env->spr[spr];
613 break;
614
615 case KVM_REG_SIZE_U64:
616 val.u64 = env->spr[spr];
617 break;
618
619 default:
620 /* Don't handle this size yet */
621 abort();
622 }
623
624 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
625 if (ret != 0) {
626 trace_kvm_failed_spr_set(spr, strerror(errno));
627 }
628 }
629
kvm_put_fp(CPUState * cs)630 static int kvm_put_fp(CPUState *cs)
631 {
632 CPUPPCState *env = cpu_env(cs);
633 struct kvm_one_reg reg;
634 int i;
635 int ret;
636
637 if (env->insns_flags & PPC_FLOAT) {
638 uint64_t fpscr = env->fpscr;
639 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
640
641 reg.id = KVM_REG_PPC_FPSCR;
642 reg.addr = (uintptr_t)&fpscr;
643 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
644 if (ret < 0) {
645 trace_kvm_failed_fpscr_set(strerror(errno));
646 return ret;
647 }
648
649 for (i = 0; i < 32; i++) {
650 uint64_t vsr[2];
651 uint64_t *fpr = cpu_fpr_ptr(env, i);
652 uint64_t *vsrl = cpu_vsrl_ptr(env, i);
653
654 #if HOST_BIG_ENDIAN
655 vsr[0] = float64_val(*fpr);
656 vsr[1] = *vsrl;
657 #else
658 vsr[0] = *vsrl;
659 vsr[1] = float64_val(*fpr);
660 #endif
661 reg.addr = (uintptr_t) &vsr;
662 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
663
664 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
665 if (ret < 0) {
666 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
667 strerror(errno));
668 return ret;
669 }
670 }
671 }
672
673 if (env->insns_flags & PPC_ALTIVEC) {
674 reg.id = KVM_REG_PPC_VSCR;
675 reg.addr = (uintptr_t)&env->vscr;
676 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
677 if (ret < 0) {
678 trace_kvm_failed_vscr_set(strerror(errno));
679 return ret;
680 }
681
682 for (i = 0; i < 32; i++) {
683 reg.id = KVM_REG_PPC_VR(i);
684 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
685 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
686 if (ret < 0) {
687 trace_kvm_failed_vr_set(i, strerror(errno));
688 return ret;
689 }
690 }
691 }
692
693 return 0;
694 }
695
kvm_get_fp(CPUState * cs)696 static int kvm_get_fp(CPUState *cs)
697 {
698 CPUPPCState *env = cpu_env(cs);
699 struct kvm_one_reg reg;
700 int i;
701 int ret;
702
703 if (env->insns_flags & PPC_FLOAT) {
704 uint64_t fpscr;
705 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
706
707 reg.id = KVM_REG_PPC_FPSCR;
708 reg.addr = (uintptr_t)&fpscr;
709 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
710 if (ret < 0) {
711 trace_kvm_failed_fpscr_get(strerror(errno));
712 return ret;
713 } else {
714 env->fpscr = fpscr;
715 }
716
717 for (i = 0; i < 32; i++) {
718 uint64_t vsr[2];
719 uint64_t *fpr = cpu_fpr_ptr(env, i);
720 uint64_t *vsrl = cpu_vsrl_ptr(env, i);
721
722 reg.addr = (uintptr_t) &vsr;
723 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
724
725 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
726 if (ret < 0) {
727 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
728 strerror(errno));
729 return ret;
730 } else {
731 #if HOST_BIG_ENDIAN
732 *fpr = vsr[0];
733 if (vsx) {
734 *vsrl = vsr[1];
735 }
736 #else
737 *fpr = vsr[1];
738 if (vsx) {
739 *vsrl = vsr[0];
740 }
741 #endif
742 }
743 }
744 }
745
746 if (env->insns_flags & PPC_ALTIVEC) {
747 reg.id = KVM_REG_PPC_VSCR;
748 reg.addr = (uintptr_t)&env->vscr;
749 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
750 if (ret < 0) {
751 trace_kvm_failed_vscr_get(strerror(errno));
752 return ret;
753 }
754
755 for (i = 0; i < 32; i++) {
756 reg.id = KVM_REG_PPC_VR(i);
757 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
758 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
759 if (ret < 0) {
760 trace_kvm_failed_vr_get(i, strerror(errno));
761 return ret;
762 }
763 }
764 }
765
766 return 0;
767 }
768
769 #if defined(TARGET_PPC64)
kvm_get_vpa(CPUState * cs)770 static int kvm_get_vpa(CPUState *cs)
771 {
772 PowerPCCPU *cpu = POWERPC_CPU(cs);
773 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
774 struct kvm_one_reg reg;
775 int ret;
776
777 reg.id = KVM_REG_PPC_VPA_ADDR;
778 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
779 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
780 if (ret < 0) {
781 trace_kvm_failed_vpa_addr_get(strerror(errno));
782 return ret;
783 }
784
785 assert((uintptr_t)&spapr_cpu->slb_shadow_size
786 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
787 reg.id = KVM_REG_PPC_VPA_SLB;
788 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
789 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
790 if (ret < 0) {
791 trace_kvm_failed_slb_get(strerror(errno));
792 return ret;
793 }
794
795 assert((uintptr_t)&spapr_cpu->dtl_size
796 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
797 reg.id = KVM_REG_PPC_VPA_DTL;
798 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
799 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
800 if (ret < 0) {
801 trace_kvm_failed_dtl_get(strerror(errno));
802 return ret;
803 }
804
805 return 0;
806 }
807
kvm_put_vpa(CPUState * cs)808 static int kvm_put_vpa(CPUState *cs)
809 {
810 PowerPCCPU *cpu = POWERPC_CPU(cs);
811 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
812 struct kvm_one_reg reg;
813 int ret;
814
815 /*
816 * SLB shadow or DTL can't be registered unless a master VPA is
817 * registered. That means when restoring state, if a VPA *is*
818 * registered, we need to set that up first. If not, we need to
819 * deregister the others before deregistering the master VPA
820 */
821 assert(spapr_cpu->vpa_addr
822 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
823
824 if (spapr_cpu->vpa_addr) {
825 reg.id = KVM_REG_PPC_VPA_ADDR;
826 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
827 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
828 if (ret < 0) {
829 trace_kvm_failed_vpa_addr_set(strerror(errno));
830 return ret;
831 }
832 }
833
834 assert((uintptr_t)&spapr_cpu->slb_shadow_size
835 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
836 reg.id = KVM_REG_PPC_VPA_SLB;
837 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
838 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
839 if (ret < 0) {
840 trace_kvm_failed_slb_set(strerror(errno));
841 return ret;
842 }
843
844 assert((uintptr_t)&spapr_cpu->dtl_size
845 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
846 reg.id = KVM_REG_PPC_VPA_DTL;
847 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
848 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
849 if (ret < 0) {
850 trace_kvm_failed_dtl_set(strerror(errno));
851 return ret;
852 }
853
854 if (!spapr_cpu->vpa_addr) {
855 reg.id = KVM_REG_PPC_VPA_ADDR;
856 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
857 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
858 if (ret < 0) {
859 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
860 return ret;
861 }
862 }
863
864 return 0;
865 }
866 #endif /* TARGET_PPC64 */
867
kvmppc_put_books_sregs(PowerPCCPU * cpu)868 int kvmppc_put_books_sregs(PowerPCCPU *cpu)
869 {
870 CPUPPCState *env = &cpu->env;
871 struct kvm_sregs sregs = { };
872 int i;
873
874 sregs.pvr = env->spr[SPR_PVR];
875
876 if (cpu->vhyp) {
877 sregs.u.s.sdr1 = cpu->vhyp_class->encode_hpt_for_kvm_pr(cpu->vhyp);
878 } else {
879 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
880 }
881
882 /* Sync SLB */
883 #ifdef TARGET_PPC64
884 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
885 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
886 if (env->slb[i].esid & SLB_ESID_V) {
887 sregs.u.s.ppc64.slb[i].slbe |= i;
888 }
889 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
890 }
891 #endif
892
893 /* Sync SRs */
894 for (i = 0; i < 16; i++) {
895 sregs.u.s.ppc32.sr[i] = env->sr[i];
896 }
897
898 /* Sync BATs */
899 for (i = 0; i < 8; i++) {
900 /* Beware. We have to swap upper and lower bits here */
901 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
902 | env->DBAT[1][i];
903 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
904 | env->IBAT[1][i];
905 }
906
907 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
908 }
909
kvm_arch_put_registers(CPUState * cs,int level,Error ** errp)910 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp)
911 {
912 PowerPCCPU *cpu = POWERPC_CPU(cs);
913 CPUPPCState *env = &cpu->env;
914 struct kvm_regs regs;
915 int ret;
916 int i;
917
918 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
919 if (ret < 0) {
920 return ret;
921 }
922
923 regs.ctr = env->ctr;
924 regs.lr = env->lr;
925 regs.xer = cpu_read_xer(env);
926 regs.msr = env->msr;
927 regs.pc = env->nip;
928
929 regs.srr0 = env->spr[SPR_SRR0];
930 regs.srr1 = env->spr[SPR_SRR1];
931
932 regs.sprg0 = env->spr[SPR_SPRG0];
933 regs.sprg1 = env->spr[SPR_SPRG1];
934 regs.sprg2 = env->spr[SPR_SPRG2];
935 regs.sprg3 = env->spr[SPR_SPRG3];
936 regs.sprg4 = env->spr[SPR_SPRG4];
937 regs.sprg5 = env->spr[SPR_SPRG5];
938 regs.sprg6 = env->spr[SPR_SPRG6];
939 regs.sprg7 = env->spr[SPR_SPRG7];
940
941 regs.pid = env->spr[SPR_BOOKE_PID];
942
943 for (i = 0; i < 32; i++) {
944 regs.gpr[i] = env->gpr[i];
945 }
946
947 regs.cr = ppc_get_cr(env);
948
949 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
950 if (ret < 0) {
951 return ret;
952 }
953
954 kvm_put_fp(cs);
955
956 if (env->tlb_dirty) {
957 kvm_sw_tlb_put(cpu);
958 env->tlb_dirty = false;
959 }
960
961 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
962 ret = kvmppc_put_books_sregs(cpu);
963 if (ret < 0) {
964 return ret;
965 }
966 }
967
968 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
969 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
970 }
971
972 if (cap_one_reg) {
973 /*
974 * We deliberately ignore errors here, for kernels which have
975 * the ONE_REG calls, but don't support the specific
976 * registers, there's a reasonable chance things will still
977 * work, at least until we try to migrate.
978 */
979 for (i = 0; i < 1024; i++) {
980 uint64_t id = env->spr_cb[i].one_reg_id;
981
982 if (id != 0) {
983 kvm_put_one_spr(cs, id, i);
984 }
985 }
986
987 #ifdef TARGET_PPC64
988 if (FIELD_EX64(env->msr, MSR, TS)) {
989 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
991 }
992 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
994 }
995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
997 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
999 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1000 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1001 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1002 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1003 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1004 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1005 }
1006
1007 if (cap_papr) {
1008 if (kvm_put_vpa(cs) < 0) {
1009 trace_kvm_failed_put_vpa();
1010 }
1011 }
1012
1013 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1014
1015 if (level > KVM_PUT_RUNTIME_STATE) {
1016 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1017 }
1018 #endif /* TARGET_PPC64 */
1019 }
1020
1021 return ret;
1022 }
1023
kvm_sync_excp(CPUPPCState * env,int vector,int ivor)1024 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1025 {
1026 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1027 }
1028
kvmppc_get_booke_sregs(PowerPCCPU * cpu)1029 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1030 {
1031 CPUPPCState *env = &cpu->env;
1032 struct kvm_sregs sregs;
1033 int ret;
1034
1035 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1036 if (ret < 0) {
1037 return ret;
1038 }
1039
1040 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1041 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1042 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1043 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1044 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1045 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1046 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1047 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1048 env->spr[SPR_DECR] = sregs.u.e.dec;
1049 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1050 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1051 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1052 }
1053
1054 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1055 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1056 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1057 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1058 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1059 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1060 }
1061
1062 if (sregs.u.e.features & KVM_SREGS_E_64) {
1063 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1064 }
1065
1066 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1067 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1068 }
1069
1070 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1071 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1072 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1073 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1074 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1075 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1076 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1077 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1078 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1079 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1080 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1081 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1082 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1083 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1084 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1085 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1086 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1087 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1088 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1089 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1090 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1091 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1092 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1093 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1094 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1095 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1096 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1097 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1098 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1099 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1100 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1101 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1102 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1103
1104 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1105 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1106 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1107 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1108 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1109 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1110 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1111 }
1112
1113 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1114 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1115 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1116 }
1117
1118 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1119 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1120 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1121 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1122 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1123 }
1124 }
1125
1126 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1127 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1128 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1129 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1130 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1131 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1132 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1133 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1134 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1135 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1136 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1137 }
1138
1139 if (sregs.u.e.features & KVM_SREGS_EXP) {
1140 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1141 }
1142
1143 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1144 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1145 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1146 }
1147
1148 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1149 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1150 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1151 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1152
1153 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1154 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1155 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1156 }
1157 }
1158
1159 return 0;
1160 }
1161
kvmppc_get_books_sregs(PowerPCCPU * cpu)1162 static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1163 {
1164 CPUPPCState *env = &cpu->env;
1165 struct kvm_sregs sregs;
1166 int ret;
1167 int i;
1168
1169 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1170 if (ret < 0) {
1171 return ret;
1172 }
1173
1174 if (!cpu->vhyp) {
1175 ppc_store_sdr1(env, sregs.u.s.sdr1);
1176 }
1177
1178 /* Sync SLB */
1179 #ifdef TARGET_PPC64
1180 /*
1181 * The packed SLB array we get from KVM_GET_SREGS only contains
1182 * information about valid entries. So we flush our internal copy
1183 * to get rid of stale ones, then put all valid SLB entries back
1184 * in.
1185 */
1186 memset(env->slb, 0, sizeof(env->slb));
1187 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1188 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1189 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1190 /*
1191 * Only restore valid entries
1192 */
1193 if (rb & SLB_ESID_V) {
1194 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1195 }
1196 }
1197 #endif
1198
1199 /* Sync SRs */
1200 for (i = 0; i < 16; i++) {
1201 env->sr[i] = sregs.u.s.ppc32.sr[i];
1202 }
1203
1204 /* Sync BATs */
1205 for (i = 0; i < 8; i++) {
1206 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1207 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1208 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1209 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1210 }
1211
1212 return 0;
1213 }
1214
kvm_arch_get_registers(CPUState * cs,Error ** errp)1215 int kvm_arch_get_registers(CPUState *cs, Error **errp)
1216 {
1217 PowerPCCPU *cpu = POWERPC_CPU(cs);
1218 CPUPPCState *env = &cpu->env;
1219 struct kvm_regs regs;
1220 int i, ret;
1221
1222 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
1223 if (ret < 0) {
1224 return ret;
1225 }
1226
1227 ppc_set_cr(env, regs.cr);
1228 env->ctr = regs.ctr;
1229 env->lr = regs.lr;
1230 cpu_write_xer(env, regs.xer);
1231 env->msr = regs.msr;
1232 env->nip = regs.pc;
1233
1234 env->spr[SPR_SRR0] = regs.srr0;
1235 env->spr[SPR_SRR1] = regs.srr1;
1236
1237 env->spr[SPR_SPRG0] = regs.sprg0;
1238 env->spr[SPR_SPRG1] = regs.sprg1;
1239 env->spr[SPR_SPRG2] = regs.sprg2;
1240 env->spr[SPR_SPRG3] = regs.sprg3;
1241 env->spr[SPR_SPRG4] = regs.sprg4;
1242 env->spr[SPR_SPRG5] = regs.sprg5;
1243 env->spr[SPR_SPRG6] = regs.sprg6;
1244 env->spr[SPR_SPRG7] = regs.sprg7;
1245
1246 env->spr[SPR_BOOKE_PID] = regs.pid;
1247
1248 for (i = 0; i < 32; i++) {
1249 env->gpr[i] = regs.gpr[i];
1250 }
1251
1252 kvm_get_fp(cs);
1253
1254 if (cap_booke_sregs) {
1255 ret = kvmppc_get_booke_sregs(cpu);
1256 if (ret < 0) {
1257 return ret;
1258 }
1259 }
1260
1261 if (cap_segstate) {
1262 ret = kvmppc_get_books_sregs(cpu);
1263 if (ret < 0) {
1264 return ret;
1265 }
1266 }
1267
1268 if (cap_hior) {
1269 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1270 }
1271
1272 if (cap_one_reg) {
1273 /*
1274 * We deliberately ignore errors here, for kernels which have
1275 * the ONE_REG calls, but don't support the specific
1276 * registers, there's a reasonable chance things will still
1277 * work, at least until we try to migrate.
1278 */
1279 for (i = 0; i < 1024; i++) {
1280 uint64_t id = env->spr_cb[i].one_reg_id;
1281
1282 if (id != 0) {
1283 kvm_get_one_spr(cs, id, i);
1284 }
1285 }
1286
1287 #ifdef TARGET_PPC64
1288 if (FIELD_EX64(env->msr, MSR, TS)) {
1289 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1291 }
1292 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1294 }
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1301 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1302 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1303 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1304 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1305 }
1306
1307 if (cap_papr) {
1308 if (kvm_get_vpa(cs) < 0) {
1309 trace_kvm_failed_get_vpa();
1310 }
1311 }
1312
1313 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1314 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1315 #endif
1316 }
1317
1318 return 0;
1319 }
1320
kvmppc_set_interrupt(PowerPCCPU * cpu,int irq,int level)1321 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
1322 {
1323 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1324
1325 if (irq != PPC_INTERRUPT_EXT) {
1326 return 0;
1327 }
1328
1329 if (!cap_interrupt_unset) {
1330 return 0;
1331 }
1332
1333 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
1334
1335 return 0;
1336 }
1337
kvm_arch_pre_run(CPUState * cs,struct kvm_run * run)1338 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
1339 {
1340 }
1341
kvm_arch_post_run(CPUState * cs,struct kvm_run * run)1342 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
1343 {
1344 return MEMTXATTRS_UNSPECIFIED;
1345 }
1346
kvm_arch_process_async_events(CPUState * cs)1347 int kvm_arch_process_async_events(CPUState *cs)
1348 {
1349 return cs->halted;
1350 }
1351
kvmppc_handle_halt(PowerPCCPU * cpu)1352 static int kvmppc_handle_halt(PowerPCCPU *cpu)
1353 {
1354 CPUState *cs = CPU(cpu);
1355 CPUPPCState *env = &cpu->env;
1356
1357 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1358 FIELD_EX64(env->msr, MSR, EE)) {
1359 cs->halted = 1;
1360 cs->exception_index = EXCP_HLT;
1361 }
1362
1363 return 0;
1364 }
1365
1366 /* map dcr access to existing qemu dcr emulation */
kvmppc_handle_dcr_read(CPUPPCState * env,uint32_t dcrn,uint32_t * data)1367 static int kvmppc_handle_dcr_read(CPUPPCState *env,
1368 uint32_t dcrn, uint32_t *data)
1369 {
1370 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
1371 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1372 }
1373
1374 return 0;
1375 }
1376
kvmppc_handle_dcr_write(CPUPPCState * env,uint32_t dcrn,uint32_t data)1377 static int kvmppc_handle_dcr_write(CPUPPCState *env,
1378 uint32_t dcrn, uint32_t data)
1379 {
1380 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
1381 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1382 }
1383
1384 return 0;
1385 }
1386
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)1387 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1388 {
1389 /* Mixed endian case is not handled */
1390 uint32_t sc = debug_inst_opcode;
1391
1392 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1393 sizeof(sc), 0) ||
1394 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1395 return -EINVAL;
1396 }
1397
1398 return 0;
1399 }
1400
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)1401 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1402 {
1403 uint32_t sc;
1404
1405 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1406 sc != debug_inst_opcode ||
1407 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1408 sizeof(sc), 1)) {
1409 return -EINVAL;
1410 }
1411
1412 return 0;
1413 }
1414
find_hw_breakpoint(target_ulong addr,int type)1415 static int find_hw_breakpoint(target_ulong addr, int type)
1416 {
1417 int n;
1418
1419 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1420 <= ARRAY_SIZE(hw_debug_points));
1421
1422 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1423 if (hw_debug_points[n].addr == addr &&
1424 hw_debug_points[n].type == type) {
1425 return n;
1426 }
1427 }
1428
1429 return -1;
1430 }
1431
find_hw_watchpoint(target_ulong addr,int * flag)1432 static int find_hw_watchpoint(target_ulong addr, int *flag)
1433 {
1434 int n;
1435
1436 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1437 if (n >= 0) {
1438 *flag = BP_MEM_ACCESS;
1439 return n;
1440 }
1441
1442 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1443 if (n >= 0) {
1444 *flag = BP_MEM_WRITE;
1445 return n;
1446 }
1447
1448 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1449 if (n >= 0) {
1450 *flag = BP_MEM_READ;
1451 return n;
1452 }
1453
1454 return -1;
1455 }
1456
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)1457 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
1458 {
1459 const unsigned breakpoint_index = nb_hw_breakpoint + nb_hw_watchpoint;
1460 if (breakpoint_index >= ARRAY_SIZE(hw_debug_points)) {
1461 return -ENOBUFS;
1462 }
1463
1464 hw_debug_points[breakpoint_index].addr = addr;
1465 hw_debug_points[breakpoint_index].type = type;
1466
1467 switch (type) {
1468 case GDB_BREAKPOINT_HW:
1469 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1470 return -ENOBUFS;
1471 }
1472
1473 if (find_hw_breakpoint(addr, type) >= 0) {
1474 return -EEXIST;
1475 }
1476
1477 nb_hw_breakpoint++;
1478 break;
1479
1480 case GDB_WATCHPOINT_WRITE:
1481 case GDB_WATCHPOINT_READ:
1482 case GDB_WATCHPOINT_ACCESS:
1483 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1484 return -ENOBUFS;
1485 }
1486
1487 if (find_hw_breakpoint(addr, type) >= 0) {
1488 return -EEXIST;
1489 }
1490
1491 nb_hw_watchpoint++;
1492 break;
1493
1494 default:
1495 return -ENOSYS;
1496 }
1497
1498 return 0;
1499 }
1500
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)1501 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
1502 {
1503 int n;
1504
1505 n = find_hw_breakpoint(addr, type);
1506 if (n < 0) {
1507 return -ENOENT;
1508 }
1509
1510 switch (type) {
1511 case GDB_BREAKPOINT_HW:
1512 nb_hw_breakpoint--;
1513 break;
1514
1515 case GDB_WATCHPOINT_WRITE:
1516 case GDB_WATCHPOINT_READ:
1517 case GDB_WATCHPOINT_ACCESS:
1518 nb_hw_watchpoint--;
1519 break;
1520
1521 default:
1522 return -ENOSYS;
1523 }
1524 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1525
1526 return 0;
1527 }
1528
kvm_arch_remove_all_hw_breakpoints(void)1529 void kvm_arch_remove_all_hw_breakpoints(void)
1530 {
1531 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1532 }
1533
kvm_arch_update_guest_debug(CPUState * cs,struct kvm_guest_debug * dbg)1534 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1535 {
1536 int n;
1537
1538 /* Software Breakpoint updates */
1539 if (kvm_sw_breakpoints_active(cs)) {
1540 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1541 }
1542
1543 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1544 <= ARRAY_SIZE(hw_debug_points));
1545 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1546
1547 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1548 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1549 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1550 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1551 switch (hw_debug_points[n].type) {
1552 case GDB_BREAKPOINT_HW:
1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1554 break;
1555 case GDB_WATCHPOINT_WRITE:
1556 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1557 break;
1558 case GDB_WATCHPOINT_READ:
1559 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1560 break;
1561 case GDB_WATCHPOINT_ACCESS:
1562 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1563 KVMPPC_DEBUG_WATCH_READ;
1564 break;
1565 default:
1566 cpu_abort(cs, "Unsupported breakpoint type\n");
1567 }
1568 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1569 }
1570 }
1571 }
1572
kvm_handle_hw_breakpoint(CPUState * cs,struct kvm_debug_exit_arch * arch_info)1573 static int kvm_handle_hw_breakpoint(CPUState *cs,
1574 struct kvm_debug_exit_arch *arch_info)
1575 {
1576 int handle = DEBUG_RETURN_GUEST;
1577 int n;
1578 int flag = 0;
1579
1580 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1581 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1582 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1583 if (n >= 0) {
1584 handle = DEBUG_RETURN_GDB;
1585 }
1586 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1587 KVMPPC_DEBUG_WATCH_WRITE)) {
1588 n = find_hw_watchpoint(arch_info->address, &flag);
1589 if (n >= 0) {
1590 handle = DEBUG_RETURN_GDB;
1591 cs->watchpoint_hit = &hw_watchpoint;
1592 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1593 hw_watchpoint.flags = flag;
1594 }
1595 }
1596 }
1597 return handle;
1598 }
1599
kvm_handle_singlestep(void)1600 static int kvm_handle_singlestep(void)
1601 {
1602 return DEBUG_RETURN_GDB;
1603 }
1604
kvm_handle_sw_breakpoint(void)1605 static int kvm_handle_sw_breakpoint(void)
1606 {
1607 return DEBUG_RETURN_GDB;
1608 }
1609
kvm_handle_debug(PowerPCCPU * cpu,struct kvm_run * run)1610 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1611 {
1612 CPUState *cs = CPU(cpu);
1613 CPUPPCState *env = &cpu->env;
1614 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1615
1616 if (cs->singlestep_enabled) {
1617 return kvm_handle_singlestep();
1618 }
1619
1620 if (arch_info->status) {
1621 return kvm_handle_hw_breakpoint(cs, arch_info);
1622 }
1623
1624 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1625 return kvm_handle_sw_breakpoint();
1626 }
1627
1628 /*
1629 * QEMU is not able to handle debug exception, so inject
1630 * program exception to guest;
1631 * Yes program exception NOT debug exception !!
1632 * When QEMU is using debug resources then debug exception must
1633 * be always set. To achieve this we set MSR_DE and also set
1634 * MSRP_DEP so guest cannot change MSR_DE.
1635 * When emulating debug resource for guest we want guest
1636 * to control MSR_DE (enable/disable debug interrupt on need).
1637 * Supporting both configurations are NOT possible.
1638 * So the result is that we cannot share debug resources
1639 * between QEMU and Guest on BOOKE architecture.
1640 * In the current design QEMU gets the priority over guest,
1641 * this means that if QEMU is using debug resources then guest
1642 * cannot use them;
1643 * For software breakpoint QEMU uses a privileged instruction;
1644 * So there cannot be any reason that we are here for guest
1645 * set debug exception, only possibility is guest executed a
1646 * privileged / illegal instruction and that's why we are
1647 * injecting a program interrupt.
1648 */
1649 cpu_synchronize_state(cs);
1650 /*
1651 * env->nip is PC, so increment this by 4 to use
1652 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1653 */
1654 env->nip += 4;
1655 cs->exception_index = POWERPC_EXCP_PROGRAM;
1656 env->error_code = POWERPC_EXCP_INVAL;
1657 ppc_cpu_do_interrupt(cs);
1658
1659 return DEBUG_RETURN_GUEST;
1660 }
1661
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)1662 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
1663 {
1664 PowerPCCPU *cpu = POWERPC_CPU(cs);
1665 CPUPPCState *env = &cpu->env;
1666 int ret;
1667
1668 bql_lock();
1669
1670 switch (run->exit_reason) {
1671 case KVM_EXIT_DCR:
1672 if (run->dcr.is_write) {
1673 trace_kvm_handle_dcr_write();
1674 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1675 } else {
1676 trace_kvm_handle_dcr_read();
1677 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1678 }
1679 break;
1680 case KVM_EXIT_HLT:
1681 trace_kvm_handle_halt();
1682 ret = kvmppc_handle_halt(cpu);
1683 break;
1684 #if defined(CONFIG_PSERIES)
1685 case KVM_EXIT_PAPR_HCALL:
1686 trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
1687 run->papr_hcall.ret = spapr_hypercall(cpu,
1688 run->papr_hcall.nr,
1689 run->papr_hcall.args);
1690 ret = 0;
1691 break;
1692 #endif
1693 case KVM_EXIT_EPR:
1694 trace_kvm_handle_epr();
1695 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
1696 ret = 0;
1697 break;
1698 case KVM_EXIT_WATCHDOG:
1699 trace_kvm_handle_watchdog_expiry();
1700 watchdog_perform_action();
1701 ret = 0;
1702 break;
1703
1704 case KVM_EXIT_DEBUG:
1705 trace_kvm_handle_debug_exception();
1706 if (kvm_handle_debug(cpu, run)) {
1707 ret = EXCP_DEBUG;
1708 break;
1709 }
1710 /* re-enter, this exception was guest-internal */
1711 ret = 0;
1712 break;
1713
1714 #if defined(CONFIG_PSERIES)
1715 case KVM_EXIT_NMI:
1716 trace_kvm_handle_nmi_exception();
1717 ret = kvm_handle_nmi(cpu, run);
1718 break;
1719 #endif
1720
1721 default:
1722 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1723 ret = -1;
1724 break;
1725 }
1726
1727 bql_unlock();
1728 return ret;
1729 }
1730
kvmppc_or_tsr_bits(PowerPCCPU * cpu,uint32_t tsr_bits)1731 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1732 {
1733 CPUState *cs = CPU(cpu);
1734 uint32_t bits = tsr_bits;
1735 struct kvm_one_reg reg = {
1736 .id = KVM_REG_PPC_OR_TSR,
1737 .addr = (uintptr_t) &bits,
1738 };
1739
1740 if (!kvm_enabled()) {
1741 return 0;
1742 }
1743
1744 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1745 }
1746
kvmppc_clear_tsr_bits(PowerPCCPU * cpu,uint32_t tsr_bits)1747 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1748 {
1749
1750 CPUState *cs = CPU(cpu);
1751 uint32_t bits = tsr_bits;
1752 struct kvm_one_reg reg = {
1753 .id = KVM_REG_PPC_CLEAR_TSR,
1754 .addr = (uintptr_t) &bits,
1755 };
1756
1757 if (!kvm_enabled()) {
1758 return 0;
1759 }
1760
1761 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1762 }
1763
kvmppc_set_tcr(PowerPCCPU * cpu)1764 int kvmppc_set_tcr(PowerPCCPU *cpu)
1765 {
1766 CPUState *cs = CPU(cpu);
1767 CPUPPCState *env = &cpu->env;
1768 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1769
1770 struct kvm_one_reg reg = {
1771 .id = KVM_REG_PPC_TCR,
1772 .addr = (uintptr_t) &tcr,
1773 };
1774
1775 if (!kvm_enabled()) {
1776 return 0;
1777 }
1778
1779 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1780 }
1781
kvmppc_booke_watchdog_enable(PowerPCCPU * cpu)1782 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1783 {
1784 CPUState *cs = CPU(cpu);
1785 int ret;
1786
1787 if (!kvm_enabled()) {
1788 return -1;
1789 }
1790
1791 if (!cap_ppc_watchdog) {
1792 printf("warning: KVM does not support watchdog");
1793 return -1;
1794 }
1795
1796 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
1797 if (ret < 0) {
1798 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1799 __func__, strerror(-ret));
1800 return ret;
1801 }
1802
1803 return ret;
1804 }
1805
read_cpuinfo(const char * field,char * value,int len)1806 static int read_cpuinfo(const char *field, char *value, int len)
1807 {
1808 FILE *f;
1809 int ret = -1;
1810 int field_len = strlen(field);
1811 char line[512];
1812
1813 f = fopen("/proc/cpuinfo", "r");
1814 if (!f) {
1815 return -1;
1816 }
1817
1818 do {
1819 if (!fgets(line, sizeof(line), f)) {
1820 break;
1821 }
1822 if (!strncmp(line, field, field_len)) {
1823 pstrcpy(value, len, line);
1824 ret = 0;
1825 break;
1826 }
1827 } while (*line);
1828
1829 fclose(f);
1830
1831 return ret;
1832 }
1833
kvmppc_get_tbfreq_procfs(void)1834 static uint32_t kvmppc_get_tbfreq_procfs(void)
1835 {
1836 char line[512];
1837 char *ns;
1838 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1839 uint32_t tbfreq_procfs;
1840
1841 if (read_cpuinfo("timebase", line, sizeof(line))) {
1842 return tbfreq_fallback;
1843 }
1844
1845 ns = strchr(line, ':');
1846 if (!ns) {
1847 return tbfreq_fallback;
1848 }
1849
1850 tbfreq_procfs = atoi(++ns);
1851
1852 /* 0 is certainly not acceptable by the guest, return fallback value */
1853 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1854 }
1855
kvmppc_get_tbfreq(void)1856 uint32_t kvmppc_get_tbfreq(void)
1857 {
1858 static uint32_t cached_tbfreq;
1859
1860 if (!cached_tbfreq) {
1861 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1862 }
1863
1864 return cached_tbfreq;
1865 }
1866
kvmppc_get_host_serial(char ** value)1867 bool kvmppc_get_host_serial(char **value)
1868 {
1869 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1870 NULL);
1871 }
1872
kvmppc_get_host_model(char ** value)1873 bool kvmppc_get_host_model(char **value)
1874 {
1875 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1876 }
1877
1878 /* Try to find a device tree node for a CPU with clock-frequency property */
kvmppc_find_cpu_dt(char * buf,int buf_len)1879 static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1880 {
1881 struct dirent *dirp;
1882 DIR *dp;
1883
1884 dp = opendir(PROC_DEVTREE_CPU);
1885 if (!dp) {
1886 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1887 return -1;
1888 }
1889
1890 buf[0] = '\0';
1891 while ((dirp = readdir(dp)) != NULL) {
1892 FILE *f;
1893
1894 /* Don't accidentally read from the current and parent directories */
1895 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) {
1896 continue;
1897 }
1898
1899 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1900 dirp->d_name);
1901 f = fopen(buf, "r");
1902 if (f) {
1903 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1904 fclose(f);
1905 break;
1906 }
1907 buf[0] = '\0';
1908 }
1909 closedir(dp);
1910 if (buf[0] == '\0') {
1911 printf("Unknown host!\n");
1912 return -1;
1913 }
1914
1915 return 0;
1916 }
1917
kvmppc_read_int_dt(const char * filename)1918 static uint64_t kvmppc_read_int_dt(const char *filename)
1919 {
1920 union {
1921 uint32_t v32;
1922 uint64_t v64;
1923 } u;
1924 FILE *f;
1925 int len;
1926
1927 f = fopen(filename, "rb");
1928 if (!f) {
1929 return -1;
1930 }
1931
1932 len = fread(&u, 1, sizeof(u), f);
1933 fclose(f);
1934 switch (len) {
1935 case 4:
1936 /* property is a 32-bit quantity */
1937 return be32_to_cpu(u.v32);
1938 case 8:
1939 return be64_to_cpu(u.v64);
1940 }
1941
1942 return 0;
1943 }
1944
1945 /*
1946 * Read a CPU node property from the host device tree that's a single
1947 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1948 * (can't find or open the property, or doesn't understand the format)
1949 */
kvmppc_read_int_cpu_dt(const char * propname)1950 static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1951 {
1952 char buf[PATH_MAX], *tmp;
1953 uint64_t val;
1954
1955 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1956 return -1;
1957 }
1958
1959 tmp = g_strdup_printf("%s/%s", buf, propname);
1960 val = kvmppc_read_int_dt(tmp);
1961 g_free(tmp);
1962
1963 return val;
1964 }
1965
kvmppc_get_clockfreq(void)1966 uint64_t kvmppc_get_clockfreq(void)
1967 {
1968 return kvmppc_read_int_cpu_dt("clock-frequency");
1969 }
1970
kvmppc_get_dec_bits(void)1971 static int kvmppc_get_dec_bits(void)
1972 {
1973 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1974
1975 if (nr_bits > 0) {
1976 return nr_bits;
1977 }
1978 return 0;
1979 }
1980
kvmppc_get_pvinfo(CPUPPCState * env,struct kvm_ppc_pvinfo * pvinfo)1981 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1982 {
1983 CPUState *cs = env_cpu(env);
1984
1985 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1986 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1987 return 0;
1988 }
1989
1990 return 1;
1991 }
1992
kvmppc_get_hasidle(CPUPPCState * env)1993 int kvmppc_get_hasidle(CPUPPCState *env)
1994 {
1995 struct kvm_ppc_pvinfo pvinfo;
1996
1997 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1998 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1999 return 1;
2000 }
2001
2002 return 0;
2003 }
2004
kvmppc_get_hypercall(CPUPPCState * env,uint8_t * buf,int buf_len)2005 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
2006 {
2007 uint32_t *hc = (uint32_t *)buf;
2008 struct kvm_ppc_pvinfo pvinfo;
2009
2010 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
2011 memcpy(buf, pvinfo.hcall, buf_len);
2012 return 0;
2013 }
2014
2015 /*
2016 * Fallback to always fail hypercalls regardless of endianness:
2017 *
2018 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2019 * li r3, -1
2020 * b .+8 (becomes nop in wrong endian)
2021 * bswap32(li r3, -1)
2022 */
2023
2024 hc[0] = cpu_to_be32(0x08000048);
2025 hc[1] = cpu_to_be32(0x3860ffff);
2026 hc[2] = cpu_to_be32(0x48000008);
2027 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
2028
2029 return 1;
2030 }
2031
kvmppc_enable_hcall(KVMState * s,target_ulong hcall)2032 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2033 {
2034 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2035 }
2036
kvmppc_enable_logical_ci_hcalls(void)2037 void kvmppc_enable_logical_ci_hcalls(void)
2038 {
2039 /*
2040 * FIXME: it would be nice if we could detect the cases where
2041 * we're using a device which requires the in kernel
2042 * implementation of these hcalls, but the kernel lacks them and
2043 * produce a warning.
2044 */
2045 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2046 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2047 }
2048
kvmppc_enable_set_mode_hcall(void)2049 void kvmppc_enable_set_mode_hcall(void)
2050 {
2051 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2052 }
2053
kvmppc_enable_clear_ref_mod_hcalls(void)2054 void kvmppc_enable_clear_ref_mod_hcalls(void)
2055 {
2056 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2057 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2058 }
2059
kvmppc_enable_h_page_init(void)2060 void kvmppc_enable_h_page_init(void)
2061 {
2062 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2063 }
2064
kvmppc_enable_h_rpt_invalidate(void)2065 void kvmppc_enable_h_rpt_invalidate(void)
2066 {
2067 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2068 }
2069
2070 #ifdef CONFIG_PSERIES
kvmppc_set_papr(PowerPCCPU * cpu)2071 void kvmppc_set_papr(PowerPCCPU *cpu)
2072 {
2073 CPUState *cs = CPU(cpu);
2074 int ret;
2075
2076 if (!kvm_enabled()) {
2077 return;
2078 }
2079
2080 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
2081 if (ret) {
2082 error_report("This vCPU type or KVM version does not support PAPR");
2083 exit(1);
2084 }
2085
2086 /*
2087 * Update the capability flag so we sync the right information
2088 * with kvm
2089 */
2090 cap_papr = 1;
2091 }
2092 #endif
2093
kvmppc_set_compat(PowerPCCPU * cpu,uint32_t compat_pvr)2094 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
2095 {
2096 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
2097 }
2098
kvmppc_set_mpic_proxy(PowerPCCPU * cpu,int mpic_proxy)2099 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2100 {
2101 CPUState *cs = CPU(cpu);
2102 int ret;
2103
2104 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
2105 if (ret && mpic_proxy) {
2106 error_report("This KVM version does not support EPR");
2107 exit(1);
2108 }
2109 }
2110
kvmppc_get_fwnmi(void)2111 bool kvmppc_get_fwnmi(void)
2112 {
2113 return cap_fwnmi;
2114 }
2115
kvmppc_set_fwnmi(PowerPCCPU * cpu)2116 int kvmppc_set_fwnmi(PowerPCCPU *cpu)
2117 {
2118 CPUState *cs = CPU(cpu);
2119
2120 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2121 }
2122
kvmppc_has_cap_dawr1(void)2123 bool kvmppc_has_cap_dawr1(void)
2124 {
2125 return !!cap_dawr1;
2126 }
2127
kvmppc_set_cap_dawr1(int enable)2128 int kvmppc_set_cap_dawr1(int enable)
2129 {
2130 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_DAWR1, 0, enable);
2131 }
2132
kvmppc_smt_threads(void)2133 int kvmppc_smt_threads(void)
2134 {
2135 return cap_ppc_smt ? cap_ppc_smt : 1;
2136 }
2137
kvmppc_set_smt_threads(int smt)2138 int kvmppc_set_smt_threads(int smt)
2139 {
2140 int ret;
2141
2142 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2143 if (!ret) {
2144 cap_ppc_smt = smt;
2145 }
2146 return ret;
2147 }
2148
kvmppc_error_append_smt_possible_hint(Error * const * errp)2149 void kvmppc_error_append_smt_possible_hint(Error *const *errp)
2150 {
2151 int i;
2152 GString *g;
2153 char *s;
2154
2155 assert(kvm_enabled());
2156 if (cap_ppc_smt_possible) {
2157 g = g_string_new("Available VSMT modes:");
2158 for (i = 63; i >= 0; i--) {
2159 if ((1UL << i) & cap_ppc_smt_possible) {
2160 g_string_append_printf(g, " %lu", (1UL << i));
2161 }
2162 }
2163 s = g_string_free(g, false);
2164 error_append_hint(errp, "%s.\n", s);
2165 g_free(s);
2166 } else {
2167 error_append_hint(errp,
2168 "This KVM seems to be too old to support VSMT.\n");
2169 }
2170 }
2171
2172
2173 #ifdef TARGET_PPC64
kvmppc_vrma_limit(unsigned int hash_shift)2174 uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
2175 {
2176 struct kvm_ppc_smmu_info info;
2177 long rampagesize, best_page_shift;
2178 int i;
2179
2180 /*
2181 * Find the largest hardware supported page size that's less than
2182 * or equal to the (logical) backing page size of guest RAM
2183 */
2184 kvm_get_smmu_info(&info, &error_fatal);
2185 rampagesize = qemu_minrampagesize();
2186 best_page_shift = 0;
2187
2188 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2189 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2190
2191 if (!sps->page_shift) {
2192 continue;
2193 }
2194
2195 if ((sps->page_shift > best_page_shift)
2196 && ((1UL << sps->page_shift) <= rampagesize)) {
2197 best_page_shift = sps->page_shift;
2198 }
2199 }
2200
2201 return 1ULL << (best_page_shift + hash_shift - 7);
2202 }
2203 #endif
2204
kvmppc_spapr_use_multitce(void)2205 bool kvmppc_spapr_use_multitce(void)
2206 {
2207 return cap_spapr_multitce;
2208 }
2209
kvmppc_spapr_enable_inkernel_multitce(void)2210 int kvmppc_spapr_enable_inkernel_multitce(void)
2211 {
2212 int ret;
2213
2214 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2215 H_PUT_TCE_INDIRECT, 1);
2216 if (!ret) {
2217 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2218 H_STUFF_TCE, 1);
2219 }
2220
2221 return ret;
2222 }
2223
kvmppc_create_spapr_tce(uint32_t liobn,uint32_t page_shift,uint64_t bus_offset,uint32_t nb_table,int * pfd,bool need_vfio)2224 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2225 uint64_t bus_offset, uint32_t nb_table,
2226 int *pfd, bool need_vfio)
2227 {
2228 long len;
2229 int fd;
2230 void *table;
2231
2232 /*
2233 * Must set fd to -1 so we don't try to munmap when called for
2234 * destroying the table, which the upper layers -will- do
2235 */
2236 *pfd = -1;
2237 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
2238 return NULL;
2239 }
2240
2241 if (cap_spapr_tce_64) {
2242 struct kvm_create_spapr_tce_64 args = {
2243 .liobn = liobn,
2244 .page_shift = page_shift,
2245 .offset = bus_offset >> page_shift,
2246 .size = nb_table,
2247 .flags = 0
2248 };
2249 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2250 if (fd < 0) {
2251 fprintf(stderr,
2252 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2253 liobn);
2254 return NULL;
2255 }
2256 } else if (cap_spapr_tce) {
2257 uint64_t window_size = (uint64_t) nb_table << page_shift;
2258 struct kvm_create_spapr_tce args = {
2259 .liobn = liobn,
2260 .window_size = window_size,
2261 };
2262 if ((window_size != args.window_size) || bus_offset) {
2263 return NULL;
2264 }
2265 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2266 if (fd < 0) {
2267 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2268 liobn);
2269 return NULL;
2270 }
2271 } else {
2272 return NULL;
2273 }
2274
2275 len = nb_table * sizeof(uint64_t);
2276 /* FIXME: round this up to page size */
2277
2278 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
2279 if (table == MAP_FAILED) {
2280 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2281 liobn);
2282 close(fd);
2283 return NULL;
2284 }
2285
2286 *pfd = fd;
2287 return table;
2288 }
2289
kvmppc_remove_spapr_tce(void * table,int fd,uint32_t nb_table)2290 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
2291 {
2292 long len;
2293
2294 if (fd < 0) {
2295 return -1;
2296 }
2297
2298 len = nb_table * sizeof(uint64_t);
2299 if ((munmap(table, len) < 0) ||
2300 (close(fd) < 0)) {
2301 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2302 strerror(errno));
2303 /* Leak the table */
2304 }
2305
2306 return 0;
2307 }
2308
kvmppc_reset_htab(int shift_hint)2309 int kvmppc_reset_htab(int shift_hint)
2310 {
2311 uint32_t shift = shift_hint;
2312
2313 if (!kvm_enabled()) {
2314 /* Full emulation, tell caller to allocate htab itself */
2315 return 0;
2316 }
2317 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
2318 int ret;
2319 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
2320 if (ret == -ENOTTY) {
2321 /*
2322 * At least some versions of PR KVM advertise the
2323 * capability, but don't implement the ioctl(). Oops.
2324 * Return 0 so that we allocate the htab in qemu, as is
2325 * correct for PR.
2326 */
2327 return 0;
2328 } else if (ret < 0) {
2329 return ret;
2330 }
2331 return shift;
2332 }
2333
2334 /*
2335 * We have a kernel that predates the htab reset calls. For PR
2336 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2337 * this era, it has allocated a 16MB fixed size hash table
2338 * already.
2339 */
2340 if (kvmppc_is_pr(kvm_state)) {
2341 /* PR - tell caller to allocate htab */
2342 return 0;
2343 } else {
2344 /* HV - assume 16MB kernel allocated htab */
2345 return 24;
2346 }
2347 }
2348
mfpvr(void)2349 static inline uint32_t mfpvr(void)
2350 {
2351 uint32_t pvr;
2352
2353 asm ("mfpvr %0"
2354 : "=r"(pvr));
2355 return pvr;
2356 }
2357
alter_insns(uint64_t * word,uint64_t flags,bool on)2358 static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2359 {
2360 if (on) {
2361 *word |= flags;
2362 } else {
2363 *word &= ~flags;
2364 }
2365 }
2366
kvmppc_cpu_realize(CPUState * cs,Error ** errp)2367 static bool kvmppc_cpu_realize(CPUState *cs, Error **errp)
2368 {
2369 int ret;
2370 const char *vcpu_str = (cs->parent_obj.hotplugged == true) ?
2371 "hotplug" : "create";
2372 cs->cpu_index = cpu_get_free_index();
2373
2374 POWERPC_CPU(cs)->vcpu_id = cs->cpu_index;
2375
2376 /* create and park to fail gracefully in case vcpu hotplug fails */
2377 ret = kvm_create_and_park_vcpu(cs);
2378 if (ret) {
2379 /*
2380 * This causes QEMU to terminate if initial CPU creation
2381 * fails, and only CPU hotplug failure if the error happens
2382 * there.
2383 */
2384 error_setg(errp, "%s: vcpu %s failed with %d",
2385 __func__, vcpu_str, ret);
2386 return false;
2387 }
2388 return true;
2389 }
2390
kvmppc_host_cpu_class_init(ObjectClass * oc,const void * data)2391 static void kvmppc_host_cpu_class_init(ObjectClass *oc, const void *data)
2392 {
2393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2394 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2395 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
2396
2397 /* Now fix up the class with information we can query from the host */
2398 pcc->pvr = mfpvr();
2399
2400 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2401 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2402 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2403 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2404 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2405 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
2406
2407 if (dcache_size != -1) {
2408 pcc->l1_dcache_size = dcache_size;
2409 }
2410
2411 if (icache_size != -1) {
2412 pcc->l1_icache_size = icache_size;
2413 }
2414
2415 #if defined(TARGET_PPC64)
2416 pcc->radix_page_info = kvmppc_get_radix_page_info();
2417 #endif /* defined(TARGET_PPC64) */
2418 }
2419
kvmppc_has_cap_epr(void)2420 bool kvmppc_has_cap_epr(void)
2421 {
2422 return cap_epr;
2423 }
2424
kvmppc_has_cap_fixup_hcalls(void)2425 bool kvmppc_has_cap_fixup_hcalls(void)
2426 {
2427 return cap_fixup_hcalls;
2428 }
2429
kvmppc_has_cap_htm(void)2430 bool kvmppc_has_cap_htm(void)
2431 {
2432 return cap_htm;
2433 }
2434
kvmppc_has_cap_mmu_radix(void)2435 bool kvmppc_has_cap_mmu_radix(void)
2436 {
2437 return cap_mmu_radix;
2438 }
2439
kvmppc_has_cap_mmu_hash_v3(void)2440 bool kvmppc_has_cap_mmu_hash_v3(void)
2441 {
2442 return cap_mmu_hash_v3;
2443 }
2444
kvmppc_power8_host(void)2445 static bool kvmppc_power8_host(void)
2446 {
2447 bool ret = false;
2448 #ifdef TARGET_PPC64
2449 {
2450 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2451 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2452 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2453 (base_pvr == CPU_POWERPC_POWER8_BASE);
2454 }
2455 #endif /* TARGET_PPC64 */
2456 return ret;
2457 }
2458
parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)2459 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2460 {
2461 bool l1d_thread_priv_req = !kvmppc_power8_host();
2462
2463 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2464 return 2;
2465 } else if ((!l1d_thread_priv_req ||
2466 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
2467 (c.character & c.character_mask
2468 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2469 return 1;
2470 }
2471
2472 return 0;
2473 }
2474
parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)2475 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2476 {
2477 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2478 return 2;
2479 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2480 return 1;
2481 }
2482
2483 return 0;
2484 }
2485
parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)2486 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2487 {
2488 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2489 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2490 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2491 return SPAPR_CAP_FIXED_NA;
2492 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2493 return SPAPR_CAP_WORKAROUND;
2494 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2495 return SPAPR_CAP_FIXED_CCD;
2496 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2497 return SPAPR_CAP_FIXED_IBS;
2498 }
2499
2500 return 0;
2501 }
2502
parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)2503 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2504 {
2505 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2506 return 1;
2507 }
2508 return 0;
2509 }
2510
kvmppc_has_cap_xive(void)2511 bool kvmppc_has_cap_xive(void)
2512 {
2513 return cap_xive;
2514 }
2515
kvmppc_get_cpu_characteristics(KVMState * s)2516 static void kvmppc_get_cpu_characteristics(KVMState *s)
2517 {
2518 struct kvm_ppc_cpu_char c;
2519 int ret;
2520
2521 /* Assume broken */
2522 cap_ppc_safe_cache = 0;
2523 cap_ppc_safe_bounds_check = 0;
2524 cap_ppc_safe_indirect_branch = 0;
2525
2526 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2527 if (!ret) {
2528 return;
2529 }
2530 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2531 if (ret < 0) {
2532 return;
2533 }
2534
2535 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2536 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2537 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
2538 cap_ppc_count_cache_flush_assist =
2539 parse_cap_ppc_count_cache_flush_assist(c);
2540 }
2541
kvmppc_get_cap_safe_cache(void)2542 int kvmppc_get_cap_safe_cache(void)
2543 {
2544 return cap_ppc_safe_cache;
2545 }
2546
kvmppc_get_cap_safe_bounds_check(void)2547 int kvmppc_get_cap_safe_bounds_check(void)
2548 {
2549 return cap_ppc_safe_bounds_check;
2550 }
2551
kvmppc_get_cap_safe_indirect_branch(void)2552 int kvmppc_get_cap_safe_indirect_branch(void)
2553 {
2554 return cap_ppc_safe_indirect_branch;
2555 }
2556
kvmppc_get_cap_count_cache_flush_assist(void)2557 int kvmppc_get_cap_count_cache_flush_assist(void)
2558 {
2559 return cap_ppc_count_cache_flush_assist;
2560 }
2561
kvmppc_has_cap_nested_kvm_hv(void)2562 bool kvmppc_has_cap_nested_kvm_hv(void)
2563 {
2564 return !!cap_ppc_nested_kvm_hv;
2565 }
2566
kvmppc_set_cap_nested_kvm_hv(int enable)2567 int kvmppc_set_cap_nested_kvm_hv(int enable)
2568 {
2569 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2570 }
2571
kvmppc_has_cap_spapr_vfio(void)2572 bool kvmppc_has_cap_spapr_vfio(void)
2573 {
2574 return cap_spapr_vfio;
2575 }
2576
kvmppc_get_cap_large_decr(void)2577 int kvmppc_get_cap_large_decr(void)
2578 {
2579 return cap_large_decr;
2580 }
2581
kvmppc_enable_cap_large_decr(PowerPCCPU * cpu,int enable)2582 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2583 {
2584 CPUState *cs = CPU(cpu);
2585 uint64_t lpcr = 0;
2586
2587 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2588 /* Do we need to modify the LPCR? */
2589 if (!!(lpcr & LPCR_LD) != !!enable) {
2590 if (enable) {
2591 lpcr |= LPCR_LD;
2592 } else {
2593 lpcr &= ~LPCR_LD;
2594 }
2595 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2596 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2597
2598 if (!!(lpcr & LPCR_LD) != !!enable) {
2599 return -1;
2600 }
2601 }
2602
2603 return 0;
2604 }
2605
kvmppc_has_cap_rpt_invalidate(void)2606 int kvmppc_has_cap_rpt_invalidate(void)
2607 {
2608 return cap_rpt_invalidate;
2609 }
2610
kvmppc_supports_ail_3(void)2611 bool kvmppc_supports_ail_3(void)
2612 {
2613 return cap_ail_mode_3;
2614 }
2615
kvm_ppc_get_host_cpu_class(void)2616 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2617 {
2618 uint32_t host_pvr = mfpvr();
2619 PowerPCCPUClass *pvr_pcc;
2620
2621 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2622 if (pvr_pcc == NULL) {
2623 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2624 }
2625
2626 return pvr_pcc;
2627 }
2628
pseries_machine_class_fixup(ObjectClass * oc,void * opaque)2629 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2630 {
2631 MachineClass *mc = MACHINE_CLASS(oc);
2632
2633 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2634 }
2635
kvm_ppc_register_host_cpu_type(void)2636 static int kvm_ppc_register_host_cpu_type(void)
2637 {
2638 TypeInfo type_info = {
2639 .name = TYPE_HOST_POWERPC_CPU,
2640 .class_init = kvmppc_host_cpu_class_init,
2641 };
2642 PowerPCCPUClass *pvr_pcc;
2643 ObjectClass *oc;
2644 DeviceClass *dc;
2645 int i;
2646
2647 pvr_pcc = kvm_ppc_get_host_cpu_class();
2648 if (pvr_pcc == NULL) {
2649 return -1;
2650 }
2651 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2652 type_register_static(&type_info);
2653 /* override TCG default cpu type with 'host' cpu model */
2654 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2655 false, NULL);
2656
2657 oc = object_class_by_name(type_info.name);
2658 g_assert(oc);
2659
2660 /*
2661 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2662 * we want "POWER8" to be a "family" alias that points to the current
2663 * host CPU type, too)
2664 */
2665 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2666 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
2667 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
2668 char *suffix;
2669
2670 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
2671 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
2672 if (suffix) {
2673 *suffix = 0;
2674 }
2675 break;
2676 }
2677 }
2678
2679 return 0;
2680 }
2681
kvmppc_define_rtas_kernel_token(uint32_t token,const char * function)2682 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2683 {
2684 struct kvm_rtas_token_args args = {
2685 .token = token,
2686 };
2687
2688 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2689 return -ENOENT;
2690 }
2691
2692 strncpy(args.name, function, sizeof(args.name) - 1);
2693
2694 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2695 }
2696
kvmppc_get_htab_fd(bool write,uint64_t index,Error ** errp)2697 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
2698 {
2699 struct kvm_get_htab_fd s = {
2700 .flags = write ? KVM_GET_HTAB_WRITE : 0,
2701 .start_index = index,
2702 };
2703 int ret;
2704
2705 if (!cap_htab_fd) {
2706 error_setg(errp, "KVM version doesn't support %s the HPT",
2707 write ? "writing" : "reading");
2708 return -ENOTSUP;
2709 }
2710
2711 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2712 if (ret < 0) {
2713 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2714 write ? "writing" : "reading", write ? "to" : "from",
2715 strerror(errno));
2716 return -errno;
2717 }
2718
2719 return ret;
2720 }
2721
kvmppc_save_htab(QEMUFile * f,int fd,size_t bufsize,int64_t max_ns)2722 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2723 {
2724 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2725 g_autofree uint8_t *buf = g_malloc(bufsize);
2726 ssize_t rc;
2727
2728 do {
2729 rc = read(fd, buf, bufsize);
2730 if (rc < 0) {
2731 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2732 strerror(errno));
2733 return rc;
2734 } else if (rc) {
2735 uint8_t *buffer = buf;
2736 ssize_t n = rc;
2737 while (n) {
2738 struct kvm_get_htab_header *head =
2739 (struct kvm_get_htab_header *) buffer;
2740 size_t chunksize = sizeof(*head) +
2741 HASH_PTE_SIZE_64 * head->n_valid;
2742
2743 qemu_put_be32(f, head->index);
2744 qemu_put_be16(f, head->n_valid);
2745 qemu_put_be16(f, head->n_invalid);
2746 qemu_put_buffer(f, (void *)(head + 1),
2747 HASH_PTE_SIZE_64 * head->n_valid);
2748
2749 buffer += chunksize;
2750 n -= chunksize;
2751 }
2752 }
2753 } while ((rc != 0)
2754 && ((max_ns < 0) ||
2755 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
2756
2757 return (rc == 0) ? 1 : 0;
2758 }
2759
kvmppc_load_htab_chunk(QEMUFile * f,int fd,uint32_t index,uint16_t n_valid,uint16_t n_invalid,Error ** errp)2760 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2761 uint16_t n_valid, uint16_t n_invalid, Error **errp)
2762 {
2763 struct kvm_get_htab_header *buf;
2764 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
2765 ssize_t rc;
2766
2767 buf = alloca(chunksize);
2768 buf->index = index;
2769 buf->n_valid = n_valid;
2770 buf->n_invalid = n_invalid;
2771
2772 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
2773
2774 rc = write(fd, buf, chunksize);
2775 if (rc < 0) {
2776 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2777 return -errno;
2778 }
2779 if (rc != chunksize) {
2780 /* We should never get a short write on a single chunk */
2781 error_setg(errp, "Short write while restoring the KVM hash table");
2782 return -ENOSPC;
2783 }
2784 return 0;
2785 }
2786
kvm_arch_stop_on_emulation_error(CPUState * cpu)2787 bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
2788 {
2789 return true;
2790 }
2791
kvm_arch_init_irq_routing(KVMState * s)2792 void kvm_arch_init_irq_routing(KVMState *s)
2793 {
2794 }
2795
kvmppc_read_hptes(ppc_hash_pte64_t * hptes,hwaddr ptex,int n)2796 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
2797 {
2798 int fd, rc;
2799 int i;
2800
2801 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
2802
2803 i = 0;
2804 while (i < n) {
2805 struct kvm_get_htab_header *hdr;
2806 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2807 char buf[sizeof(*hdr) + HPTES_PER_GROUP * HASH_PTE_SIZE_64];
2808
2809 rc = read(fd, buf, sizeof(*hdr) + m * HASH_PTE_SIZE_64);
2810 if (rc < 0) {
2811 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2812 }
2813
2814 hdr = (struct kvm_get_htab_header *)buf;
2815 while ((i < n) && ((char *)hdr < (buf + rc))) {
2816 int invalid = hdr->n_invalid, valid = hdr->n_valid;
2817
2818 if (hdr->index != (ptex + i)) {
2819 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2820 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2821 }
2822
2823 if (n - i < valid) {
2824 valid = n - i;
2825 }
2826 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2827 i += valid;
2828
2829 if ((n - i) < invalid) {
2830 invalid = n - i;
2831 }
2832 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
2833 i += invalid;
2834
2835 hdr = (struct kvm_get_htab_header *)
2836 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2837 }
2838 }
2839
2840 close(fd);
2841 }
2842
kvmppc_write_hpte(hwaddr ptex,uint64_t pte0,uint64_t pte1)2843 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
2844 {
2845 int fd, rc;
2846 struct {
2847 struct kvm_get_htab_header hdr;
2848 uint64_t pte0;
2849 uint64_t pte1;
2850 } buf;
2851
2852 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
2853
2854 buf.hdr.n_valid = 1;
2855 buf.hdr.n_invalid = 0;
2856 buf.hdr.index = ptex;
2857 buf.pte0 = cpu_to_be64(pte0);
2858 buf.pte1 = cpu_to_be64(pte1);
2859
2860 rc = write(fd, &buf, sizeof(buf));
2861 if (rc != sizeof(buf)) {
2862 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2863 }
2864 close(fd);
2865 }
2866
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)2867 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2868 uint64_t address, uint32_t data, PCIDevice *dev)
2869 {
2870 return 0;
2871 }
2872
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)2873 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2874 int vector, PCIDevice *dev)
2875 {
2876 return 0;
2877 }
2878
kvm_arch_release_virq_post(int virq)2879 int kvm_arch_release_virq_post(int virq)
2880 {
2881 return 0;
2882 }
2883
kvm_arch_msi_data_to_gsi(uint32_t data)2884 int kvm_arch_msi_data_to_gsi(uint32_t data)
2885 {
2886 return data & 0xffff;
2887 }
2888
2889 #if defined(CONFIG_PSERIES)
kvm_handle_nmi(PowerPCCPU * cpu,struct kvm_run * run)2890 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2891 {
2892 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
2893
2894 cpu_synchronize_state(CPU(cpu));
2895
2896 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
2897
2898 return 0;
2899 }
2900 #endif
2901
kvmppc_enable_hwrng(void)2902 int kvmppc_enable_hwrng(void)
2903 {
2904 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2905 return -1;
2906 }
2907
2908 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2909 }
2910
kvmppc_check_papr_resize_hpt(Error ** errp)2911 void kvmppc_check_papr_resize_hpt(Error **errp)
2912 {
2913 if (!kvm_enabled()) {
2914 return; /* No KVM, we're good */
2915 }
2916
2917 if (cap_resize_hpt) {
2918 return; /* Kernel has explicit support, we're good */
2919 }
2920
2921 /* Otherwise fallback on looking for PR KVM */
2922 if (kvmppc_is_pr(kvm_state)) {
2923 return;
2924 }
2925
2926 error_setg(errp,
2927 "Hash page table resizing not available with this KVM version");
2928 }
2929
kvmppc_resize_hpt_prepare(PowerPCCPU * cpu,target_ulong flags,int shift)2930 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2931 {
2932 CPUState *cs = CPU(cpu);
2933 struct kvm_ppc_resize_hpt rhpt = {
2934 .flags = flags,
2935 .shift = shift,
2936 };
2937
2938 if (!cap_resize_hpt) {
2939 return -ENOSYS;
2940 }
2941
2942 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2943 }
2944
kvmppc_resize_hpt_commit(PowerPCCPU * cpu,target_ulong flags,int shift)2945 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2946 {
2947 CPUState *cs = CPU(cpu);
2948 struct kvm_ppc_resize_hpt rhpt = {
2949 .flags = flags,
2950 .shift = shift,
2951 };
2952
2953 if (!cap_resize_hpt) {
2954 return -ENOSYS;
2955 }
2956
2957 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2958 }
2959
2960 /*
2961 * This is a helper function to detect a post migration scenario
2962 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2963 * the guest kernel can't handle a PVR value other than the actual host
2964 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2965 *
2966 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2967 * (so, we're HV), return true. The workaround itself is done in
2968 * cpu_post_load.
2969 *
2970 * The order here is important: we'll only check for KVM PR as a
2971 * fallback if the guest kernel can't handle the situation itself.
2972 * We need to avoid as much as possible querying the running KVM type
2973 * in QEMU level.
2974 */
kvmppc_pvr_workaround_required(PowerPCCPU * cpu)2975 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2976 {
2977 CPUState *cs = CPU(cpu);
2978
2979 if (!kvm_enabled()) {
2980 return false;
2981 }
2982
2983 if (cap_ppc_pvr_compat) {
2984 return false;
2985 }
2986
2987 return !kvmppc_is_pr(cs->kvm_state);
2988 }
2989
kvmppc_set_reg_ppc_online(PowerPCCPU * cpu,unsigned int online)2990 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2991 {
2992 CPUState *cs = CPU(cpu);
2993
2994 if (kvm_enabled()) {
2995 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2996 }
2997 }
2998
kvmppc_set_reg_tb_offset(PowerPCCPU * cpu,int64_t tb_offset)2999 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
3000 {
3001 CPUState *cs = CPU(cpu);
3002
3003 if (kvm_enabled()) {
3004 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
3005 }
3006 }
3007
kvm_arch_accel_class_init(ObjectClass * oc)3008 void kvm_arch_accel_class_init(ObjectClass *oc)
3009 {
3010 }
3011
kvm_cpu_accel_class_init(ObjectClass * oc,const void * data)3012 static void kvm_cpu_accel_class_init(ObjectClass *oc, const void *data)
3013 {
3014 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
3015
3016 acc->cpu_target_realize = kvmppc_cpu_realize;
3017 }
3018
3019 static const TypeInfo kvm_cpu_accel_type_info = {
3020 .name = ACCEL_CPU_NAME("kvm"),
3021
3022 .parent = TYPE_ACCEL_CPU,
3023 .class_init = kvm_cpu_accel_class_init,
3024 .abstract = true,
3025 };
kvm_cpu_accel_register_types(void)3026 static void kvm_cpu_accel_register_types(void)
3027 {
3028 type_register_static(&kvm_cpu_accel_type_info);
3029 }
3030 type_init(kvm_cpu_accel_register_types);
3031