1 /*
2 * QEMU PPC (monitor definitions)
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "cpu.h"
27 #include "monitor/monitor.h"
28 #include "qemu/ctype.h"
29 #include "monitor/hmp-target.h"
30 #include "monitor/hmp.h"
31 #include "qapi/error.h"
32 #include "qapi/qapi-commands-machine.h"
33 #include "cpu-models.h"
34 #include "cpu-qom.h"
35
monitor_get_ccr(Monitor * mon,const struct MonitorDef * md,int val)36 static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
37 int val)
38 {
39 CPUArchState *env = mon_get_cpu_env(mon);
40 unsigned int u;
41
42 u = ppc_get_cr(env);
43
44 return u;
45 }
46
monitor_get_xer(Monitor * mon,const struct MonitorDef * md,int val)47 static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,
48 int val)
49 {
50 CPUArchState *env = mon_get_cpu_env(mon);
51 return cpu_read_xer(env);
52 }
53
monitor_get_decr(Monitor * mon,const struct MonitorDef * md,int val)54 static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
55 int val)
56 {
57 CPUArchState *env = mon_get_cpu_env(mon);
58 if (!env->tb_env) {
59 return 0;
60 }
61 return cpu_ppc_load_decr(env);
62 }
63
monitor_get_tbu(Monitor * mon,const struct MonitorDef * md,int val)64 static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
65 int val)
66 {
67 CPUArchState *env = mon_get_cpu_env(mon);
68 if (!env->tb_env) {
69 return 0;
70 }
71 return cpu_ppc_load_tbu(env);
72 }
73
monitor_get_tbl(Monitor * mon,const struct MonitorDef * md,int val)74 static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
75 int val)
76 {
77 CPUArchState *env = mon_get_cpu_env(mon);
78 if (!env->tb_env) {
79 return 0;
80 }
81 return cpu_ppc_load_tbl(env);
82 }
83
hmp_info_tlb(Monitor * mon,const QDict * qdict)84 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
85 {
86 CPUArchState *env1 = mon_get_cpu_env(mon);
87
88 if (!env1) {
89 monitor_printf(mon, "No CPU available\n");
90 return;
91 }
92 dump_mmu(env1);
93 }
94
95 const MonitorDef monitor_defs[] = {
96 { "fpscr", offsetof(CPUPPCState, fpscr) },
97 /* Next instruction pointer */
98 { "nip|pc", offsetof(CPUPPCState, nip) },
99 { "lr", offsetof(CPUPPCState, lr) },
100 { "ctr", offsetof(CPUPPCState, ctr) },
101 { "decr", 0, &monitor_get_decr, },
102 { "ccr|cr", 0, &monitor_get_ccr, },
103 /* Machine state register */
104 { "xer", 0, &monitor_get_xer },
105 { "msr", offsetof(CPUPPCState, msr) },
106 { "tbu", 0, &monitor_get_tbu, },
107 #if defined(TARGET_PPC64)
108 { "tb", 0, &monitor_get_tbl, },
109 #else
110 { "tbl", 0, &monitor_get_tbl, },
111 #endif
112 { NULL },
113 };
114
target_monitor_defs(void)115 const MonitorDef *target_monitor_defs(void)
116 {
117 return monitor_defs;
118 }
119
ppc_cpu_get_reg_num(const char * numstr,int maxnum,int * pregnum)120 static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
121 {
122 int regnum;
123 char *endptr = NULL;
124
125 if (!*numstr) {
126 return false;
127 }
128
129 regnum = strtoul(numstr, &endptr, 10);
130 if (*endptr || (regnum >= maxnum)) {
131 return false;
132 }
133 *pregnum = regnum;
134
135 return true;
136 }
137
target_get_monitor_def(CPUState * cs,const char * name,uint64_t * pval)138 int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
139 {
140 int i, regnum;
141 CPUPPCState *env = cpu_env(cs);
142
143 /* General purpose registers */
144 if ((qemu_tolower(name[0]) == 'r') &&
145 ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) {
146 *pval = env->gpr[regnum];
147 return 0;
148 }
149
150 /* Floating point registers */
151 if ((qemu_tolower(name[0]) == 'f') &&
152 ppc_cpu_get_reg_num(name + 1, 32, ®num)) {
153 *pval = *cpu_fpr_ptr(env, regnum);
154 return 0;
155 }
156
157 /* Special purpose registers */
158 for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
159 ppc_spr_t *spr = &env->spr_cb[i];
160
161 if (spr->name && (strcasecmp(name, spr->name) == 0)) {
162 *pval = env->spr[i];
163 return 0;
164 }
165 }
166
167 /* Segment registers */
168 #if !defined(CONFIG_USER_ONLY)
169 if ((strncasecmp(name, "sr", 2) == 0) &&
170 ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) {
171 *pval = env->sr[regnum];
172 return 0;
173 }
174 #endif
175
176 return -EINVAL;
177 }
178
179 CpuModelExpansionInfo *
qmp_query_cpu_model_expansion(CpuModelExpansionType type,CpuModelInfo * model,Error ** errp)180 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
181 CpuModelInfo *model,
182 Error **errp)
183 {
184 error_setg(errp, "CPU model expansion is not supported on this target");
185 return NULL;
186 }
187
ppc_cpu_defs_entry(gpointer data,gpointer user_data)188 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
189 {
190 ObjectClass *oc = data;
191 CpuDefinitionInfoList **first = user_data;
192 const char *typename;
193 CpuDefinitionInfo *info;
194
195 typename = object_class_get_name(oc);
196 info = g_malloc0(sizeof(*info));
197 info->name = cpu_model_from_type(typename);
198
199 QAPI_LIST_PREPEND(*first, info);
200 }
201
qmp_query_cpu_definitions(Error ** errp)202 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
203 {
204 CpuDefinitionInfoList *cpu_list = NULL;
205 GSList *list;
206 int i;
207
208 list = object_class_get_list(TYPE_POWERPC_CPU, false);
209 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
210 g_slist_free(list);
211
212 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
213 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
214 ObjectClass *oc;
215 CpuDefinitionInfo *info;
216
217 oc = ppc_cpu_class_by_name(alias->model);
218 if (oc == NULL) {
219 continue;
220 }
221
222 info = g_malloc0(sizeof(*info));
223 info->name = g_strdup(alias->alias);
224 info->q_typename = g_strdup(object_class_get_name(oc));
225
226 QAPI_LIST_PREPEND(cpu_list, info);
227 }
228
229 return cpu_list;
230 }
231