| /linux-3.3/arch/blackfin/mach-bf533/include/mach/ |
| D | defBF532.h | 582 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
583 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
584 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
586 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
587 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
588 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
590 …ne B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
591 …ne B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
592 …ne B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
594 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
[all …]
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| /linux-3.3/arch/alpha/include/asm/ |
| D | xor.h | 62 xor $0,$1,$0 # 7 cycles from $1 load \n\
119 xor $0,$1,$1 # 8 cycles from $0 load \n\
120 xor $3,$4,$4 # 6 cycles from $4 load \n\
121 xor $6,$7,$7 # 6 cycles from $7 load \n\
122 xor $21,$22,$22 # 5 cycles from $22 load \n\
124 xor $1,$2,$2 # 9 cycles from $2 load \n\
125 xor $24,$25,$25 # 5 cycles from $25 load \n\
127 xor $4,$5,$5 # 6 cycles from $5 load \n\
130 xor $7,$20,$20 # 7 cycles from $20 load \n\
132 xor $22,$23,$23 # 7 cycles from $23 load \n\
[all …]
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| /linux-3.3/arch/blackfin/mach-bf527/include/mach/ |
| D | defBF522.h | 786 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
787 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
788 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
790 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
791 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
792 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
794 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
795 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
796 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
798 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
[all …]
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| /linux-3.3/arch/blackfin/mach-bf561/include/mach/ |
| D | defBF561.h | 1120 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1121 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1122 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1124 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1125 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1126 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1128 …ne B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1129 …ne B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1130 …ne B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1132 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
[all …]
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| /linux-3.3/arch/blackfin/mach-bf518/include/mach/ |
| D | defBF512.h | 785 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
786 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
787 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
789 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
790 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
791 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
793 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
794 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
795 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
797 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
[all …]
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| /linux-3.3/arch/blackfin/mach-bf537/include/mach/ |
| D | defBF534.h | 1108 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1109 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1110 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1112 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1113 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1114 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1116 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1117 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1118 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1120 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
[all …]
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| /linux-3.3/arch/blackfin/mach-bf538/include/mach/ |
| D | defBF538.h | 1500 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1501 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1502 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1504 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles…
1505 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles…
1506 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles…
1508 …B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1509 …B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1510 …B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1512 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
[all …]
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| /linux-3.3/arch/x86/include/asm/ |
| D | timer.h | 16 * convert from cycles(64bits) => nanoseconds (64bits)
18 * ns = cycles / (freq / ns_per_sec)
19 * ns = cycles * (ns_per_sec / freq)
20 * ns = cycles * (10^9 / (cpu_khz * 10^3))
21 * ns = cycles * (10^6 / cpu_khz)
24 * ns = cycles * (10^6 * SC / cpu_khz) / SC
25 * ns = cycles * cyc2ns_scale / SC
38 * ns = cycles * cyc2ns_scale / SC
41 * in some cases, we may not have enough bits to store cycles * cyc2ns_scale,
44 * To avoid this, we can decompose 'cycles' into quotient and remainder
|
| /linux-3.3/Documentation/m68k/ |
| D | README.buddha | 142 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
148 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
152 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
156 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
160 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
164 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
168 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
172 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
178 781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive.
182 system: Sometimes two more clock cycles are inserted by the
[all …]
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| /linux-3.3/arch/mips/include/asm/sgi/ |
| D | hpc3.h | 85 #define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
86 #define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
87 #define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
96 #define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
97 #define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
98 #define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
99 #define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
137 #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138 #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139 #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
[all …]
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| /linux-3.3/tools/power/cpupower/bench/ |
| D | benchmark.c | 106 total_time *= 2; /* powersave and performance cycles */ in start_benchmark()
125 printf("_round %i: doing %u cycles with %u calculations" in start_benchmark()
126 " for %lius\n", _round + 1, config->cycles, in start_benchmark()
137 /* do some sleep/load cycles with the performance governor */ in start_benchmark()
138 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
152 performance_time / config->cycles); in start_benchmark()
162 /* again, do some sleep/load cycles with the in start_benchmark()
164 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
180 /* compare the avarage sleep/load cycles */ in start_benchmark()
182 powersave_time / config->cycles); in start_benchmark()
|
| D | README-BENCH | 35 will be run X time in a row (cycles):
39 cycles=20
50 25ms load/sleep time repeated 20 times (cycles).
51 50ms load/sleep time repeated 20 times (cycles).
53 100ms load/sleep time repeated 20 times (cycles).
83 But if ondemand always kicks in in the middle of the load sleep cycles, it
116 -n, --cycles=<int> load/sleep cycles to get an avarage value to compare
|
| D | main.c | 40 {"cycles", 1, 0, 'n'},
63 printf(" -n, --cycles=<int>\t\t\tload/sleep cycles\n"); in usage()
135 sscanf(optarg, "%u", &config->cycles); in main()
136 dprintf("user cycles -> %s\n", optarg); in main()
178 "cycles=%u\n\t" in main()
186 config->cycles, in main()
|
| /linux-3.3/arch/blackfin/mach-common/ |
| D | cpufreq.c | 48 * normalized to maximum frequency offset for CYCLES,
49 * used in time-ts cycles clock source, but could be used
112 cycles_t cycles; in bfin_target() local
142 cycles = get_cycles(); in bfin_target()
144 cycles += 10; /* ~10 cycles we lose after get_cycles() */ in bfin_target()
146 (cycles << __bfin_cycles_mod) - (cycles << index); in bfin_target()
159 /* TODO: just test case for cycles clock source, remove later */ in bfin_target()
|
| /linux-3.3/arch/sh/lib/ |
| D | udivsi3_i4i-Os.S | 33 udiv small divisor: 55 cycles
34 udiv large divisor: 52 cycles
35 sdiv small divisor, positive result: 59 cycles
36 sdiv large divisor, positive result: 56 cycles
37 sdiv small divisor, negative result: 65 cycles (*)
38 sdiv large divisor, negative result: 62 cycles (*)
40 of two more cycles. */
|
| /linux-3.3/arch/powerpc/include/asm/ |
| D | 8xx_immap.h | 127 #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128 #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129 #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130 #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131 #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133 #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135 #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136 #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
[all …]
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| /linux-3.3/drivers/net/ethernet/seeq/ |
| D | sgiseeq.h | 88 #define SEEQ_HPIO_P1BITS 0x00000001 /* cycles to stay in P1 phase for PIO */
89 #define SEEQ_HPIO_P2BITS 0x00000060 /* cycles to stay in P2 phase for PIO */
90 #define SEEQ_HPIO_P3BITS 0x00000100 /* cycles to stay in P3 phase for PIO */
91 #define SEEQ_HDMA_D1BITS 0x00000006 /* cycles to stay in D1 phase for DMA */
92 #define SEEQ_HDMA_D2BITS 0x00000020 /* cycles to stay in D2 phase for DMA */
93 #define SEEQ_HDMA_D3BITS 0x00000000 /* cycles to stay in D3 phase for DMA */
94 #define SEEQ_HDMA_TIMEO 0x00030000 /* cycles for DMA timeout */
|
| /linux-3.3/include/linux/ |
| D | clocksource.h | 73 * cyclecounter_cyc2ns - converts cycle counter cycles to nanoseconds
75 * @cycles: Cycles
81 cycle_t cycles) in cyclecounter_cyc2ns() argument
83 u64 ret = (u64)cycles; in cyclecounter_cyc2ns()
265 * clocksource_cyc2ns - converts clocksource cycles to nanoseconds
266 * @cycles: cycles
270 * Converts cycles to nanoseconds, using the given mult and shift.
274 static inline s64 clocksource_cyc2ns(cycle_t cycles, u32 mult, u32 shift) in clocksource_cyc2ns() argument
276 return ((u64) cycles * mult) >> shift; in clocksource_cyc2ns()
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| /linux-3.3/crypto/ |
| D | tcrypt.c | 96 unsigned long cycles = 0; in test_cipher_cycles() local
128 cycles += end - start; in test_cipher_cycles()
136 printk("1 operation in %lu cycles (%d bytes)\n", in test_cipher_cycles()
137 (cycles + 4) / 8, blen); in test_cipher_cycles()
299 unsigned long cycles = 0; in test_hash_cycles_digest() local
325 cycles += end - start; in test_hash_cycles_digest()
335 printk("%6lu cycles/operation, %4lu cycles/byte\n", in test_hash_cycles_digest()
336 cycles / 8, cycles / (8 * blen)); in test_hash_cycles_digest()
344 unsigned long cycles = 0; in test_hash_cycles() local
389 cycles += end - start; in test_hash_cycles()
[all …]
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| /linux-3.3/arch/arm/plat-omap/ |
| D | counter_32k.c | 48 * 32k sync timer. Convert the cycles elapsed since last read into
52 static cycles_t cycles, last_cycles; variable
60 last_cycles = cycles; in read_persistent_clock()
61 cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0; in read_persistent_clock()
62 delta = cycles - last_cycles; in read_persistent_clock()
|
| /linux-3.3/Documentation/misc-devices/ |
| D | isl29003 | 46 0: 2^16 cycles (default)
47 1: 2^12 cycles
48 2: 2^8 cycles
49 3: 2^4 cycles
|
| /linux-3.3/arch/tile/lib/ |
| D | spinlock_common.h | 17 * The mfspr in __spinlock_relax() is 5 or 6 cycles plus 2 for loop
27 * Idle the core for CYCLES_PER_RELAX_LOOP * iterations cycles.
44 * which takes 8 cycles. We want to start with a 16- to 31-cycle in delay_backoff()
52 * or 1,024 (to 2,047) cycles, as our maximum. in delay_backoff()
|
| /linux-3.3/arch/parisc/kernel/ |
| D | time.c | 38 static unsigned long clocktick __read_mostly; /* timer cycles per tick */
52 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
97 /* Determine when (in CR16 cycles) next IT interrupt will fire. in timer_interrupt()
126 * GGG: DEBUG code for how many cycles programming CR16 used. in timer_interrupt()
128 if (unlikely(now2 - now > 0x3000)) /* 12K cycles */ in timer_interrupt()
129 printk (KERN_CRIT "timer_interrupt(CPU %d): SLOW! 0x%lx cycles!" in timer_interrupt()
139 * Timer_interrupt will be delivered at least a few hundred cycles in timer_interrupt()
149 " cycles %lX rem %lX " in timer_interrupt()
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| /linux-3.3/arch/arm/mach-exynos/ |
| D | mct.c | 175 unsigned long cycles) in exynos4_mct_comp0_start() argument
184 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); in exynos4_mct_comp0_start()
187 comp_cycle = exynos4_frc_read(&mct_frc) + cycles; in exynos4_mct_comp0_start()
197 static int exynos4_comp_set_next_event(unsigned long cycles, in exynos4_comp_set_next_event() argument
200 exynos4_mct_comp0_start(evt->mode, cycles); in exynos4_comp_set_next_event()
282 static void exynos4_mct_tick_start(unsigned long cycles, in exynos4_mct_tick_start() argument
289 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ in exynos4_mct_tick_start()
303 static int exynos4_tick_set_next_event(unsigned long cycles, in exynos4_tick_set_next_event() argument
308 exynos4_mct_tick_start(cycles, mevt); in exynos4_tick_set_next_event()
|
| /linux-3.3/drivers/net/wireless/ath/ |
| D | hw.c | 138 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
145 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
160 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
165 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
177 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
|