Lines Matching full:cycles
582 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
583 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
584 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
586 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
587 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
588 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
590 …ne B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
591 …ne B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
592 …ne B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
594 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
595 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
596 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
597 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
598 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
599 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
600 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
601 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
602 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
603 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
604 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
605 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
606 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
607 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
609 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
610 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
611 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
612 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
613 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
614 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
615 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
616 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
617 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
618 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
619 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
620 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
621 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
622 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
626 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
627 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
628 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
630 … B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
631 … B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
632 … B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
634 …HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
635 …HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
636 …HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
638 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
639 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
640 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
641 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
642 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
643 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
644 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
645 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
646 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
647 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
648 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
649 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
650 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
651 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
653 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
654 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
655 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
656 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
657 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
658 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
659 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
660 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
661 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
662 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
663 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
664 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
665 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
666 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
672 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
673 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
674 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
676 … B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
677 … B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
678 … B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
680 …HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
681 …HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
682 …HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
684 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
685 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
686 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
687 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
688 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
689 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
690 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
691 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
692 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
693 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
694 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
695 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
696 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
697 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
699 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
700 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
701 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
702 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
703 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
704 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
705 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
706 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
707 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
708 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
709 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
710 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
711 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
712 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
716 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
717 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
718 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
720 … B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
721 … B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
722 … B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
724 …HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
725 …HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
726 …HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
728 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
729 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
730 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
731 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
732 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
733 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
734 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
735 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
736 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
737 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
738 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
739 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
740 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
741 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
743 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
744 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
745 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
746 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
747 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
748 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
749 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
750 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
751 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
752 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
753 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
754 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
755 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
756 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
762 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
763 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
770 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
771 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
772 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
773 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
774 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
775 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
776 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
777 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
778 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
779 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
780 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
781 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
782 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
783 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
785 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
786 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
787 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
788 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
789 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
790 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
792 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
793 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
794 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
795 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
796 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
797 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
799 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
800 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
802 …PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */