Lines Matching full:cycles
785 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
786 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
787 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
789 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
790 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
791 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
793 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
794 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
795 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
797 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
798 #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
799 #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
800 #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
801 #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
802 #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
803 #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
804 #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
805 #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
806 #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
807 #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
808 #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
809 #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
810 #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
812 #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
813 #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
814 #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
815 #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
816 #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
817 #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
818 #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
819 #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
820 #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
821 #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
822 #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
823 #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
824 #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
825 #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
830 #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
831 #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
832 #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
834 #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
835 #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
836 #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
838 #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
839 #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
840 #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
842 #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
843 #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
844 #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
845 #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
846 #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
847 #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
848 #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
849 #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
850 #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
851 #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
852 #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
853 #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
854 #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
855 #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
857 #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
858 #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
859 #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
860 #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
861 #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
862 #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
863 #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
864 #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
865 #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
866 #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
867 #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
868 #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
869 #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
870 #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
876 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
877 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
878 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
880 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
881 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
882 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
884 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
885 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
886 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
888 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
889 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
890 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
891 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
892 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
893 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
894 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
895 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
896 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
897 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
898 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
899 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
900 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
901 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
903 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
904 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
905 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
906 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
907 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
908 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
909 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
910 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
911 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
912 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
913 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
914 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
915 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
916 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
921 #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
922 #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
923 #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
925 #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
926 #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
927 #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
929 #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
930 #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
931 #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
933 #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
934 #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
935 #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
936 #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
937 #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
938 #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
939 #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
940 #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
941 #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
942 #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
943 #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
944 #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
945 #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
946 #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
948 #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
949 #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
950 #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
951 #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
952 #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
953 #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
954 #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
955 #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
956 #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
957 #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
958 #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
959 #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
960 #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
961 #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
967 #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
968 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
973 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
974 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
975 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
976 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
977 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
978 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
979 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
980 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
981 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
982 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
983 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
984 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
985 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
986 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
988 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
989 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
990 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
991 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
992 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
993 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
995 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
996 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
997 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
998 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
999 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1000 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1002 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1003 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1004 #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */