Lines Matching full:cycles
127 #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128 #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129 #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130 #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131 #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133 #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135 #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136 #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137 #define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138 #define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139 #define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140 #define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141 #define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142 #define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */