Lines Matching full:cycles
1500 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1501 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1502 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1504 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles…
1505 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles…
1506 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles…
1508 …B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1509 …B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1510 …B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1512 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1513 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1514 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1515 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1516 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1517 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1518 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1519 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1520 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1521 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1522 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1523 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1524 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1525 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1527 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1528 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1529 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1530 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1531 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1532 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1533 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1534 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1535 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1536 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1537 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1538 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1539 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1540 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1544 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1545 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1546 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1548 …B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1549 …B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1550 …B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1552 …T_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1553 …T_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1554 …T_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1556 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1557 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1558 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1559 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1560 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1561 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1562 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1563 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1564 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1565 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1566 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1567 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1568 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1569 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1571 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1572 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1573 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1574 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1575 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1576 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1577 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1578 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1579 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1580 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1581 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1582 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1583 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1584 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1590 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1591 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1592 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1594 …B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1595 …B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1596 …B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1598 …T_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1599 …T_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1600 …T_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1602 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1603 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1604 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1605 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1606 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1607 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1608 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1609 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1610 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1611 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1612 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1613 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1614 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1615 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1617 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1618 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1619 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1620 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1621 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1622 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1623 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1624 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1625 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1626 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1627 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1628 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1629 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1630 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1634 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1635 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1636 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1638 …B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1639 …B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1640 …B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1642 …T_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1643 …T_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1644 …T_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1646 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1647 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1648 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1649 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1650 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1651 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1652 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1653 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1654 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1655 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1656 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1657 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1658 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1659 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1661 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1662 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1663 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1664 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1665 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1666 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1667 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1668 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1669 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1670 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1671 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1672 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1673 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1674 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1679 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1680 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1687 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1688 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1689 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1690 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1691 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1692 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1693 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1694 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1695 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1696 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1697 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1698 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1699 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1700 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1702 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1703 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1704 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1705 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1706 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1707 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1709 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1710 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1711 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1712 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1713 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1714 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1716 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1717 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1719 …SM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */