Lines Matching full:cycles
1108 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1109 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1110 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1112 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1113 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1114 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1116 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1117 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1118 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1120 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1121 #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1122 #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1123 #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1124 #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1125 #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1126 #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1127 #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1128 #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1129 #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1130 #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1131 #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1132 #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1133 #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1135 #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1136 #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1137 #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1138 #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1139 #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1140 #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1141 #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1142 #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1143 #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1144 #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1145 #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1146 #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1147 #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1148 #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1153 #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1154 #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1155 #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1157 #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1158 #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1159 #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1161 #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1162 #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1163 #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1165 #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1166 #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1167 #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1168 #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1169 #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1170 #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1171 #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1172 #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1173 #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1174 #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1175 #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1176 #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1177 #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1178 #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1180 #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1181 #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1182 #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1183 #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1184 #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1185 #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1186 #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1187 #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1188 #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1189 #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1190 #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1191 #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1192 #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1193 #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1199 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1200 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1201 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1203 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1204 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1205 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1207 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1208 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1209 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1211 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1212 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1213 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1214 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1215 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1216 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1217 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1218 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1219 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1220 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1221 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1222 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1223 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1224 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1226 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1227 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1228 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1229 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1230 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1231 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1232 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1233 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1234 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1235 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1236 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1237 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1238 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1239 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1244 #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1245 #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1246 #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1248 #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1249 #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1250 #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1252 #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1253 #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1254 #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1256 #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1257 #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1258 #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1259 #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1260 #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1261 #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1262 #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1263 #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1264 #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1265 #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1266 #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1267 #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1268 #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1269 #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1271 #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1272 #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1273 #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1274 #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1275 #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1276 #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1277 #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1278 #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1279 #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1280 #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1281 #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1282 #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1283 #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1284 #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1289 #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles …
1290 #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles …
1295 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles …
1296 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles …
1297 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles …
1298 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles …
1299 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles …
1300 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles …
1301 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles …
1302 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles …
1303 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles …
1304 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles …
1305 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles …
1306 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles …
1307 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles …
1308 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles …
1310 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles …
1311 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles …
1312 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles …
1313 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles …
1314 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles …
1315 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles …
1317 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles …
1318 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles …
1319 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles …
1320 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles …
1321 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles …
1322 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles …
1324 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles …
1325 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles …
1326 #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) …