| /qemu/hw/intc/ |
| H A D | imx_avic.c | 2 * i.MX31 Vectored Interrupt Controller
76 * Take interrupt if there's a pending interrupt with in imx_avic_update()
119 case 1: /* Normal Interrupt Mask Register, NIMASK */ in imx_avic_read()
122 case 2: /* Interrupt Enable Number Register, INTENNUM */ in imx_avic_read()
123 case 3: /* Interrupt Disable Number Register, INTDISNUM */ in imx_avic_read()
126 case 4: /* Interrupt Enabled Number Register High */ in imx_avic_read()
129 case 5: /* Interrupt Enabled Number Register Low */ in imx_avic_read()
132 case 6: /* Interrupt Type Register High */ in imx_avic_read()
135 case 7: /* Interrupt Type Register Low */ in imx_avic_read()
138 case 8: /* Normal Interrupt Priority Register 7 */ in imx_avic_read()
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| H A D | aspeed_vic.c | 2 * ASPEED Interrupt Controller (New)
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
66 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", in aspeed_vic_set_irq()
131 case 0x90: /* Raw Interrupt Status */ in aspeed_vic_read()
135 case 0x98: /* Interrupt Selection */ in aspeed_vic_read()
139 case 0xa0: /* Interrupt Enable */ in aspeed_vic_read()
143 case 0xb0: /* Software Interrupt */ in aspeed_vic_read()
147 case 0xc0: /* Interrupt Sensitivity */ in aspeed_vic_read()
151 case 0xc8: /* Interrupt Both Edge Trigger Control */ in aspeed_vic_read()
155 case 0xd0: /* Interrupt Event */ in aspeed_vic_read()
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| H A D | arm_gicv3.c | 2 * ARM Generic Interrupt Controller v3 (emulation)
12 /* This file contains implementation code for an interrupt controller
28 * pending interrupt for this CPU. We also return true if in irqbetter()
29 * the current recorded highest priority pending interrupt in irqbetter()
47 * signal the one with the lowest interrupt number. in irqbetter()
60 * interrupt that is eligible to be signaled to the CPU interface. in gicd_int_pending()
62 * An interrupt is pending if: in gicd_int_pending()
104 * and return a 32-bit integer which has a bit set for each interrupt in gicr_int_pending()
107 * An interrupt is pending if: in gicr_int_pending()
175 /* Update the interrupt status after state in a redistributor
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| /qemu/docs/specs/ |
| H A D | ppc-xive.rst | 2 POWER9 XIVE interrupt controller
5 The POWER9 processor comes with a new interrupt controller
6 architecture, called XIVE as "eXternal Interrupt Virtualization
10 XIVE are to support a larger number of interrupt sources and to
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
29 Controller (VC). It handles event coalescing and perform interrupt
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
33 Controller (PC). It maintains the interrupt context state of each
34 thread and handles the delivery of the external interrupt to the
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| H A D | ivshmem-spec.rst | 14 In the latter case, the device can additionally interrupt its peers, and
41 - If you additionally need the capability for peers to interrupt each
64 0 4 read/write 0 Interrupt Mask
65 bit 0: peer interrupt (rev 0)
68 4 4 read/write 0 Interrupt Status
69 bit 0: peer interrupt (rev 0)
82 In revision 0 of the device, Interrupt Status and Mask Register
83 together control the legacy INTx interrupt when the device has no
85 Mask is non-zero and the device has no MSI-X capability. Interrupt
86 Status Register bit 0 becomes 1 when an interrupt request from a peer
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| H A D | edu.rst | 63 raise interrupt after finishing factorial computation
65 0x24 (RO) : interrupt status register
66 It contains values which raised the interrupt (see interrupt raise
69 0x60 (WO) : interrupt raise register
70 Raise an interrupt. The value will be put to the interrupt status
73 0x64 (WO) : interrupt acknowledge register
74 Clear an interrupt. The value will be cleared from the interrupt
95 raise interrupt 0x100 after finishing the DMA
100 An IRQ is generated when written to the interrupt raise register. The value
101 appears in interrupt status register when the interrupt is raised and has to
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| H A D | ppc-spapr-xive.rst | 4 The POWER9 processor comes with a new interrupt controller
5 architecture, called XIVE as "eXternal Interrupt Virtualization
6 Engine". It supports a larger number of interrupt sources and offers
11 processors can run under two interrupt modes:
23 structures, and provides direct control for interrupt management
26 Which interrupt modes can be used by the machine is negotiated with
30 Both interrupt mode share the same IRQ number space. See below for the
36 QEMU advertises the supported interrupt modes in the device tree
41 The interrupt modes supported by the machine depend on the CPU type
49 The chosen interrupt mode is activated after a reconfiguration done
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| H A D | vmw_pvscsi-spec.rst | 30 issue device interrupts, and control interrupt masking.
53 The following interrupt types are supported by the PVSCSI device:
66 register. If a bit is set it means the interrupt is enabled, and if
67 it is clear then the interrupt is disabled.
69 The interrupt modes supported are legacy, MSI and MSI-X.
71 register is used to check which interrupt has arrived. Interrupts are
72 acknowledged when the corresponding bit is written to the interrupt
82 b. Windows driver reads interrupt status register here
114 a. Upon completion interrupt arrival process completion
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| /qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 52 UIC0: interrupt-controller0 {
54 interrupt-controller;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
64 interrupt-controller;
69 #interrupt-cells = <2>;
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
76 interrupt-controller;
81 #interrupt-cells = <2>;
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| H A D | bamboo.dts | 50 UIC0: interrupt-controller0 {
52 interrupt-controller;
57 #interrupt-cells = <0x2>;
96 /* interrupt-parent = <&UIC1>; */
107 /* interrupt-parent = <&UIC1>; */
117 interrupt-parent = <&UIC0>;
128 interrupt-parent = <&UIC0>;
136 interrupt-parent = <&UIC0>;
144 interrupt-parent = <&UIC0>;
158 #interrupt-cells = <1>;
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| /qemu/tests/qtest/ |
| H A D | stm32l4x5_exti-test.c | 177 * Testing interrupt line EXTI0 in test_software_interrupt()
184 /* Check that this specific interrupt isn't pending in NVIC */ in test_software_interrupt()
187 /* Enable interrupt line EXTI0 */ in test_software_interrupt()
197 /* Check that the corresponding interrupt is pending in the NVIC */ in test_software_interrupt()
207 /* Check that the interrupt is still pending in the NVIC */ in test_software_interrupt()
211 * Testing interrupt line EXTI35 in test_software_interrupt()
220 /* Enable interrupt line EXTI0 */ in test_software_interrupt()
230 /* Check that the corresponding interrupt is pending in the NVIC */ in test_software_interrupt()
240 /* Check that the interrupt is still pending in the NVIC */ in test_software_interrupt()
347 * Testing interrupt line EXTI0 in test_no_software_interrupt()
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| H A D | rtl8139-test.c | 106 /* Test 2. Check we didn't get an interrupt with TimerInt == 0 */ in test_timer()
108 fatal("got an interrupt\n"); in test_timer()
111 /* Test 3. Setting TimerInt to 1 and Timer to 0 get interrupt */ in test_timer()
116 fatal("we should have an interrupt here!\n"); in test_timer()
122 fatal("got an interrupt\n"); in test_timer()
134 fatal("we should have an interrupt here!\n"); in test_timer()
146 fatal("we should have an interrupt here!\n"); in test_timer()
149 /* Test 4. Increment TimerInt we should see an interrupt */ in test_timer()
163 fatal("we should have an interrupt here!\n"); in test_timer()
171 /* Test 5. Second time we pass from 0 should see an interrupt */ in test_timer()
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| /qemu/tests/tcg/xtensa/ |
| H A D | test_timer.S | 66 rsr a2, interrupt
77 rsr a3, interrupt
83 rsr a2, interrupt
91 rsr a2, interrupt
104 rsr a3, interrupt
106 rsr a5, interrupt
119 rsr a2, interrupt
133 rsr a2, interrupt
156 rsr a2, interrupt
168 rsr a2, interrupt
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| H A D | test_interrupt.S | 41 test_suite interrupt
58 rsr a2, interrupt
62 rsr a2, interrupt
70 assert eqi, a2, 0x10 /* only EXCM is set for level-1 interrupt */
99 rsr a3, interrupt
105 rsr a3, interrupt
121 rsr a3, interrupt
140 rsr a3, interrupt
159 rsr a3, interrupt
178 rsr a3, interrupt
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| /qemu/rust/qemu-api/src/ |
| H A D | irq.rs | 5 //! Bindings for interrupt sources
25 /// Interrupt sources are used by devices to pass changes to a value (typically
26 /// a boolean). The interrupt sink is usually an interrupt controller or
29 /// As far as devices are concerned, interrupt sources are always active-high:
33 /// device and the interrupt controller.
35 /// Interrupts are implemented as a pointer to the interrupt "sink", which has
39 /// interrupt. To connect it, whoever creates the device fills the pointer with
41 /// devices are generally shared objects, interrupt sources are an example of
44 /// Interrupt sources can only be triggered under the Big QEMU Lock; `BqlCell`
60 /// Send a low (`false`) value to the interrupt sink.
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| /qemu/include/hw/net/ |
| H A D | npcm7xx_emc.h | 107 /* Enable Transmit Descriptor Unavailable Interrupt */
109 /* Enable Transmit Completion Interrupt */
111 /* Enable Transmit Interrupt */
113 /* Enable Receive Descriptor Unavailable Interrupt */
115 /* Enable Receive Good Interrupt */
117 /* Enable Receive Interrupt */
122 /* Transmit Bus Error Interrupt */
124 /* Transmit Descriptor Unavailable Interrupt */
126 /* Transmit Completion Interrupt */
128 /* Transmit Interrupt */
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| H A D | npcm_gmac.h | 82 /* Disable Interrupt on Completion */
138 /* Interrupt of Completion */
210 /* Early Receive Interrupt */
212 /* Fatal Bus Error Interrupt */
214 /* Early transmit Interrupt */
222 /* Receive Interrupt */
234 /* Transmit Interrupt */
237 /* Normal Interrupt Summary */
244 /* Abnormal Interrupt Summary */
257 /* Early Receive Interrupt Enable */
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| /qemu/target/sparc/ |
| H A D | int32_helper.c | 2 * Sparc32 interrupt helpers
39 [TT_EXTINT | 0x1] = "External Interrupt 1",
40 [TT_EXTINT | 0x2] = "External Interrupt 2",
41 [TT_EXTINT | 0x3] = "External Interrupt 3",
42 [TT_EXTINT | 0x4] = "External Interrupt 4",
43 [TT_EXTINT | 0x5] = "External Interrupt 5",
44 [TT_EXTINT | 0x6] = "External Interrupt 6",
45 [TT_EXTINT | 0x7] = "External Interrupt 7",
46 [TT_EXTINT | 0x8] = "External Interrupt 8",
47 [TT_EXTINT | 0x9] = "External Interrupt 9",
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| H A D | int64_helper.c | 2 * Sparc64 interrupt helpers
47 [TT_EXTINT | 0x1] = "External Interrupt 1",
48 [TT_EXTINT | 0x2] = "External Interrupt 2",
49 [TT_EXTINT | 0x3] = "External Interrupt 3",
50 [TT_EXTINT | 0x4] = "External Interrupt 4",
51 [TT_EXTINT | 0x5] = "External Interrupt 5",
52 [TT_EXTINT | 0x6] = "External Interrupt 6",
53 [TT_EXTINT | 0x7] = "External Interrupt 7",
54 [TT_EXTINT | 0x8] = "External Interrupt 8",
55 [TT_EXTINT | 0x9] = "External Interrupt 9",
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| /qemu/target/xtensa/ |
| H A D | overlay_tool.h | 246 #define INTERRUPT(i) { \ macro
252 [0] = INTERRUPT(0), \
253 [1] = INTERRUPT(1), \
254 [2] = INTERRUPT(2), \
255 [3] = INTERRUPT(3), \
256 [4] = INTERRUPT(4), \
257 [5] = INTERRUPT(5), \
258 [6] = INTERRUPT(6), \
259 [7] = INTERRUPT(7), \
260 [8] = INTERRUPT(8), \
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| /qemu/include/hw/ppc/ |
| H A D | xive.h | 2 * QEMU PowerPC XIVE interrupt controller model
5 * The POWER9 processor comes with a new interrupt controller, called
6 * XIVE as "eXternal Interrupt Virtualization Engine".
11 * XIVE Interrupt Controller
45 * tctx: Thread interrupt Context
50 * - Interrupt Virtualization Source Engine (IVSE), or Source
56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
60 * - Interrupt Virtualization Presentation Engine (IVPE) or
61 * Presentation Controller (PC). It maintains the interrupt context
117 * the thread interrupt context (TCTX) of each thread in a NVT table.
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| /qemu/include/hw/intc/ |
| H A D | imx_avic.h | 2 * i.MX31 Vectored Interrupt Controller
28 /* Interrupt Control Bits */
31 #define NIDIS (1<<22) /* Normal Interrupt disable */
32 #define FIDIS (1<<21) /* Fast interrupt disable */
33 #define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
34 #define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
35 #define NM (1<<18) /* Normal interrupt mode */
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| /qemu/linux-user/ppc/ |
| H A D | cpu_loop.c | 88 cpu_abort(cs, "Critical interrupt while in user mode. " in cpu_loop()
102 cpu_abort(cs, "External interrupt while in user mode. " in cpu_loop()
206 cpu_abort(cs, "Decrementer interrupt while in user mode. " in cpu_loop()
209 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ in cpu_loop()
210 cpu_abort(cs, "Fix interval timer interrupt while in user mode. " in cpu_loop()
213 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ in cpu_loop()
214 cpu_abort(cs, "Watchdog timer interrupt while in user mode. " in cpu_loop()
234 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ in cpu_loop()
235 cpu_abort(cs, "Doorbell interrupt while in user mode. " in cpu_loop()
238 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ in cpu_loop()
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| /qemu/include/hw/char/ |
| H A D | imx_serial.h | 41 #define USR1_ESCF (1<<11) /* Escape sequence interrupt */
44 #define USR1_AGTIM (1<<8) /* Aging timer interrupt */
47 #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */
57 #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */
67 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
68 #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
69 #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
77 #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
78 #define UCR4_OREN BIT(1) /* Overrun interrupt enable */
79 #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
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| /qemu/rust/hw/char/pl011/src/ |
| H A D | device.rs | 25 registers::{self, Interrupt, RegisterOffset},
91 pub int_enabled: Interrupt,
92 pub int_level: Interrupt,
116 /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line)
117 /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line)
118 /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line)
119 /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line)
120 /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line)
121 /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line)
209 // "The UARTICR Register is the interrupt clear register and is write-only" in read()
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