docs/specs/ivshmem-spec.rst

14 In the latter case, the device can additionally interrupt its peers, and
41 - If you additionally need the capability for peers to interrupt each
64         0     4   read/write        0   Interrupt Mask
65                                         bit 0: peer interrupt (rev 0)
68         4     4   read/write        0   Interrupt Status
69                                         bit 0: peer interrupt (rev 0)
82 In revision 0 of the device, Interrupt Status and Mask Register
83 together control the legacy INTx interrupt when the device has no
85 Mask is non-zero and the device has no MSI-X capability.  Interrupt
86 Status Register bit 0 becomes 1 when an interrupt request from a peer
99 Doorbell Register: writing this register requests to interrupt a peer.
100 The written value's high 16 bits are the ID of the peer to interrupt,
101 and its low 16 bits select an interrupt vector.
105 If the interrupt hasn't completed setup, the write is ignored.  The
110 interrupt vectors connected, the write is ignored.  The device is not
112 interrupt vectors are connected.
114 The peer's interrupt for this vector then becomes pending.  There is
119 Interrupt Status register is set to 1.  This asserts INTx unless
120 masked by the Interrupt Mask register.  The device is not capable to
121 communicate the interrupt vector to guest software then.
124 different events have occurred.  The semantics of interrupt vectors
127 Interrupt infrastructure
142 - creates eventfd file descriptors for the interrupt vectors,
149 - sends interrupt setup messages to the new client (these contain file
167 production.  It assumes all clients use the same number of interrupt
207 5. Interrupt setup.  This is the client's own ID, repeated N times.
237 To interrupt a peer, the device writes the 8-byte integer 1 in native
240 To receive an interrupt, the device reads and discards as many 8-byte