xref: /qemu/target/sparc/int32_helper.c (revision fc524567087c2537b5103cdfc1d41e4f442892b6)
1ab3b491fSBlue Swirl /*
2ab3b491fSBlue Swirl  * Sparc32 interrupt helpers
3ab3b491fSBlue Swirl  *
4ab3b491fSBlue Swirl  *  Copyright (c) 2003-2005 Fabrice Bellard
5ab3b491fSBlue Swirl  *
6ab3b491fSBlue Swirl  * This library is free software; you can redistribute it and/or
7ab3b491fSBlue Swirl  * modify it under the terms of the GNU Lesser General Public
8ab3b491fSBlue Swirl  * License as published by the Free Software Foundation; either
95650b549SChetan Pant  * version 2.1 of the License, or (at your option) any later version.
10ab3b491fSBlue Swirl  *
11ab3b491fSBlue Swirl  * This library is distributed in the hope that it will be useful,
12ab3b491fSBlue Swirl  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13ab3b491fSBlue Swirl  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14ab3b491fSBlue Swirl  * Lesser General Public License for more details.
15ab3b491fSBlue Swirl  *
16ab3b491fSBlue Swirl  * You should have received a copy of the GNU Lesser General Public
17ab3b491fSBlue Swirl  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18ab3b491fSBlue Swirl  */
19ab3b491fSBlue Swirl 
20db5ebe5fSPeter Maydell #include "qemu/osdep.h"
2110fb1340SPhilippe Mathieu-Daudé #include "qemu/main-loop.h"
22ab3b491fSBlue Swirl #include "cpu.h"
2311e66bcaSBlue Swirl #include "trace.h"
24*42fa9665SPhilippe Mathieu-Daudé #include "accel/tcg/cpu-ldst.h"
25508127e2SPaolo Bonzini #include "exec/log.h"
2632cad1ffSPhilippe Mathieu-Daudé #include "system/runstate.h"
27ab3b491fSBlue Swirl 
28ab3b491fSBlue Swirl static const char * const excp_names[0x80] = {
29ab3b491fSBlue Swirl     [TT_TFAULT] = "Instruction Access Fault",
30ab3b491fSBlue Swirl     [TT_ILL_INSN] = "Illegal Instruction",
31ab3b491fSBlue Swirl     [TT_PRIV_INSN] = "Privileged Instruction",
32ab3b491fSBlue Swirl     [TT_NFPU_INSN] = "FPU Disabled",
33ab3b491fSBlue Swirl     [TT_WIN_OVF] = "Window Overflow",
34ab3b491fSBlue Swirl     [TT_WIN_UNF] = "Window Underflow",
35ab3b491fSBlue Swirl     [TT_UNALIGNED] = "Unaligned Memory Access",
36ab3b491fSBlue Swirl     [TT_FP_EXCP] = "FPU Exception",
37ab3b491fSBlue Swirl     [TT_DFAULT] = "Data Access Fault",
38ab3b491fSBlue Swirl     [TT_TOVF] = "Tag Overflow",
39ab3b491fSBlue Swirl     [TT_EXTINT | 0x1] = "External Interrupt 1",
40ab3b491fSBlue Swirl     [TT_EXTINT | 0x2] = "External Interrupt 2",
41ab3b491fSBlue Swirl     [TT_EXTINT | 0x3] = "External Interrupt 3",
42ab3b491fSBlue Swirl     [TT_EXTINT | 0x4] = "External Interrupt 4",
43ab3b491fSBlue Swirl     [TT_EXTINT | 0x5] = "External Interrupt 5",
44ab3b491fSBlue Swirl     [TT_EXTINT | 0x6] = "External Interrupt 6",
45ab3b491fSBlue Swirl     [TT_EXTINT | 0x7] = "External Interrupt 7",
46ab3b491fSBlue Swirl     [TT_EXTINT | 0x8] = "External Interrupt 8",
47ab3b491fSBlue Swirl     [TT_EXTINT | 0x9] = "External Interrupt 9",
48ab3b491fSBlue Swirl     [TT_EXTINT | 0xa] = "External Interrupt 10",
49ab3b491fSBlue Swirl     [TT_EXTINT | 0xb] = "External Interrupt 11",
50ab3b491fSBlue Swirl     [TT_EXTINT | 0xc] = "External Interrupt 12",
51ab3b491fSBlue Swirl     [TT_EXTINT | 0xd] = "External Interrupt 13",
52ab3b491fSBlue Swirl     [TT_EXTINT | 0xe] = "External Interrupt 14",
53ab3b491fSBlue Swirl     [TT_EXTINT | 0xf] = "External Interrupt 15",
54ab3b491fSBlue Swirl     [TT_CODE_ACCESS] = "Instruction Access Error",
55ab3b491fSBlue Swirl     [TT_DATA_ACCESS] = "Data Access Error",
56ab3b491fSBlue Swirl     [TT_DIV_ZERO] = "Division By Zero",
57ab3b491fSBlue Swirl     [TT_NCP_INSN] = "Coprocessor Disabled",
58ab3b491fSBlue Swirl };
59ab3b491fSBlue Swirl 
excp_name_str(int32_t exception_index)6086e8c353SPhilippe Mathieu-Daudé static const char *excp_name_str(int32_t exception_index)
6186e8c353SPhilippe Mathieu-Daudé {
6286e8c353SPhilippe Mathieu-Daudé     if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) {
6386e8c353SPhilippe Mathieu-Daudé         return "Unknown";
6486e8c353SPhilippe Mathieu-Daudé     }
6586e8c353SPhilippe Mathieu-Daudé     return excp_names[exception_index];
6686e8c353SPhilippe Mathieu-Daudé }
6786e8c353SPhilippe Mathieu-Daudé 
cpu_check_irqs(CPUSPARCState * env)6810fb1340SPhilippe Mathieu-Daudé void cpu_check_irqs(CPUSPARCState *env)
6910fb1340SPhilippe Mathieu-Daudé {
7010fb1340SPhilippe Mathieu-Daudé     CPUState *cs;
7110fb1340SPhilippe Mathieu-Daudé 
7210fb1340SPhilippe Mathieu-Daudé     /* We should be holding the BQL before we mess with IRQs */
73195801d7SStefan Hajnoczi     g_assert(bql_locked());
7410fb1340SPhilippe Mathieu-Daudé 
7510fb1340SPhilippe Mathieu-Daudé     if (env->pil_in && (env->interrupt_index == 0 ||
7610fb1340SPhilippe Mathieu-Daudé                         (env->interrupt_index & ~15) == TT_EXTINT)) {
7710fb1340SPhilippe Mathieu-Daudé         unsigned int i;
7810fb1340SPhilippe Mathieu-Daudé 
7910fb1340SPhilippe Mathieu-Daudé         for (i = 15; i > 0; i--) {
8010fb1340SPhilippe Mathieu-Daudé             if (env->pil_in & (1 << i)) {
8110fb1340SPhilippe Mathieu-Daudé                 int old_interrupt = env->interrupt_index;
8210fb1340SPhilippe Mathieu-Daudé 
8310fb1340SPhilippe Mathieu-Daudé                 env->interrupt_index = TT_EXTINT | i;
8410fb1340SPhilippe Mathieu-Daudé                 if (old_interrupt != env->interrupt_index) {
8510fb1340SPhilippe Mathieu-Daudé                     cs = env_cpu(env);
8610fb1340SPhilippe Mathieu-Daudé                     trace_sun4m_cpu_interrupt(i);
8710fb1340SPhilippe Mathieu-Daudé                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
8810fb1340SPhilippe Mathieu-Daudé                 }
8910fb1340SPhilippe Mathieu-Daudé                 break;
9010fb1340SPhilippe Mathieu-Daudé             }
9110fb1340SPhilippe Mathieu-Daudé         }
9210fb1340SPhilippe Mathieu-Daudé     } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
9310fb1340SPhilippe Mathieu-Daudé         cs = env_cpu(env);
9410fb1340SPhilippe Mathieu-Daudé         trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
9510fb1340SPhilippe Mathieu-Daudé         env->interrupt_index = 0;
9610fb1340SPhilippe Mathieu-Daudé         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
9710fb1340SPhilippe Mathieu-Daudé     }
9810fb1340SPhilippe Mathieu-Daudé }
9910fb1340SPhilippe Mathieu-Daudé 
sparc_cpu_do_interrupt(CPUState * cs)10097a8ea5aSAndreas Färber void sparc_cpu_do_interrupt(CPUState *cs)
101ab3b491fSBlue Swirl {
10277976769SPhilippe Mathieu-Daudé     CPUSPARCState *env = cpu_env(cs);
10327103424SAndreas Färber     int cwp, intno = cs->exception_index;
104ab3b491fSBlue Swirl 
105ab3b491fSBlue Swirl     if (qemu_loglevel_mask(CPU_LOG_INT)) {
106ab3b491fSBlue Swirl         static int count;
107ab3b491fSBlue Swirl         const char *name;
108ab3b491fSBlue Swirl 
109ab3b491fSBlue Swirl         if (intno < 0 || intno >= 0x100) {
110ab3b491fSBlue Swirl             name = "Unknown";
111ab3b491fSBlue Swirl         } else if (intno >= 0x80) {
112ab3b491fSBlue Swirl             name = "Trap Instruction";
113ab3b491fSBlue Swirl         } else {
11486e8c353SPhilippe Mathieu-Daudé             name = excp_name_str(intno);
115ab3b491fSBlue Swirl         }
116ab3b491fSBlue Swirl 
117b884fc5eSRichard Henderson         qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
118a0762859SAndreas Färber         log_cpu_state(cs, 0);
119ab3b491fSBlue Swirl         count++;
120ab3b491fSBlue Swirl     }
121c35c8d4dSCarl Hauser #ifndef CONFIG_USER_ONLY
122ab3b491fSBlue Swirl     if (env->psret == 0) {
12327103424SAndreas Färber         if (cs->exception_index == 0x80 &&
124576e1c4cSIgor Mammedov             env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
125cf83f140SEric Blake             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
12696d922a6SFabien Chouteau         } else {
12786e8c353SPhilippe Mathieu-Daudé             cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
12886e8c353SPhilippe Mathieu-Daudé                           "Error state",
12986e8c353SPhilippe Mathieu-Daudé                       cs->exception_index, excp_name_str(cs->exception_index));
13096d922a6SFabien Chouteau         }
131ab3b491fSBlue Swirl         return;
132ab3b491fSBlue Swirl     }
133c35c8d4dSCarl Hauser     if (intno == TT_FP_EXCP) {
134c35c8d4dSCarl Hauser         /*
135c35c8d4dSCarl Hauser          * The sparc32 fpu has three states related to exception handling.
136c35c8d4dSCarl Hauser          * The FPop that signals an exception transitions from fp_execute
137c35c8d4dSCarl Hauser          * to fp_exception_pending.  A subsequent FPop transitions from
138c35c8d4dSCarl Hauser          * fp_exception_pending to fp_exception, which forces the trap.
139c35c8d4dSCarl Hauser          *
140c35c8d4dSCarl Hauser          * If the queue is not empty, this trap is due to execution of an
141c35c8d4dSCarl Hauser          * illegal FPop while in fp_exception state.  Here we are to
142c35c8d4dSCarl Hauser          * re-enter fp_exception_pending state without queuing the insn.
143c35c8d4dSCarl Hauser          *
144c35c8d4dSCarl Hauser          * We do not model the fp_exception_pending state, but instead
145c35c8d4dSCarl Hauser          * skip directly to fp_exception state.  We advance pc/npc to
146c35c8d4dSCarl Hauser          * mimic delayed trap delivery as if by the subsequent insn.
147c35c8d4dSCarl Hauser          */
148c35c8d4dSCarl Hauser         if (!env->fsr_qne) {
149c35c8d4dSCarl Hauser             env->fsr_qne = FSR_QNE;
150c35c8d4dSCarl Hauser             env->fq.s.addr = env->pc;
151c35c8d4dSCarl Hauser             env->fq.s.insn = cpu_ldl_code(env, env->pc);
152c35c8d4dSCarl Hauser         }
153c35c8d4dSCarl Hauser         env->pc = env->npc;
154c35c8d4dSCarl Hauser         env->npc = env->npc + 4;
155c35c8d4dSCarl Hauser     }
156ab3b491fSBlue Swirl #endif
157ab3b491fSBlue Swirl     env->psret = 0;
158ab3b491fSBlue Swirl     cwp = cpu_cwp_dec(env, env->cwp - 1);
159ab3b491fSBlue Swirl     cpu_set_cwp(env, cwp);
160ab3b491fSBlue Swirl     env->regwptr[9] = env->pc;
161ab3b491fSBlue Swirl     env->regwptr[10] = env->npc;
162ab3b491fSBlue Swirl     env->psrps = env->psrs;
163ab3b491fSBlue Swirl     env->psrs = 1;
164ab3b491fSBlue Swirl     env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
165ab3b491fSBlue Swirl     env->pc = env->tbr;
166ab3b491fSBlue Swirl     env->npc = env->pc + 4;
16727103424SAndreas Färber     cs->exception_index = -1;
168ab3b491fSBlue Swirl 
169ab3b491fSBlue Swirl #if !defined(CONFIG_USER_ONLY)
170ab3b491fSBlue Swirl     /* IRQ acknowledgment */
171ab3b491fSBlue Swirl     if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
172a318da6bSClément Chigot         env->qemu_irq_ack(env, intno);
173ab3b491fSBlue Swirl     }
174ab3b491fSBlue Swirl #endif
175ab3b491fSBlue Swirl }
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