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/qemu/docs/devel/testing/
H A Dacpi-bits.rst2 ACPI/SMBIOS testing using biosbits
10 executes the bios components such as acpi and smbios tables directly through
11 acpica bios interpreter (a freely available C based library written by Intel,
13 operating system getting involved in between. Bios-bits has python integration
15 python instead of bash-ish (grub's native scripting language).
22 Another issue is that we cannot exercise bios components such as ACPI and
32 bios-bits very attractive for testing bioses. More details on the inspiration
41 author's FOSDEM presentation <FOSDEM_>`__ on this bios-bits based test framework.
45 .. _gitlab: https://gitlab.com/qemu-project/biosbits-bits
46 …rg/2024/schedule/event/fosdem-2024-2262-exercising-qemu-generated-acpi-smbios-tables-using-biosbit…
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/qemu/docs/specs/
H A Dacpi_nvdimm.rst1 QEMU<->ACPI BIOS NVDIMM interface
4 QEMU supports NVDIMM via ACPI. This document describes the basic concepts of
5 NVDIMM ACPI and the interface between QEMU and the ACPI BIOS.
7 NVDIMM ACPI Background
8 ----------------------
10 NVDIMM is introduced in ACPI 6.0 which defines an NVDIMM root device under
12 to be supported by platform, platform firmware also exposes an ACPI
20 This is an example from ACPI 6.0, a platform contains one NVDIMM::
76 The detailed definition of the structure can be found at ACPI 6.0: 5.2.25
80 --------------------------
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H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
5 describes the interface between QEMU and the ACPI BIOS.
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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H A Dtpm.rst1 .. _tpm-device:
7 Guest-side hardware interface
11 -------------
20 0xfed40000-0xfed44fff available to the guest operating system.
23 - ``hw/tpm/tpm_tis_common.c``
24 - ``hw/tpm/tpm_tis_isa.c``
25 - ``hw/tpm/tpm_tis_sysbus.c``
26 - ``hw/tpm/tpm_tis_i2c.c``
27 - ``hw/tpm/tpm_tis.h``
34 based emulation machines. This device only supports the TPM 2 protocol.
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H A Dppc-spapr-numa.rst6 Information Table (SLIT) in ACPI. The logic is explained in the LOPAPR
12 --------------------------------------------
19 bit 0 of byte 5 of the ibm,architecture-vec-5 property. The format with
28 Mem M1 ---- Proc P1 |
29 ----------------- | Socket S1 ---|
32 Mem M2 ---- Proc P2 | |
33 ----------------- | Socket S2 ---|
46 Relative Performance Distance and ibm,associativity-reference-points
47 --------------------------------------------------------------------
49 The ibm,associativity-reference-points property is an array that is used
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/qemu/tests/uefi-test-tools/UefiTestToolsPkg/Include/Guid/
H A DBiosTablesTest.h2 Expose the address(es) of the ACPI RSD PTR table(s) and the SMBIOS entry
3 point(s) in a MB-aligned structure to the hypervisor.
5 The hypervisor locates the MB-aligned structure based on the signature GUID
7 address(es) are retrieved, the hypervisor may perform various ACPI and SMBIOS
10 This feature is a development aid, for supporting ACPI and SMBIOS table unit
18 <http://opensource.org/licenses/bsd-license.php>.
46 // The signature GUID is written to the MB-aligned structure from
50 // bit-flipping occurs in order not to store the actual GUID in any UEFI
57 // Rsdp10 is the guest-physical address of the ACPI 1.0 specification RSD PTR
58 // table, in 8-byte little endian representation. Rsdp20 is the same, for the
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/qemu/hw/acpi/
H A Dviot.c2 * ACPI Virtual I/O Translation table implementation
4 * SPDX-License-Identifier: GPL-2.0-or-later
7 #include "hw/acpi/acpi.h"
8 #include "hw/acpi/aml-build.h"
9 #include "hw/acpi/viot.h"
49 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; in enumerate_pci_host_bridges()
72 if (range_a->min_bus < range_b->min_bus) { in pci_host_range_compare()
73 return -1; in pci_host_range_compare()
74 } else if (range_a->min_bus > range_b->min_bus) { in pci_host_range_compare()
82 * Generate a VIOT table with one PCI-based virtio-iommu that manages PCI
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H A Dpcihp.c2 * QEMU<->ACPI BIOS PCI hotplug interface
4 * QEMU supports PCI hotplug via ACPI. This module
5 * implements the interface between QEMU and the ACPI BIOS.
6 * Interface specification - see docs/specs/acpi_pci_hotplug.txt
23 * Contributions after 2012-01-13 are licensed under the terms of the
28 #include "hw/acpi/pcihp.h"
30 #include "hw/pci-host/i440fx.h"
35 #include "hw/pci-bridge/xio3130_downstream.h"
36 #include "hw/i386/acpi-build.h"
37 #include "hw/acpi/acpi.h"
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H A Dghes.c24 #include "hw/acpi/ghes.h"
25 #include "hw/acpi/aml-build.h"
26 #include "qemu/error-report.h"
27 #include "hw/acpi/generic_event_device.h"
45 * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data,
46 * Table 18-343 Generic Error Data Entry
58 * ACPI 6.2: 18.3.2.7.1 Generic Error Data,
59 * Table 18-380 Generic Error Status Block
75 * ACPI 4.0: 17.3.2.7 Hardware Error Notification
105 * ACPI 6.1: 18.3.2.7.1 Generic Error Data
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H A Dich9.c2 * ACPI implementation
9 * This is based on acpi.c.
23 * Contributions after 2012-01-13 are licensed under the terms of the
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/ich9_tco.h"
38 #include "hw/acpi/ich9_timer.h"
41 #include "hw/mem/pc-dimm.h"
47 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_pm_update_sci_fn()
53 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); in ich9_gpe_readb()
60 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); in ich9_gpe_writeb()
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/qemu/docs/system/i386/
H A Dmicrovm.rst7 It's a minimalist machine type without ``PCI`` nor ``ACPI`` support,
8 designed for short-lived guests. microvm also establishes a baseline
14 -----------------
18 - ISA bus
19 - i8259 PIC (optional)
20 - i8254 PIT (optional)
21 - MC146818 RTC (optional)
22 - One ISA serial port (optional)
23 - LAPIC
24 - IOAPIC (with kernel-irqchip=split by default)
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H A Dsgx.rst5 --------
16 -----------
36 require -maxmem as EPC is not treated as {cold,hot}plugged memory.
43 The following QEMU snippet creates two EPC sections, with 64M pre-allocated
46 -object memory-backend-epc,id=mem1,size=64M,prealloc=on \
47 -object memory-backend-epc,id=mem2,size=28M \
48 -M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
79 in any of QEMU's built-in CPU configuration. To expose SGX (and SGX Launch
80 Control) to a guest, you must either use ``-cpu host`` to pass-through the
81 host CPU model, or explicitly enable SGX when using a built-in CPU model,
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/qemu/hw/i386/
H A Dfw_cfg.c7 * Philippe Mathieu-Daudé <philmd@redhat.com>
9 * SPDX-License-Identifier: GPL-2.0-or-later
12 * See the COPYING file in the top-level directory.
17 #include "hw/acpi/acpi.h"
18 #include "hw/acpi/aml-build.h"
73 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); in fw_cfg_build_smbios()
76 if (pcmc->smbios_defaults) { in fw_cfg_build_smbios()
78 smbios_set_defaults("QEMU", mc->desc, mc->name); in fw_cfg_build_smbios()
82 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); in fw_cfg_build_smbios()
84 if (pcmc->smbios_legacy_mode) { in fw_cfg_build_smbios()
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H A Dacpi-build.c1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
26 #include "acpi-build.h"
27 #include "acpi-common.h"
29 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
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H A Dpc_q35.c2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
10 * This is based on pc.c, but heavily modified.
33 #include "hw/acpi/acpi.h"
34 #include "hw/char/parallel-isa.h"
41 #include "hw/pci-host/q35.h"
43 #include "hw/qdev-properties.h"
48 #include "hw/virtio/virtio-iommu.h"
51 #include "hw/ide/ahci-pci.h"
55 #include "hw/usb/hcd-uhci.h"
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/qemu/include/hw/arm/
H A Dvirt.h20 * + we can only present devices whose Linux drivers will work based
22 * + we want to present a very stripped-down minimalist platform,
47 /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
122 bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */
153 OnOffAuto acpi; member
192 if (vms->gic_version == VIRT_GIC_VERSION_3) { in virt_redist_capacity()
197 return vms->memmap[region].size / redist_size; in virt_redist_capacity()
205 assert(vms->gic_version != VIRT_GIC_VERSION_2); in virt_gicv3_redist_region_count()
207 return (MACHINE(vms)->smp.cpus > redist0_capacity && in virt_gicv3_redist_region_count()
208 vms->highmem_redists) ? 2 : 1; in virt_gicv3_redist_region_count()
/qemu/hw/usb/
H A Dhcd-xhci-sysbus.c2 * USB xHCI controller for system-bus interface
3 * Based on hcd-echi-sysbus.c
5 * SPDX-FileCopyrightText: 2020 Xilinx
6 * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "hw/qdev-properties.h"
15 #include "hcd-xhci-sysbus.h"
16 #include "hw/acpi/aml-build.h"
23 qemu_set_irq(s->irq[n], level); in xhci_sysbus_intr_raise()
32 device_cold_reset(DEVICE(&s->xhci)); in xhci_sysbus_reset()
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/qemu/hw/arm/
H A Dvirt-acpi-build.c1 /* Support for generating ACPI tables and passing them to Guests
3 * ARM virt ACPI generation
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
32 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
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/qemu/tests/tcg/i386/system/
H A Dboot.S2 * i386 boot code, based on qemu-bmibug.
8 * See the COPYING file in the top-level directory.
10 * SPDX-License-Identifier: GPL-2.0-or-later
15 /* Multi-boot header */
19 .int -(0x10000+0x1BADB002)
69 push $((32 * 8 - 1) << 16)
79 _exit: /* output any non-zero result in eax to isa-debug-exit device */
84 1: /* QEMU ACPI poweroff */
147 .short gdt_en - gdt - 1
/qemu/include/standard-headers/linux/
H A Dvmclock-abi.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
4 * This structure provides a vDSO-style clock to VM guests, exposing the
30 * action, even when using a vDSO-style method to get the time instead of a
49 * nascent virtio-rtc standard, as a virtio-rtc that does not address the live
52 * the virtio-rtc proposal. The structure can also be exposed through an ACPI
61 #include "standard-headers/linux/types.h"
74 #define VMCLOCK_TIME_UTC 0 /* Since 1970-01-01 00:00:00z */
75 #define VMCLOCK_TIME_TAI 1 /* Since 1970-01-01 00:00:00z */
80 /* NON-CONSTANT FIELDS PROTECTED BY SEQCOUNT LOCK */
83 * This field changes to another non-repeating value when the CPU
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/qemu/include/hw/xen/interface/hvm/
H A Dparams.h1 /* SPDX-License-Identifier: MIT */
34 * How should CPU0 event-channel notifications be delivered?
36 * If val == 0 then CPU0 event-channel notifications are not delivered.
62 * val[15:8] is interrupt flag of the PPI used by event-channel:
65 * val[7:0] is a PPI number used by event-channel.
74 * These are not used by Xen. They are here for convenience of HVM-guest
89 …* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hyperviso…
99 * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
100 * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
101 * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
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/qemu/hw/isa/
H A Dlpc_ich9.c10 * This is based on piix.c, but heavily modified.
44 #include "hw/acpi/acpi.h"
45 #include "hw/acpi/ich9.h"
46 #include "hw/acpi/ich9_timer.h"
48 #include "hw/qdev-properties.h"
54 #include "hw/acpi/acpi_aml_interface.h"
90 /* D{25 - 31}IR, but D30IR is read only to 0. */ in ich9_cc_update()
95 ich9_cc_update_ir(lpc->irr[slot], in ich9_cc_update()
96 pci_get_word(lpc->chip_config + *offset)); in ich9_cc_update()
102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. in ich9_cc_update()
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/qemu/qapi/
H A Dmachine.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
12 { 'include': 'machine-common.json' }
18 # targets. Run "./configure --help" in the project root directory,
19 # and look for the \*-softmmu targets near the "--target-list" option.
30 # "qemu-system-" prefix to produce the corresponding QEMU
31 # executable name. This is true even for "qemu-system-x86_64".
52 'data': [ 'uninitialized', 'stopped', 'check-stop', 'operating', 'load' ] }
59 # @cpu-state: the virtual CPU's state
68 'data': { 'cpu-state': 'S390CpuState',
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/qemu/hw/riscv/
H A Dvirt.c2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
36 #include "hw/riscv/riscv-iommu-bits.h"
46 #include "hw/platform-bus.h"
55 #include "hw/pci-host/gpex.h"
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/qemu/
H A DMAINTAINERS10 consult qemu-devel and not any specific individual privately.
23 W: Web-page with status/info
24 Q: Patchwork web based patch tracking system site
59 ------------------------------
63 L: qemu-devel@nongnu.org
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
75 F: docs/devel/build-environment.rst
76 F: docs/devel/code-of-conduct.rst
78 F: docs/devel/conflict-resolution.rst
80 F: docs/devel/submitting-a-patch.rst
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