1 /*
2 * QEMU fw_cfg helpers (X86 specific)
3 *
4 * Copyright (c) 2019 Red Hat, Inc.
5 *
6 * Author:
7 * Philippe Mathieu-Daudé <philmd@redhat.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 */
14
15 #include "qemu/osdep.h"
16 #include "system/numa.h"
17 #include "hw/acpi/acpi.h"
18 #include "hw/acpi/aml-build.h"
19 #include "hw/firmware/smbios.h"
20 #include "hw/i386/fw_cfg.h"
21 #include "hw/timer/hpet.h"
22 #include "hw/nvram/fw_cfg.h"
23 #include "e820_memory_layout.h"
24 #include "kvm/kvm_i386.h"
25 #include "qapi/error.h"
26 #include CONFIG_DEVICES
27 #include "target/i386/cpu.h"
28
29 #if !defined(CONFIG_HPET)
30 struct hpet_fw_config hpet_fw_cfg = {.count = UINT8_MAX};
31 #endif
32
fw_cfg_arch_key_name(uint16_t key)33 const char *fw_cfg_arch_key_name(uint16_t key)
34 {
35 static const struct {
36 uint16_t key;
37 const char *name;
38 } fw_cfg_arch_wellknown_keys[] = {
39 {FW_CFG_ACPI_TABLES, "acpi_tables"},
40 {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
41 {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
42 {FW_CFG_HPET, "hpet"},
43 };
44
45 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
46 if (fw_cfg_arch_wellknown_keys[i].key == key) {
47 return fw_cfg_arch_wellknown_keys[i].name;
48 }
49 }
50 return NULL;
51 }
52
53 /* Add etc/e820 late, once all regions should be present */
fw_cfg_add_e820(FWCfgState * fw_cfg)54 void fw_cfg_add_e820(FWCfgState *fw_cfg)
55 {
56 struct e820_entry *table;
57 int nr_e820 = e820_get_table(&table);
58
59 fw_cfg_add_file(fw_cfg, "etc/e820", table, nr_e820 * sizeof(*table));
60 }
61
fw_cfg_build_smbios(PCMachineState * pcms,FWCfgState * fw_cfg,SmbiosEntryPointType ep_type)62 void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState *fw_cfg,
63 SmbiosEntryPointType ep_type)
64 {
65 #ifdef CONFIG_SMBIOS
66 uint8_t *smbios_tables, *smbios_anchor;
67 size_t smbios_tables_len, smbios_anchor_len;
68 struct smbios_phys_mem_area *mem_array;
69 unsigned i, array_count;
70 MachineState *ms = MACHINE(pcms);
71 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72 MachineClass *mc = MACHINE_GET_CLASS(pcms);
73 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
74 int nr_e820;
75
76 if (pcmc->smbios_defaults) {
77 /* These values are guest ABI, do not change */
78 smbios_set_defaults("QEMU", mc->desc, mc->name);
79 }
80
81 /* tell smbios about cpuid version and features */
82 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
83
84 if (pcmc->smbios_legacy_mode) {
85 smbios_tables = smbios_get_table_legacy(&smbios_tables_len,
86 &error_fatal);
87 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
88 smbios_tables, smbios_tables_len);
89 return;
90 }
91
92 /* build the array of physical mem area from e820 table */
93 nr_e820 = e820_get_table(NULL);
94 mem_array = g_malloc0(sizeof(*mem_array) * nr_e820);
95 for (i = 0, array_count = 0; i < nr_e820; i++) {
96 uint64_t addr, len;
97
98 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
99 mem_array[array_count].address = addr;
100 mem_array[array_count].length = len;
101 array_count++;
102 }
103 }
104 smbios_get_tables(ms, ep_type, mem_array, array_count,
105 &smbios_tables, &smbios_tables_len,
106 &smbios_anchor, &smbios_anchor_len,
107 &error_fatal);
108 g_free(mem_array);
109
110 if (smbios_anchor) {
111 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
112 smbios_tables, smbios_tables_len);
113 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
114 smbios_anchor, smbios_anchor_len);
115 }
116 #endif
117 }
118
fw_cfg_arch_create(MachineState * ms,uint16_t boot_cpus,uint16_t apic_id_limit)119 FWCfgState *fw_cfg_arch_create(MachineState *ms,
120 uint16_t boot_cpus,
121 uint16_t apic_id_limit)
122 {
123 FWCfgState *fw_cfg;
124 uint64_t *numa_fw_cfg;
125 int i;
126 MachineClass *mc = MACHINE_GET_CLASS(ms);
127 const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
128 int nb_numa_nodes = ms->numa_state->num_nodes;
129
130 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
131 &address_space_memory);
132 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
133
134 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
135 *
136 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
137 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
138 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
139 * for CPU hotplug also uses APIC ID and not "CPU index".
140 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
141 * but the "limit to the APIC ID values SeaBIOS may see".
142 *
143 * So for compatibility reasons with old BIOSes we are stuck with
144 * "etc/max-cpus" actually being apic_id_limit
145 */
146 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
147 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
148 if (acpi_builtin()) {
149 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
150 acpi_tables, acpi_tables_len);
151 }
152 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
153
154 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_fw_cfg, sizeof(hpet_fw_cfg));
155 /* allocate memory for the NUMA channel: one (64bit) word for the number
156 * of nodes, one word for each VCPU->node and one word for each node to
157 * hold the amount of memory.
158 */
159 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
160 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
161 for (i = 0; i < cpus->len; i++) {
162 unsigned int apic_id = cpus->cpus[i].arch_id;
163 assert(apic_id < apic_id_limit);
164 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
165 }
166 for (i = 0; i < nb_numa_nodes; i++) {
167 numa_fw_cfg[apic_id_limit + 1 + i] =
168 cpu_to_le64(ms->numa_state->nodes[i].node_mem);
169 }
170 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
171 (1 + apic_id_limit + nb_numa_nodes) *
172 sizeof(*numa_fw_cfg));
173
174 return fw_cfg;
175 }
176
fw_cfg_build_feature_control(MachineState * ms,FWCfgState * fw_cfg)177 void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
178 {
179 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
180 CPUX86State *env = &cpu->env;
181 uint32_t unused, ebx, ecx, edx;
182 uint64_t feature_control_bits = 0;
183 uint64_t *val;
184
185 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
186 if (ecx & CPUID_EXT_VMX) {
187 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
188 }
189
190 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
191 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
192 (env->mcg_cap & MCG_LMCE_P)) {
193 feature_control_bits |= FEATURE_CONTROL_LMCE;
194 }
195
196 if (env->cpuid_level >= 7) {
197 cpu_x86_cpuid(env, 0x7, 0, &unused, &ebx, &ecx, &unused);
198 if (ebx & CPUID_7_0_EBX_SGX) {
199 feature_control_bits |= FEATURE_CONTROL_SGX;
200 }
201 if (ecx & CPUID_7_0_ECX_SGX_LC) {
202 feature_control_bits |= FEATURE_CONTROL_SGX_LC;
203 }
204 }
205
206 if (!feature_control_bits) {
207 return;
208 }
209
210 val = g_malloc(sizeof(*val));
211 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
212 fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
213 }
214
215 #ifdef CONFIG_ACPI
fw_cfg_add_acpi_dsdt(Aml * scope,FWCfgState * fw_cfg)216 void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg)
217 {
218 /*
219 * when using port i/o, the 8-bit data register *always* overlaps
220 * with half of the 16-bit control register. Hence, the total size
221 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
222 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4
223 */
224 Object *obj = OBJECT(fw_cfg);
225 uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ?
226 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
227 FW_CFG_CTL_SIZE;
228 Aml *dev = aml_device("FWCF");
229 Aml *crs = aml_resource_template();
230
231 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
232
233 /* device present, functioning, decoding, not shown in UI */
234 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
235
236 aml_append(crs,
237 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size));
238
239 aml_append(dev, aml_name_decl("_CRS", crs));
240 aml_append(scope, dev);
241 }
242 #endif
243