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Searched +full:0 +full:x2000 (Results 1 – 12 of 12) sorted by relevance

/kvm-unit-tests/lib/x86/asm/
H A Ddebugreg.h11 #define DR6_ACTIVE_LOW 0xffff0ff0
12 #define DR6_VOLATILE 0x0001e80f
15 #define DR6_TRAP0 BIT(0) /* DR0 matched */
21 #define DR6_BUS_LOCK BIT(11) /* Bus lock 0x800 */
22 #define DR6_BD BIT(13) /* General Detect 0x2000 */
23 #define DR6_BS BIT(14) /* Single-Step 0x4000 */
24 #define DR6_BT BIT(15) /* Task Switch 0x8000 */
25 #define DR6_RTM BIT(16) /* RTM / TSX 0x10000 */
27 #define DR7_FIXED_1 0x00000400 /* init/reset value, too */
28 #define DR7_VOLATILE 0xffff2bff
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/kvm-unit-tests/s390x/snippets/c/
H A Dflat.lds.S15 * address 0x4000 (cstart.S .init).
17 . = 0;
19 LONG(0x00080000)
20 LONG(0x80004000)
22 . = 0x1a0;
23 QUAD(0x0000000180000000)
24 QUAD(0x0000000000004000)
26 . = 0x4000;
28 * The stack grows down from 0x4000 to 0x2000, we pre-allocoate
33 /* Start text 0x4000 */
/kvm-unit-tests/lib/s390x/
H A Duv.h44 return vm->sblk->icptcode == ICPT_VALIDITY && (vir & 0xff00) == 0x2000; in uv_validity_check()
H A Dsclp.h16 #define SCLP_CMD_CODE_MASK 0xffff00ff
19 #define SCLP_READ_CPU_INFO 0x00010001
20 #define SCLP_CMDW_READ_SCP_INFO 0x00020001
21 #define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001
22 #define SCLP_READ_STORAGE_ELEMENT_INFO 0x00040001
23 #define SCLP_ATTACH_STORAGE_ELEMENT 0x00080001
24 #define SCLP_ASSIGN_STORAGE 0x000D0001
25 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
26 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
27 #define SCLP_CMD_WRITE_EVENT_MASK 0x00780005
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/kvm-unit-tests/lib/powerpc/asm/
H A Dreg.h8 #define SPR_DSISR 0x012
9 #define SPR_DAR 0x013
10 #define SPR_DEC 0x016
11 #define SPR_SRR0 0x01a
12 #define SPR_SRR1 0x01b
13 #define SRR1_PREFIX UL(0x20000000)
14 #define SPR_PIDR 0x030
15 #define SPR_FSCR 0x099
16 #define FSCR_PREFIX UL(0x2000)
17 #define SPR_HFSCR 0x0be
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/kvm-unit-tests/x86/
H A Dinit.c5 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
6 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
7 #define KBD_CCMD_RESET 0xFE /* CPU reset */
11 while (inb(0x64) & 2); in kbd_cmd()
12 outb(val, 0x64); in kbd_cmd()
18 while (inb(0x64) & 2); in kbd_in()
19 return inb(0x60); in kbd_in()
25 while (inb(0x64) & 2); in kbd_out()
26 outb(val, 0x60); in kbd_out()
31 outb(reg, 0x70); in rtc_out()
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H A Dsvm_tests.c16 #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f
61 asm volatile ("vmrun %0" : : "a"(virt_to_phys(vmcb))); in test_vmrun()
89 case 0: in finished_rsm_intercept()
91 report_fail("VMEXIT not due to rsm. Exit reason 0x%x", in finished_rsm_intercept()
101 report_fail("VMEXIT not due to #UD. Exit reason 0x%x", in finished_rsm_intercept()
123 asm volatile ("mov %%cr3, %0" : "=r"(test->scratch) : : "memory"); in test_cr3_intercept()
146 mmio_insn = 0x90d8200f; // mov %cr3, %rax; nop in corrupt_cr3_intercept_bypass()
158 ulong a = 0xa0000; in test_cr3_intercept_bypass()
164 asm volatile ("mmio_insn: mov %0, (%0); nop" in test_cr3_intercept_bypass()
172 vmcb->control.intercept_dr_read = 0xff; in prepare_dr_intercept()
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/kvm-unit-tests/lib/x86/
H A Dusermode.c14 #define USERMODE_STACK_SIZE 0x2000
15 #define RET_TO_KERNEL_IRQ 0x20
39 volatile uint64_t rax = 0; in run_in_user()
43 *raised_vector = 0; in run_in_user()
48 if (setjmp(jmpbuf) != 0) { in run_in_user()
51 return 0; in run_in_user()
109 [rsp0]"=m"(tss[0].rsp0) in run_in_user()
H A Dapic.c28 asm volatile ("out %0, %1" : : "a"(data), "d"(port)); in outb()
33 apic_write(APIC_EOI, 0); in eoi()
76 asm volatile ("wrmsr" : : "a"(val), "d"(0), "c"(APIC_BASE_MSR + reg/16)); in x2apic_write()
112 return (apic_read(reg) & (1 << n)) != 0; in apic_read_bit()
130 asm volatile ("mov %%cr8, %0" : "=r"(tpr)); in apic_get_tpr()
140 asm volatile ("mov %0, %%cr8" : : "r"((unsigned long) tpr)); in apic_set_tpr()
150 asm ("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(1)); in enable_x2apic()
159 return 0; in enable_x2apic()
182 xapic_write(APIC_SPIV, 0x1ff); in reset_apic()
188 return *(volatile u32 *)(g_ioapic + 0x10); in ioapic_read_reg()
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/kvm-unit-tests/s390x/
H A Ddiag308.c3 * Diagnose 0x308 hypercall tests
18 asm volatile ("diag %0,%1,0x308" :: "d"(0), "d"(3)); in test_priv()
24 * Check that diag308 with subcode 0 and 1 loads the PSW at address 0, i.e.
30 report(diag308_load_reset(0), "load modified clear done"); in test_subcode0()
42 register unsigned long r3 asm("9") = 0x2000; in test_uneven_reg()
46 asm volatile ("diag %0,%1,0x308" :: "d"(r3), "d"(sc)); in test_uneven_reg()
59 asm volatile ("diag %0,%1,0x308" :: "d"(addr), "d"(sc)); in test_unaligned_address()
79 int subcodes[] = { 0x101, 0xffff, 0x10001, -1 }; in test_unsupported_subcode()
82 for (idx = 0; idx < ARRAY_SIZE(subcodes); idx++) { in test_unsupported_subcode()
83 report_prefix_pushf("0x%04x", subcodes[idx]); in test_unsupported_subcode()
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/kvm-unit-tests/lib/linux/
H A Dpci_regs.h30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
33 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
34 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
35 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
36 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
37 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
38 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
39 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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/kvm-unit-tests/powerpc/
H A Dsprs.c41 "1: mflr %0 \n" in __mfspr()
42 " addi %0, %0, (2f-1b) \n" in __mfspr()
43 " add %0, %0, %2 \n" in __mfspr()
44 " mtctr %0 \n" in __mfspr()
47 ".LSPR=0 \n" in __mfspr()
68 "1: mflr %0 \n" in __mtspr()
69 " addi %0, %0, (2f-1b) \n" in __mtspr()
70 " add %0, %0, %2 \n" in __mtspr()
71 " mtctr %0 \n" in __mtspr()
74 ".LSPR=0 \n" in __mtspr()
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