28 	asm volatile ("out %0, %1" : : "a"(data), "d"(port));  in outb()
33 	apic_write(APIC_EOI, 0);  in eoi()
76 	asm volatile ("wrmsr" : : "a"(val), "d"(0), "c"(APIC_BASE_MSR + reg/16));  in x2apic_write()
112 	return (apic_read(reg) & (1 << n)) != 0;  in apic_read_bit()
130 	asm volatile ("mov %%cr8, %0" : "=r"(tpr));  in apic_get_tpr()
140 	asm volatile ("mov %0, %%cr8" : : "r"((unsigned long) tpr));  in apic_set_tpr()
150 	asm ("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(1));  in enable_x2apic()
159 		return 0;  in enable_x2apic()
182 	xapic_write(APIC_SPIV, 0x1ff);  in reset_apic()
188 	return *(volatile u32 *)(g_ioapic + 0x10);  in ioapic_read_reg()
194 	*(volatile u32 *)(g_ioapic + 0x10) = value;  in ioapic_write_reg()
199 	ioapic_write_reg(0x10 + line * 2 + 0, ((u32 *)&e)[0]);  in ioapic_write_redir()
200 	ioapic_write_reg(0x10 + line * 2 + 1, ((u32 *)&e)[1]);  in ioapic_write_redir()
207 	((u32 *)&e)[0] = ioapic_read_reg(0x10 + line * 2 + 0);  in ioapic_read_redir()
208 	((u32 *)&e)[1] = ioapic_read_reg(0x10 + line * 2 + 1);  in ioapic_read_redir()
218 		.delivery_mode = 0,  in ioapic_set_redir()
235 	asm volatile("out %0, %1" : : "a"((u8)val), "d"((u16)(0x2000 + line)));  in set_irq_line()
241 	xapic_write(APIC_SPIV, 0x1ff);  in enable_apic()
246 	outb(0xff, 0x21);  in mask_pic_interrupts()
247 	outb(0xff, 0xa1);  in mask_pic_interrupts()
252 	unsigned int i, j = 0;  in init_apic_map()
254 	for (i = 0; i < MAX_TEST_CPUS; i++) {  in init_apic_map()
281 	apic_write(APIC_TMICT, 0);  in apic_stop_timer()