Merge tag 'kvm-x86-2023.09.01' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new testcases, and a few generic changes

- Fix a bug in runtime.bash that caused it t

Merge tag 'kvm-x86-2023.09.01' of https://github.com/kvm-x86/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new testcases, and a few generic changes

- Fix a bug in runtime.bash that caused it to mishandle "check" strings with
multiple entries, e.g. a test that depends on multiple module params
- Make the PMU tests depend on vPMU support being enabled in KVM
- Fix PMU's forced emulation test on CPUs with full-width writes
- Add a PMU testcase for measuring TSX transactional cycles
- Nested SVM testcase for virtual NMIs
- Move a pile of code to ASM_TRY() and "safe" helpers
- Set up the guest stack in the LBRV tests so that the tests don't fail if the
compiler decides to generate function calls in guest code
- Ignore the "mispredict" flag in nSVM's LBRV tests to fix false failures
- Clean up usage of helpers that disable interrupts, e.g. stop inserting
unnecessary nops
- Add helpers to dedup code for programming the APIC timer
- Fix a variety of bugs in nVMX testcases related to being a 64-bit host

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x86: add few helper functions for apic local timer

Add a few functions to apic.c to make it easier to enable and disable
the local apic timer.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Li

x86: add few helper functions for apic local timer

Add a few functions to apic.c to make it easier to enable and disable
the local apic timer.

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Link: https://lore.kernel.org/r/20221122161152.293072-4-mlevitsk@redhat.com
[sean: massage comments, use C-style]
Signed-off-by: Sean Christopherson <seanjc@google.com>

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Merge tag 'for_paolo' of https://github.com/sean-jc/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new sub-tests:

- Bug fix for the VMX-preemption timer expiration test
- Refactor SVM tests

Merge tag 'for_paolo' of https://github.com/sean-jc/kvm-unit-tests into HEAD

x86 fixes, cleanups, and new sub-tests:

- Bug fix for the VMX-preemption timer expiration test
- Refactor SVM tests to split out NPT tests
- Add tests for MCE banks to MSR test
- Add SMP Support for x86 UEFI tests
- x86: nVMX: Add VMXON #UD test (and exception cleanup)
- PMU cleanup and related nVMX bug fixes

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x86: Provide a common 64-bit AP entrypoint for EFI and non-EFI

ap_start64() currently serves as the 64-bit entrypoint for non-EFI
tests.

Having ap_start64() and save_id() written in asm prevents sh

x86: Provide a common 64-bit AP entrypoint for EFI and non-EFI

ap_start64() currently serves as the 64-bit entrypoint for non-EFI
tests.

Having ap_start64() and save_id() written in asm prevents sharing these
routines between EFI and non-EFI tests.

Rewrite them in C and use ap_start64 as the 64-bit entrypoint in the EFI
boot flow.

With this, EFI tests support -smp > 1. smptest.efi now passes.

Cc: Andrew Jones <drjones@redhat.com>
Cc: Marc Orr <marcorr@google.com>
Cc: Zixuan Wang <zxwang42@gmail.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: David Rientjes <rientjes@google.com>
Cc: Thomas.Lendacky@amd.com
Cc: Joerg Roedel <jroedel@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Signed-off-by: Varad Gautam <varad.gautam@suse.com>
[sean: reset APIC before TSS setup, halt in AP wait loop, add comment]
Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220615232943.1465490-12-seanjc@google.com

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x86: apic: Play nice with x2APIC being enabled when getting "pre-boot" ID

Retrieve the "pre-boot" APIC ID via the x2APIC interface if x2APIC is
enabled instead of assuming that the APIC is always in

x86: apic: Play nice with x2APIC being enabled when getting "pre-boot" ID

Retrieve the "pre-boot" APIC ID via the x2APIC interface if x2APIC is
enabled instead of assuming that the APIC is always in xAPIC mode. EFI
has a catch-22 where it needs the APID ID to initialize the per-vCPU
GS.base, but calling reset_apic() = >disable_apic() needs GS.base to be
correctly initialized in order to set the correct APIC ops. Play nice
with either xAPIC or x2APIC so that EFI can be used for SMP tests, in
particular the SVM INIT-SIPI tests which send APs back through the boot
sequence while x2APIC is enabled.

Alternatively, disabling x2APIC and updating the APIC ops could be split,
but there's no obvious advantage in doing so. Retrieving the pre-boot
APIC ID isn't a hot path, i.e. the cost of the RDMSR is likely negligible,
and letting callers force xAPIC without updating the ops isn't any less
fragile.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20220725201336.2158604-2-seanjc@google.com

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x86: apic: Make xAPIC and I/O APIC pointers static

Make the pointers to the xAPIC and I/O APIC static as there are no users
outside of apic.c. Opportunistically use #defines for the default values

x86: apic: Make xAPIC and I/O APIC pointers static

Make the pointers to the xAPIC and I/O APIC static as there are no users
outside of apic.c. Opportunistically use #defines for the default values
instead of open coding magic numbers.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-9-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: apic: Track APIC ops on a per-cpu basis

Track the virtual function table to handle xAPIC vs. x2APIC on a per-cpu
basis. Using a common global is racy as nothing in KUT synchronizes
CPUs when s

x86: apic: Track APIC ops on a per-cpu basis

Track the virtual function table to handle xAPIC vs. x2APIC on a per-cpu
basis. Using a common global is racy as nothing in KUT synchronizes
CPUs when switching to/from x2APIC.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-8-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: apic: Replace spaces with tabs

Replace spaces with tabs in apic.c. No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-7-

x86: apic: Replace spaces with tabs

Replace spaces with tabs in apic.c. No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-7-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Always use legacy xAPIC to get APIC ID during TSS setup

Force use of xAPIC to retrieve the APIC ID during TSS setup to fix an
issue where an AP can switch apic_ops to point at x2apic_ops before

x86: Always use legacy xAPIC to get APIC ID during TSS setup

Force use of xAPIC to retrieve the APIC ID during TSS setup to fix an
issue where an AP can switch apic_ops to point at x2apic_ops before
setup_tss() completes, leading to a #GP and triple fault due to trying
to read an x2APIC MSR without x2APIC being enabled.

A future patch will make apic_ops a per-cpu pointer, but that's not of
any help for 32-bit, which uses the APIC ID to determine the GS selector,
i.e. 32-bit KUT has a chicken-and-egg problem. All setup_tss() callers
ensure the local APIC is in xAPIC mode, so just force use of xAPIC in
this case.

Fixes: 7e33895 ("x86: Move 32-bit GDT and TSS to desc.c")
Fixes: dbd3800 ("x86: Move 64-bit GDT and TSS to desc.c")
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220121231852.1439917-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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fix a out of bounds access in init_apic_map

refer to x86/cstart64.S:online_cpus:.fill (max_cpus + 7) / 8, 1, 0
The index is out of bounds when i is in the range 248...254.

Signed-off-by: Xinpeng Li

fix a out of bounds access in init_apic_map

refer to x86/cstart64.S:online_cpus:.fill (max_cpus + 7) / 8, 1, 0
The index is out of bounds when i is in the range 248...254.

Signed-off-by: Xinpeng Liu <liuxp11@chinatelecom.cn>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <1608642049-21007-1-git-send-email-liuxp11@chinatelecom.cn>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Fix out of bounds access when processing online_cpus

online_cpus is misdeclared as a 64 *byte* variable instead of a 64 *bit*
variable. This causes init_apic_map() to test random bytes when it

x86: Fix out of bounds access when processing online_cpus

online_cpus is misdeclared as a 64 *byte* variable instead of a 64 *bit*
variable. This causes init_apic_map() to test random bytes when it
iterates over online_cpus, which in turn can cause it to overflow id_map
and corrupt rnadom memory, e.g. pg_base. Declare online_cpus using
MAX_TEST_CPUS, which presumably is set explicitly to match the storage
size of online_cpus (64-bit values == max of 64 CPUS).

Reported-by: Evgeny Yakovlev <wrfsh@yandex-team.ru>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Memory barrier before setting ICR

The wrmsr that is used in x2apic ICR programming does not behave as a
memory barrier. There is a hidden assumption that it is. Add an explicit
memory barrier f

x86: Memory barrier before setting ICR

The wrmsr that is used in x2apic ICR programming does not behave as a
memory barrier. There is a hidden assumption that it is. Add an explicit
memory barrier for this reason.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Reset lapic after boot

Do not assume that the local APIC is in a xAPIC mode after reset.
Instead reset it first, since it might be in x2APIC mode, from which a
transition in xAPIC is invalid.

x86: Reset lapic after boot

Do not assume that the local APIC is in a xAPIC mode after reset.
Instead reset it first, since it might be in x2APIC mode, from which a
transition in xAPIC is invalid.

To use reset_apic(), change it to use xapic_write(), in order to make safe to use
while apic_ops might change concurrently by x2apic_enable().

Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: APIC IDs might not be consecutive

APIC IDs do not have to be consecutive. Crease a map between logical CPU
identifiers and the physical APIC IDs for this matter and add a level of
indirection.

x86: APIC IDs might not be consecutive

APIC IDs do not have to be consecutive. Crease a map between logical CPU
identifiers and the physical APIC IDs for this matter and add a level of
indirection.

During boot, save in a bitmap the APIC IDs of the enabled CPU and use it
later when sending IPIs.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Set "APIC Software Enable" after APIC reset

After the APIC is reset, some of its registers might be reset. As the
SDM says: "When IA32_APIC_BASE[11] is set to 0, prior initialization to
the API

x86: Set "APIC Software Enable" after APIC reset

After the APIC is reset, some of its registers might be reset. As the
SDM says: "When IA32_APIC_BASE[11] is set to 0, prior initialization to
the APIC may be lost and the APIC may return to the state described in
Section 10.4.7.1". The SDM also says that after APIC reset "the
spurious-interrupt vector register is initialized to 000000FFH". This
means that after the APIC is reset it needs to be software-enabled
through the SPIV.

This is done one occasion, but there are other occasions that do not
software-enable the APIC after reset (e.g., __test_apic_id() and main()
in vmx.c). Reenable software-enable APIC in these cases.

Cc: Sean Christopherson <sean.j.christopherson@intel.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Enhance test of disabled APIC

The test now checks to see that the memory "behind" the APIC has
either bus error semantics (writes ignored, reads return all 1s) or
memory semantics, and that this mem

Enhance test of disabled APIC

The test now checks to see that the memory "behind" the APIC has
either bus error semantics (writes ignored, reads return all 1s) or
memory semantics, and that this memory is exposed when the APIC is
either disabled or in x2APIC mode. The test also checks to see that
scribbling on the memory "behind" the APIC has no effect on CR8 when
MMIO access to the APIC is disabled.

Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: lib: Rename set_ioapic_redir() to ioapic_set_redir()

This is consistent with the naming scheme of rest of ioapic utils.

Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sad

x86: lib: Rename set_ioapic_redir() to ioapic_set_redir()

This is consistent with the naming scheme of rest of ioapic utils.

Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-4-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: lib: Expose IOAPIC/APIC globals and utils to lib

Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhuk

x86: lib: Expose IOAPIC/APIC globals and utils to lib

Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-Id: <1521674594-12085-3-git-send-email-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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lib/x86/apic: fix 32-bit compilation

Use the proper name, as the improper one isn't defined... Also
cleanup some trailing spaces.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Andrew Jones

lib/x86/apic: fix 32-bit compilation

Use the proper name, as the improper one isn't defined... Also
cleanup some trailing spaces.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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vmexit: add self-ipi speed tests

These are designed to test APICv and optimizations of KVM_REQ_EVENT.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: apic: APIC ID tests

KVM commit 49bd29ba1dbd ("KVM: x86: reset APIC ID when enabling LAPIC",
2016-07-12) fixed xAPIC ID value after reset.

QEMU commit 5232d00a041c ("target-i386: Implement CPUI

x86: apic: APIC ID tests

KVM commit 49bd29ba1dbd ("KVM: x86: reset APIC ID when enabling LAPIC",
2016-07-12) fixed xAPIC ID value after reset.

QEMU commit 5232d00a041c ("target-i386: Implement CPUID[0xB] (Extended
Topology Enumeration)", 2016-05-12) added initial x2APIC to CPUID.

KVM commit a92e2543d6a8 ("KVM: x86: use hardware-compatible format
for APIC ID register", 2016-07-12) changed internal format of APIC ID
register, so make sure that guest-visible APIC ID was not been affected.

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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ioapic: test TMR behavior

Test that TMR works right even if the virtual-APIC page is modified
by another processor. Either x2apic or xapic accesses are tested,
depending on whether x2apic is availa

ioapic: test TMR behavior

Test that TMR works right even if the virtual-APIC page is modified
by another processor. Either x2apic or xapic accesses are tested,
depending on whether x2apic is available.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: Split APIC tests into IOAPIC/APIC tests

Split apart the APIC tests into constituent parts (IOAPIC and APIC tests).

Signed-off-by: Steve Rutherford <srutherford@google.com>
Message-Id: <1431482

x86: Split APIC tests into IOAPIC/APIC tests

Split apart the APIC tests into constituent parts (IOAPIC and APIC tests).

Signed-off-by: Steve Rutherford <srutherford@google.com>
Message-Id: <1431482143-28018-1-git-send-email-srutherford@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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lib/x86: fix apic_id() under x2APIC

We used MMIO (xAPIC) for x2APIC. This is the same as using xAPIC in
globally disabled mode, and APICv enforces this by returning 0 on APIC
MMIO reads under x2API

lib/x86: fix apic_id() under x2APIC

We used MMIO (xAPIC) for x2APIC. This is the same as using xAPIC in
globally disabled mode, and APICv enforces this by returning 0 on APIC
MMIO reads under x2APIC.

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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lib/x86/apic: Consolidate over MSR_IA32_APICBASE

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>