powerpc: add usermode support

The biggest difficulty for user mode is MMU support. Otherwise it is
a simple matter of setting and clearing MSR[PR] with rfid and sc
respectively.

Some common harness

powerpc: add usermode support

The biggest difficulty for user mode is MMU support. Otherwise it is
a simple matter of setting and clearing MSR[PR] with rfid and sc
respectively.

Some common harness operations will fail in usermode, so some workarounds
are reqiured (e.g., puts() can't be used directly).

A usermode privileged instruction interrupt test is added.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-8-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc: Add MMU support

Add support for radix MMU, 4kB and 64kB pages.

This also adds MMU interrupt test cases, and runs the interrupts
test entirely with MMU enabled if it is available (aside fro

powerpc: Add MMU support

Add support for radix MMU, 4kB and 64kB pages.

This also adds MMU interrupt test cases, and runs the interrupts
test entirely with MMU enabled if it is available (aside from
machine check tests).

Acked-by: Andrew Jones <andrew.jones@linux.dev> (configure changes)
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-5-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc: Add timebase tests

This has a known failure on QEMU TCG machines where the decrementer
interrupt is not lowered when the DEC wraps from -ve to +ve.

Signed-off-by: Nicholas Piggin <npiggin@

powerpc: Add timebase tests

This has a known failure on QEMU TCG machines where the decrementer
interrupt is not lowered when the DEC wraps from -ve to +ve.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240612052322.218726-4-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc: add SMP and IPI support

powerpc SMP support is very primitive and does not set up a first-class
runtime environment for secondary CPUs.

This reworks SMP support, and provides a complete C

powerpc: add SMP and IPI support

powerpc SMP support is very primitive and does not set up a first-class
runtime environment for secondary CPUs.

This reworks SMP support, and provides a complete C and harness
environment for the secondaries, including interrupt handling, as well
as IPI support.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-17-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc: general interrupt tests

Add basic testing of various kinds of interrupts, machine check,
page fault, illegal, decrementer, trace, syscall, etc.

This has a known failure on QEMU TCG pseries

powerpc: general interrupt tests

Add basic testing of various kinds of interrupts, machine check,
page fault, illegal, decrementer, trace, syscall, etc.

This has a known failure on QEMU TCG pseries machines where MSR[ME]
can be incorrectly set to 0.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-13-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc: Support powernv machine with QEMU TCG

Add support for QEMU's powernv machine. This uses standard firmware
(skiboot) rather than a minimal firmware shim.

Reviewed-by: Cédric Le Goater <clg@

powerpc: Support powernv machine with QEMU TCG

Add support for QEMU's powernv machine. This uses standard firmware
(skiboot) rather than a minimal firmware shim.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-10-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc/sprs: Avoid taking PMU interrupts caused by register fuzzing

Storing certain values in MMCR0 can cause PMU interrupts when msleep
enables MSR[EE], and this crashes the test. Freeze the PMU c

powerpc/sprs: Avoid taking PMU interrupts caused by register fuzzing

Storing certain values in MMCR0 can cause PMU interrupts when msleep
enables MSR[EE], and this crashes the test. Freeze the PMU counters
and clear any PMU exception before calling msleep.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-7-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc/sprs: Specify SPRs with data rather than code

A significant rework that builds an array of 'struct spr', where each
element describes an SPR. This makes various metadata about the SPR
like n

powerpc/sprs: Specify SPRs with data rather than code

A significant rework that builds an array of 'struct spr', where each
element describes an SPR. This makes various metadata about the SPR
like name and access type easier to carry and use.

Hypervisor privileged registers are described despite not being used
at the moment for completeness, but also the code might one day be
reused for a hypervisor-privileged test.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240504122841.1177683-6-npiggin@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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powerpc: Cleanup SPR and MSR definitions

Move SPR and MSR defines out of ppc_asm.h and processor.h and into a
new include, asm/reg.h.

Add a define for the PVR SPR and various processor versions, an

powerpc: Cleanup SPR and MSR definitions

Move SPR and MSR defines out of ppc_asm.h and processor.h and into a
new include, asm/reg.h.

Add a define for the PVR SPR and various processor versions, and replace
the open coded numbers in the sprs.c test case.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20240226101218.1472843-6-npiggin@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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