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/kvm-unit-tests/lib/x86/
H A Dsetjmp64.S5 mov %rsp, 0x8(%rdi)
6 mov %rbp, 0x10(%rdi)
7 mov %rbx, 0x18(%rdi)
8 mov %r12, 0x20(%rdi)
9 mov %r13, 0x28(%rdi)
10 mov %r14, 0x30(%rdi)
11 mov %r15, 0x38(%rdi)
18 mov 0x38(%rdi), %r15
19 mov 0x30(%rdi), %r14
20 mov 0x28(%rdi), %r13
[all …]
H A Ddesc.h6 * 0x00 NULL descriptor NULL descriptor
7 * 0x08 ring-0 code segment (32-bit) ring-0 code segment (64-bit)
8 * 0x10 ring-0 data segment (32-bit) ring-0 data segment (32/64-bit)
9 * 0x18 ring-0 code segment (P=0) ring-0 code segment (64-bit, P=0)
10 * 0x20 intr_alt_stack TSS ring-0 code segment (32-bit)
11 * 0x28 ring-0 code segment (16-bit) same
12 * 0x30 ring-0 data segment (16-bit) same
13 * 0x38 (0x3b) ring-3 code segment (32-bit) same
14 * 0x40 (0x43) ring-3 data segment (32-bit) ring-3 data segment (32/64-bit)
15 * 0x48 (0x4b) **unused** ring-3 code segment (64-bit)
[all …]
H A Dio.c12 static int serial_iobase = 0x3f8;
13 static int serial_inited = 0;
20 lsr = inb(serial_iobase + 0x05); in serial_outb()
21 } while (!(lsr & 0x20)); in serial_outb()
23 outb(ch, serial_iobase + 0x00); in serial_outb()
39 lcr = inb(serial_iobase + 0x03); in serial_init()
40 lcr |= 0x80; in serial_init()
41 outb(lcr, serial_iobase + 0x03); in serial_init()
44 outb(0x01, serial_iobase + 0x00); in serial_init()
45 outb(0x00, serial_iobase + 0x01); in serial_init()
[all …]
H A Dusermode.c14 #define USERMODE_STACK_SIZE 0x2000
15 #define RET_TO_KERNEL_IRQ 0x20
39 volatile uint64_t rax = 0; in run_in_user()
43 *raised_vector = 0; in run_in_user()
48 if (setjmp(jmpbuf) != 0) { in run_in_user()
51 return 0; in run_in_user()
109 [rsp0]"=m"(tss[0].rsp0) in run_in_user()
H A Dapic-defs.h10 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
17 #define APIC_ID 0x20
19 #define APIC_LVR 0x30
20 #define APIC_LVR_MASK 0xFF00FF
21 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
22 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
24 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
28 #define APIC_XAPIC(x) ((x) >= 0x14)
29 #define APIC_TASKPRI 0x80
[all …]
H A Dintel-iommu.h26 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
33 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
34 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
35 #define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
36 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
37 #define DMAR_ECAP_REG_HI 0X14
38 #define DMAR_GCMD_REG 0x18 /* Global command */
39 #define DMAR_GSTS_REG 0x1c /* Global status */
40 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
41 #define DMAR_RTADDR_REG_HI 0X24
[all …]
H A Dsmp.c15 #define IPI_VECTOR 0x20
50 apic_write(APIC_EOI, 0); in ipi()
56 apic_write(APIC_EOI, 0); in ipi()
107 ipi_done = 0; in __on_cpu()
125 __on_cpu(cpu, function, data, 0); in on_cpu_async()
132 for (cpu = cpu_count() - 1; cpu >= 0; --cpu) in on_cpus()
151 set_idt_entry(IPI_VECTOR, ipi_entry, 0); in smp_init()
153 setup_smp_id(0); in smp_init()
155 on_cpu(i, setup_smp_id, 0); in smp_init()
171 on_cpu(i, do_reset_apic, 0); in smp_reset_apic()
[all …]
/kvm-unit-tests/s390x/
H A Dsthyi.h16 CODE_UNSUPP = 0x04, /* with cc = 3 */
17 CODE_SUCCES = 0x00, /* with cc = 0 */
21 HDR_PERF_UNAV = 0x80,
22 HDR_STSI_UNAV = 0x40,
23 HDR_STACK_INCM = 0x20,
24 HDR_NOT_LPAR = 0x10,
28 MACH_CNT_VLD = 0x80,
29 MACH_ID_VLD = 0x40,
30 MACH_NAME_VLD = 0x20,
34 PART_MT_EN = 0x80,
[all …]
H A Dskey.c26 void *addr = (void *)0x10000 - 2 * PAGE_SIZE; in test_set_mb()
27 void *end = (void *)0x10000; in test_set_mb()
33 skey.val = 0x30; in test_set_mb()
46 skey1.val = 0x30; in test_chg()
47 set_storage_key(pagebuf, skey1.val, 0); in test_chg()
49 pagebuf[0] = 3; in test_chg()
58 skey.val = 0x30; in test_set()
60 set_storage_key(pagebuf, skey.val, 0); in test_set()
75 memset(pagebuf, 0, PAGE_SIZE * 2); in test_priv()
80 set_storage_key(pagebuf, 0x30, 0); in test_priv()
[all …]
H A Dvector.c22 " vlm 0, 15, %[a]\n" in vlm_all()
43 " vl 0, %[v1]\n" in test_add()
45 " va 2, 0, 1, 4\n" in test_add()
66 memset(&prm, 0xff, sizeof(prm)); in test_ext1_nand()
69 " vl 0, %[v1]\n" in test_ext1_nand()
71 " .byte 0xe7, 0x20, 0x10, 0x00, 0x00, 0x6e\n" /* vnn */ in test_ext1_nand()
92 prm.c = 0; in test_bcd_add()
93 prm.a = prm.b = 0b001000011100; in test_bcd_add()
96 " vl 0, %[v1]\n" in test_bcd_add()
98 " .byte 0xe6, 0x20, 0x10, 0x01, 0x00, 0x71\n" /* vap */ in test_bcd_add()
[all …]
H A Duv-host.c92 { NULL, 0, 0 },
101 unsigned long r1 = 0; in test_i3()
107 "0: .insn rrf,0xB9A40000,%[r1],%[r2],4,2\n" in test_i3()
124 for (i = 0; cmds[i].name; i++) { in test_priv()
129 uv_call_once(0, (uint64_t)&uvcb); in test_priv()
143 for (i = 0; cmds[i].name; i++) { in test_uv_uninitialized()
149 uv_call_once(0, (uint64_t)&uvcb); in test_uv_uninitialized()
178 for (i = 0; cmds[i].name; i++) { in test_access()
181 uv_call_once(0, (uint64_t)uvcb); in test_access()
193 for (i = 0; cmds[i].name; i++) { in test_access()
[all …]
/kvm-unit-tests/lib/s390x/asm/
H A Dsie-arch.h8 #define CPUSTAT_STOPPED 0x80000000
9 #define CPUSTAT_WAIT 0x10000000
10 #define CPUSTAT_ECALL_PEND 0x08000000
11 #define CPUSTAT_STOP_INT 0x04000000
12 #define CPUSTAT_IO_INT 0x02000000
13 #define CPUSTAT_EXT_INT 0x01000000
14 #define CPUSTAT_RUNNING 0x00800000
15 #define CPUSTAT_RETAINED 0x00400000
16 #define CPUSTAT_TIMING_SUB 0x00020000
17 #define CPUSTAT_SIE_SUB 0x00010000
[all …]
/kvm-unit-tests/lib/arm64/asm/
H A Desr.h16 #define ESR_EL1_EC_UNKNOWN (0x00)
17 #define ESR_EL1_EC_WFI (0x01)
18 #define ESR_EL1_EC_CP15_32 (0x03)
19 #define ESR_EL1_EC_CP15_64 (0x04)
20 #define ESR_EL1_EC_CP14_MR (0x05)
21 #define ESR_EL1_EC_CP14_LS (0x06)
22 #define ESR_EL1_EC_FP_ASIMD (0x07)
23 #define ESR_EL1_EC_CP10_ID (0x08)
24 #define ESR_EL1_EC_CP14_64 (0x0C)
25 #define ESR_EL1_EC_ILL_ISS (0x0E)
[all …]
/kvm-unit-tests/lib/powerpc/
H A Dprocessor.c25 * Exception handlers span from 0x100 to 0x1000 and can have a granularity
26 * of 0x20 bytes in some cases. Indexing spans 0-0x1000 with 0x20 increments
32 assert(!(trap & ~0xfe0)); in handle_exception()
54 * We run with AIL=0, so interrupts taken with MMU disabled. in do_handle_exception()
70 printf("Unhandled CPU%d exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", in do_handle_exception()
106 * interesting. stop with ESL=0 should be simple enough, ESL=1 in sleep_tb()
120 if (left > 0x7fffffff) in sleep_tb()
121 left = 0x7fffffff; in sleep_tb()
123 /* DEC won't fire until H_CEDE is called because EE=0 */ in sleep_tb()
124 asm volatile ("mtdec %0" : : "r" (left)); in sleep_tb()
[all …]
/kvm-unit-tests/x86/
H A Dcstart.S7 ipi_vector = 0x20
21 i = 0
23 .long 0x1e7 | (i << 22)
31 mb_magic = 0x1BADB002
32 mb_flags = 0x0
35 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
49 mov $0x10, %ax
81 bts $0, %eax
H A Dumip.c46 gp_count = 0; in do_smsw()
52 gp_count = 0; in do_sldt()
58 gp_count = 0; in do_str()
65 gp_count = 0; in do_sgdt()
72 gp_count = 0; in do_sidt()
78 gp_count = 0; in do_movcr()
87 report(gp_count == 0, "no exception from smsw"); in test_umip_nogp()
89 report(gp_count == 0, "no exception from sgdt"); in test_umip_nogp()
91 report(gp_count == 0, "no exception from sidt"); in test_umip_nogp()
93 report(gp_count == 0, "no exception from sldt"); in test_umip_nogp()
[all …]
H A Ds3.c8 #define RTC_ALARM_DONT_CARE 0xC0
14 #define REG_A_UIP 0x80
15 #define REG_B_AIE 0x20
19 outb(reg, 0x70); in rtc_in()
20 return inb(0x71); in rtc_in()
25 outb(reg, 0x70); in rtc_out()
26 outb(val, 0x71); in rtc_out()
35 char *addr, *resume_vec = (void*)0x1000; in main()
47 outw(0x400, fadt->pm1a_evt_blk + 2); in main()
50 while ((rtc_in(RTC_REG_A) & REG_A_UIP) == 0); in main()
[all …]
H A Dcstart64.S5 ipi_vector = 0x20
19 i = 0
21 .quad 0x1e7 | (i << 21)
27 .quad ptl2 + 7 + 0 * 4096
42 mb_boot_info: .quad 0
51 mb_magic = 0x1BADB002
52 mb_flags = 0x0
55 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
101 .quad 0
102 .quad 0x00cf9b000000ffff // flat 32-bit code segment
[all …]
H A Dpku.c12 volatile int pf_count = 0;
31 write_pkru(0); in do_pf_tss()
55 pf_count = 0; in init_test()
59 write_pkru(0); in init_test()
60 set_cr0_wp(0); in init_test()
66 unsigned int pkey = 0x2; in main()
67 unsigned int pkru_ad = 0x10; in main()
68 unsigned int pkru_wd = 0x20; in main()
81 for (i = 0; i < USER_BASE; i += PAGE_SIZE) { in main()
100 report(pf_count == 0 && test == 21, in main()
[all …]
H A Dpks.c12 volatile int pf_count = 0;
29 printf("#PF handler, error code: 0x%lx\n", error_code); in do_pf_tss()
32 wrmsr(MSR_IA32_PKRS, 0); in do_pf_tss()
56 pf_count = 0; in init_test()
60 wrmsr(MSR_IA32_PKRS, 0); in init_test()
61 set_cr0_wp(0); in init_test()
67 unsigned int pkey = 0x2; in main()
68 unsigned int pkrs_ad = 0x10; in main()
69 unsigned int pkrs_wd = 0x20; in main()
83 for (i = 0; i < SUPER_BASE; i += PAGE_SIZE) { in main()
[all …]
/kvm-unit-tests/lib/
H A Dpci-edu.h21 #define PCI_VENDOR_ID_QEMU 0x1234
22 #define PCI_DEVICE_ID_EDU 0x11e8
25 #define EDU_BAR 0
26 #define EDU_MAGIC 0xed
27 #define EDU_VERSION 0x100
31 #define EDU_REG_ID 0x0
32 #define EDU_REG_ALIVE 0x4
33 #define EDU_REG_FACTORIAL 0x8
34 #define EDU_REG_STATUS 0x20
35 #define EDU_REG_INTR_STATUS 0x24
[all …]
/kvm-unit-tests/lib/linux/
H A Dpci_regs.h30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
33 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
34 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
35 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
36 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
37 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
38 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
39 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
/kvm-unit-tests/riscv/
H A Dcstart.S27 REG_S zero, 0(\tmp1)
49 .dword 0x200000 // text offset
51 .dword 0 // flags
52 .word (0 << 16 | 2 << 0) // version
53 .word 0 // res1
54 .dword 0 // res2
55 .ascii "RISCV\0\0\0" // magic
57 .word 0 // res3
82 REG_S a5, 0(a4) // *addr = val
110 lw a0, 0(a0)
[all …]
/kvm-unit-tests/lib/riscv/
H A Dio.c18 #define UART_LSR_THRE 0x20
66 assert(ret >= 0 || ret == -FDT_ERR_NOTFOUND); in uart0_init_fdt()
69 for (i = 0; i < ARRAY_SIZE(compatible); i++) { in uart0_init_fdt()
71 assert(ret == 0 || ret == -FDT_ERR_NOTFOUND); in uart0_init_fdt()
72 if (ret == 0) in uart0_init_fdt()
93 ret = dt_pbus_translate_node(ret, 0, &base); in uart0_init_fdt()
94 assert(ret == 0); in uart0_init_fdt()
127 sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, strlen(s), lo, hi, 0, 0, 0); in puts()
137 uart0_write(0, *s++); in puts()
/kvm-unit-tests/arm/
H A Dcstart64.S155 \instr #0
160 stp x0, x1, [x10, #0]
235 * n = AttrIndx[2:0]
272 ldr x1, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
273 MAIR(0x04, MT_DEVICE_nGnRE) | \
274 MAIR(0x0c, MT_DEVICE_GRE) | \
275 MAIR(0x44, MT_NORMAL_NC) | \
276 MAIR(0xff, MT_NORMAL) | \
277 MAIR(0xbb, MT_NORMAL_WT) | \
278 MAIR(0x08, MT_DEVICE_nGRE) | \
[all …]

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