#
dca3f4c0 |
| 24-Feb-2025 |
Paolo Bonzini <pbonzini@redhat.com> |
Merge tag 'kvm-x86-2025.02.21' of https://github.com/kvm-x86/kvm-unit-tests into HEAD
KVM-Unit-Tests x86 changes:
- Expand the per-CPU data+stack area to 12KiB per CPU to reduce the probability
Merge tag 'kvm-x86-2025.02.21' of https://github.com/kvm-x86/kvm-unit-tests into HEAD
KVM-Unit-Tests x86 changes:
- Expand the per-CPU data+stack area to 12KiB per CPU to reduce the probability of tests overflowing their stack and clobbering pre-CPU data.
- Add testcases for LA57 canonical checks.
- Add testcases for LAM.
- Add a smoke test to make sure KVM doesn't bleed split-lock #AC/#DB into the guest.
- Fix many warts and bugs in the PMU test, and prepare it for PMU version 5 and beyond.
- Many misc fixes and cleanups.
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#
d467e659 |
| 21-Feb-2025 |
Sean Christopherson <seanjc@google.com> |
x86: Move SMP #defines from apic-defs.h to smp.h
Now that the __ASSEMBLY__ versus __ASSEMBLER_ mess is sorted out, move the SMP related #defines from apic-defs.h to smp.h, and drop the comment that
x86: Move SMP #defines from apic-defs.h to smp.h
Now that the __ASSEMBLY__ versus __ASSEMBLER_ mess is sorted out, move the SMP related #defines from apic-defs.h to smp.h, and drop the comment that explains the hackery.
Opportunistically make REALMODE_GDT_LOWMEM visible to assembly code as well, and drop efistart64.S's local copy.
Link: https://lore.kernel.org/r/20250221233832.2251456-1-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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c8a8a358 |
| 21-Feb-2025 |
Hang SU <darcysail@gmail.com> |
x86: replace segment selector magic number with macro definition
Add assembly check in desc.h, to replace segment selector magic number with macro definition.
Signed-off-by: Hang SU <darcy.sh@antgr
x86: replace segment selector magic number with macro definition
Add assembly check in desc.h, to replace segment selector magic number with macro definition.
Signed-off-by: Hang SU <darcy.sh@antgroup.com> Link: https://lore.kernel.org/r/20250221225406.2228938-4-seanjc@google.com [sean: fix KERNEL_CS vs. KERNEL_CS32 goof] Signed-off-by: Sean Christopherson <seanjc@google.com>
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2821b32d |
| 15-Feb-2025 |
Sean Christopherson <seanjc@google.com> |
x86: Add a macro for the size of the per-CPU stack/data area
Add a macro to define the size of the per-CPU stack/data area so that it's somewhat possible to make sense of the madness.
Link: https:/
x86: Add a macro for the size of the per-CPU stack/data area
Add a macro to define the size of the per-CPU stack/data area so that it's somewhat possible to make sense of the madness.
Link: https://lore.kernel.org/r/20250215012032.1206409-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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a95dd6be |
| 15-Feb-2025 |
Sean Christopherson <seanjc@google.com> |
x86: Make per-CPU stacks page-aligned
Align the per-CPU stacks, and by extension, the per-CPU data area to page boundaries so that when things go sideways, it's at least somewhat obvious that a test
x86: Make per-CPU stacks page-aligned
Align the per-CPU stacks, and by extension, the per-CPU data area to page boundaries so that when things go sideways, it's at least somewhat obvious that a test overran its stack. E.g. as is, stacks often start at the *bottom* of a page, and so it looks like they're always broken because they immediately split a page.
Link: https://lore.kernel.org/r/20250215012032.1206409-2-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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d6d3a3bd |
| 02-Nov-2022 |
Sean Christopherson <seanjc@google.com> |
x86: Add a helper for the BSP's final init sequence common to all flavors
Add bsp_rest_init() to dedup bringing up APs and doing SMP initialization across 32-bit, 64-bit, and EFI flavors of KVM-unit
x86: Add a helper for the BSP's final init sequence common to all flavors
Add bsp_rest_init() to dedup bringing up APs and doing SMP initialization across 32-bit, 64-bit, and EFI flavors of KVM-unit-tests. The common bucket will also be used in future to patches to init things that aren't SMP related and thus don't fit in smp_init(), e.g. PMU setup.
No functional change intended.
Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20221102225110.3023543-15-seanjc@google.com
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#
14b54ed7 |
| 26-Jul-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
Merge tag 'for_paolo' of https://github.com/sean-jc/kvm-unit-tests into HEAD
x86 fixes, cleanups, and new sub-tests:
- Bug fix for the VMX-preemption timer expiration test - Refactor SVM tests
Merge tag 'for_paolo' of https://github.com/sean-jc/kvm-unit-tests into HEAD
x86 fixes, cleanups, and new sub-tests:
- Bug fix for the VMX-preemption timer expiration test - Refactor SVM tests to split out NPT tests - Add tests for MCE banks to MSR test - Add SMP Support for x86 UEFI tests - x86: nVMX: Add VMXON #UD test (and exception cleanup) - PMU cleanup and related nVMX bug fixes
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#
0afd4dd0 |
| 15-Jun-2022 |
Sean Christopherson <seanjc@google.com> |
x86: Rename ap_init() to bringup_aps()
Rename the helper that wakes and waits for APs to bringup_aps(), ap_init() is terribly confusing because it's called from the BSP, not APs.
Signed-off-by: Sea
x86: Rename ap_init() to bringup_aps()
Rename the helper that wakes and waits for APs to bringup_aps(), ap_init() is terribly confusing because it's called from the BSP, not APs.
Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220615232943.1465490-13-seanjc@google.com
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#
0b7501c3 |
| 15-Jun-2022 |
Varad Gautam <varad.gautam@suse.com> |
x86: Provide a common 64-bit AP entrypoint for EFI and non-EFI
ap_start64() currently serves as the 64-bit entrypoint for non-EFI tests.
Having ap_start64() and save_id() written in asm prevents sh
x86: Provide a common 64-bit AP entrypoint for EFI and non-EFI
ap_start64() currently serves as the 64-bit entrypoint for non-EFI tests.
Having ap_start64() and save_id() written in asm prevents sharing these routines between EFI and non-EFI tests.
Rewrite them in C and use ap_start64 as the 64-bit entrypoint in the EFI boot flow.
With this, EFI tests support -smp > 1. smptest.efi now passes.
Cc: Andrew Jones <drjones@redhat.com> Cc: Marc Orr <marcorr@google.com> Cc: Zixuan Wang <zxwang42@gmail.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: David Rientjes <rientjes@google.com> Cc: Thomas.Lendacky@amd.com Cc: Joerg Roedel <jroedel@suse.de> Cc: Borislav Petkov <bp@alien8.de> Signed-off-by: Varad Gautam <varad.gautam@suse.com> [sean: reset APIC before TSS setup, halt in AP wait loop, add comment] Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220615232943.1465490-12-seanjc@google.com
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#
2187b97c |
| 15-Jun-2022 |
Varad Gautam <varad.gautam@suse.com> |
x86: Move 32-bit => 64-bit transition code to trampolines.S
Move the code for transitioning from unpaged 32-bit mode to paged 64-bit mode to trampoline.S, it can be shared across EFI and non-EFI bui
x86: Move 32-bit => 64-bit transition code to trampolines.S
Move the code for transitioning from unpaged 32-bit mode to paged 64-bit mode to trampoline.S, it can be shared across EFI and non-EFI builds.
Leave 5-level paging behind for the time being, EFI doesn't yet support support disabling paging, which is required to get from 4-level to 5-level paging.
Signed-off-by: Varad Gautam <varad.gautam@suse.com> [sean: move to trampolines.S instead of start32.S, reword changelog] Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220615232943.1465490-10-seanjc@google.com
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#
e5bb8a11 |
| 25-Jul-2022 |
Sean Christopherson <seanjc@google.com> |
x86: cstart64: Put APIC into xAPIC after loading TSS
Now that pre_boot_apic_id() works with either xAPIC or x2APIC, "reset" the APIC after configuring loading the TSS. Previously, load_tss() => set
x86: cstart64: Put APIC into xAPIC after loading TSS
Now that pre_boot_apic_id() works with either xAPIC or x2APIC, "reset" the APIC after configuring loading the TSS. Previously, load_tss() => setup_tss() needed to run after forcing the vCPU into xAPIC mode due to pre_boot_apic_id() assuming xAPIC.
The order doesn't truly matter at this point, but loading the TSS first will allow sharing code with the EFI boot flow, which "needs" to load the TSS (more specifically, needs to configure GS.base) prior to forcing the vCPU into xAPIC (and thus setting the per-vCPU APIC ops).
Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220725201336.2158604-3-seanjc@google.com
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#
b397e5a5 |
| 15-Jun-2022 |
Varad Gautam <varad.gautam@suse.com> |
x86: Move load_idt() to desc.c
This allows sharing IDT setup code between EFI (-fPIC) and non-EFI builds.
Signed-off-by: Varad Gautam <varad.gautam@suse.com> Signed-off-by: Sean Christopherson <sea
x86: Move load_idt() to desc.c
This allows sharing IDT setup code between EFI (-fPIC) and non-EFI builds.
Signed-off-by: Varad Gautam <varad.gautam@suse.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220615232943.1465490-5-seanjc@google.com
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#
d36b378f |
| 15-Jun-2022 |
Varad Gautam <varad.gautam@suse.com> |
x86: Move ap_init() to smp.c
ap_init() copies the SIPI vector to lowmem, sends INIT/SIPI to APs and waits on the APs to come up.
Port this routine to C from asm and move it to smp.c to allow sharin
x86: Move ap_init() to smp.c
ap_init() copies the SIPI vector to lowmem, sends INIT/SIPI to APs and waits on the APs to come up.
Port this routine to C from asm and move it to smp.c to allow sharing this functionality between the EFI (-fPIC) and non-EFI builds.
Call ap_init() from the EFI setup path to reset the APs to a known location.
Signed-off-by: Varad Gautam <varad.gautam@suse.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220615232943.1465490-4-seanjc@google.com
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c8ab4c00 |
| 15-Jun-2022 |
Varad Gautam <varad.gautam@suse.com> |
x86: Share realmode trampoline between i386 and x86_64
i386 and x86_64 each maintain their own copy of the realmode trampoline (sipi_entry). Move the 16-bit SIPI vector and GDT to a new trampolines.
x86: Share realmode trampoline between i386 and x86_64
i386 and x86_64 each maintain their own copy of the realmode trampoline (sipi_entry). Move the 16-bit SIPI vector and GDT to a new trampolines.S to be shared by both. The common trampoline file will also be used to shared 32-bit to 64-bit trampoline code.
Signed-off-by: Varad Gautam <varad.gautam@suse.com> [sean: rename to trampolines.S to avoid naming conundrum] Signed-off-by: Sean Christopherson <seanjc@google.com> Link: https://lore.kernel.org/r/20220615232943.1465490-3-seanjc@google.com
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#
705c9e7e |
| 24-Jan-2022 |
Junming Liu <junming.liu@intel.com> |
x86: Align incw instruction to avoid split lock
A split lock is any atomic operation whose operand crosses two cache lines. Since the operand spans two cache lines and the operation must be atomic,
x86: Align incw instruction to avoid split lock
A split lock is any atomic operation whose operand crosses two cache lines. Since the operand spans two cache lines and the operation must be atomic, the system locks the bus while the CPU accesses the two cache lines. The bus lock operation is heavy weight and can cause severe performance degradation.
Here's the log when run x86 test cases: [ 3572.765921] x86/split lock detection: #AC: qemu-system-x86/24383 took a split_lock trap at address: 0x400306
Root caused 'cpu_online_count' spans two cache lines, "lock incw cpu_online_count" instruction causes split lock. 'cpu_online_count' is the type of word(two bytes) and therefore it needs to be aligned to 2 bytes to avoid split lock.
Signed-off-by: Junming Liu <junming.liu@intel.com> Message-Id: <20220124111444.12548-1-junming.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
f3e081d7 |
| 10-Nov-2021 |
Aaron Lewis <aaronlewis@google.com> |
x86: Look up the PTEs rather than assuming them
Rather than assuming which PTEs the SMEP test runs on, look them up to ensure they are correct. If this test were to run on a different page table (i
x86: Look up the PTEs rather than assuming them
Rather than assuming which PTEs the SMEP test runs on, look them up to ensure they are correct. If this test were to run on a different page table (ie: run in an L2 test) the wrong PTEs would be set. Switch to looking up the PTEs to avoid this from happening.
Signed-off-by: Aaron Lewis <aaronlewis@google.com> Message-Id: <20211110212001.3745914-11-aaronlewis@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
91abf0b9 |
| 10-Nov-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
Merge branch 'gdt-idt-cleanup' into master
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#
7e33895d |
| 21-Oct-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: Move 32-bit GDT and TSS to desc.c
Move the GDT and TSS data structures from x86/cstart.S to lib/x86/desc.c, for consistency with the 64-bit version.
Signed-off-by: Paolo Bonzini <pbonzini@redh
x86: Move 32-bit GDT and TSS to desc.c
Move the GDT and TSS data structures from x86/cstart.S to lib/x86/desc.c, for consistency with the 64-bit version.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
dbd38004 |
| 21-Oct-2021 |
Zixuan Wang <zixuanwang@google.com> |
x86: Move 64-bit GDT and TSS to desc.c
Move the GDT and TSS data structures from x86/cstart64.S to lib/x86/desc.c, so that the follow-up UEFI support commits can reuse these definitions, without re-
x86: Move 64-bit GDT and TSS to desc.c
Move the GDT and TSS data structures from x86/cstart64.S to lib/x86/desc.c, so that the follow-up UEFI support commits can reuse these definitions, without re-defining them in UEFI's boot up assembly code.
Signed-off-by: Zixuan Wang <zixuanwang@google.com> Message-Id: <20211004204931.1537823-2-zxwang42@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
8cd86535 |
| 21-Oct-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: get rid of ring0stacktop
The ring3 switch code relied on a special stack page that was used for the ring0 stack during the ring3 part of the test. This special stack page was used if an except
x86: get rid of ring0stacktop
The ring3 switch code relied on a special stack page that was used for the ring0 stack during the ring3 part of the test. This special stack page was used if an exception handler ran during the ring3 part of the test.
This method is quite complex; it is easier to just use the same stack for the "outer" part of the test and the exception handler. To do so, store esp/rsp in the TSS just before doing the PUSH/IRET sequence. On 64-bit, the TSS can also be used to restore rsp after coming back from ring3.
Unifying the three copies of the ring switching code is left as an exercise to the reader.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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5ed10141 |
| 21-Oct-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: unify name of 32-bit and 64-bit GDT
There's no need to distinguish gdt32 and gdt64, since the same C functions operate on both and selector numbers are mostly unified between 32- and 64-bit ver
x86: unify name of 32-bit and 64-bit GDT
There's no need to distinguish gdt32 and gdt64, since the same C functions operate on both and selector numbers are mostly unified between 32- and 64-bit versions.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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6b41b633 |
| 21-Oct-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
x86: Move IDT to desc.c
Move the IDT data structures from x86/cstart.S and x86/cstart64.S to lib/x86/desc.c, so that the follow-up UEFI support commits can reuse these definitions, without re-defini
x86: Move IDT to desc.c
Move the IDT data structures from x86/cstart.S and x86/cstart64.S to lib/x86/desc.c, so that the follow-up UEFI support commits can reuse these definitions, without re-defining them in UEFI's boot up assembly code.
Extracted by a patch by Zixuan Wang <zxwang42@gmail.com> and ported to 32-bit too.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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a7f32d87 |
| 20-Oct-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
replace tss_descr global with a function
tss_descr is declared as a struct descriptor_table_ptr but it is actualy pointing to an _entry_ in the GDT. Also it is different per CPU, but tss_descr does
replace tss_descr global with a function
tss_descr is declared as a struct descriptor_table_ptr but it is actualy pointing to an _entry_ in the GDT. Also it is different per CPU, but tss_descr does not recognize that. Fix both by reusing the code (already present e.g. in the vmware_backdoors test) that extracts the base from the GDT entry; and also provide a helper to retrieve the limit, which is needed in vmx.c.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
4770e9c8 |
| 17-Jul-2020 |
Cathy Avery <cavery@redhat.com> |
svm: INIT and STARTUP ipi test
Init the vcpu and issue the STARTUP ipi to indicate the vcpu should execute its startup routine.
Signed-off-by: Cathy Avery <cavery@redhat.com> Message-Id: <202007171
svm: INIT and STARTUP ipi test
Init the vcpu and issue the STARTUP ipi to indicate the vcpu should execute its startup routine.
Signed-off-by: Cathy Avery <cavery@redhat.com> Message-Id: <20200717113422.19575-3-cavery@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
2d331a4d |
| 01-Sep-2020 |
Roman Bolshakov <r.bolshakov@yadro.com> |
x86: Replace instruction prefixes with spaces
There are three kinds of x86 prefix delimiters in GNU binutils: '/', '\\' and a space.
The first works on Linux and few other platforms. The second on
x86: Replace instruction prefixes with spaces
There are three kinds of x86 prefix delimiters in GNU binutils: '/', '\\' and a space.
The first works on Linux and few other platforms. The second one is SVR-4 compatible and works on the generic elf target. The last kind is universal and works everywhere, it's also used in the GAS manual [1]. Space delimiters fix the build errors on x86_64-elf binutils:
x86/cstart64.S:217: Error: invalid character '/' in mnemonic x86/cstart64.S:313: Error: invalid character '/' in mnemonic
1. https://sourceware.org/binutils/docs/as/i386_002dPrefixes.html
Cc: Cameron Esfahani <dirty@apple.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200901085056.33391-3-r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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