Merge branch 'riscv/sbi' into 'master'

riscv: SBI SSE tests and baremetal boot support

See merge request kvm-unit-tests/kvm-unit-tests!75

riscv: Add Image header to flat binaries

This allows flat binaries to be understood by U-Boot's booti command and
its PXE boot flow.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
[Chang

riscv: Add Image header to flat binaries

This allows flat binaries to be understood by U-Boot's booti command and
its PXE boot flow.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
[Changed text offset to 0x200000]
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'riscv/queue' into 'master'

lib/on-cpus and riscv smp improvements

See merge request kvm-unit-tests/kvm-unit-tests!69

riscv: Rework smp_boot_secondary

Use HSM status to determine when a secondary should be started.
Also save the stack pointer so a secondary may be stopped and
started again without leaking old stack

riscv: Rework smp_boot_secondary

Use HSM status to determine when a secondary should be started.
Also save the stack pointer so a secondary may be stopped and
started again without leaking old stacks.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

riscv: Fix secondary_entry

The last few instructions of secondary_entry had the right concept,
but were the totally wrong implementation. Without setting ra, then,
when the boot function doesn't sta

riscv: Fix secondary_entry

The last few instructions of secondary_entry had the right concept,
but were the totally wrong implementation. Without setting ra, then,
when the boot function doesn't stay in an infinite loop, like
do_idle() would, we'd go off into the weeds when trying to return
from it. Make sure we set ra to come back to where we can then call
do_idle() instead. The bug was found by inspection since nobody is
calling smp_boot_secondary() with anything other than do_idle() at
this time.

Fixes: 9c92b28e6b7b ("riscv: Add SMP support")
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'riscv/sbi' into 'master'

riscv: Collect some patches supporting SBI tests

See merge request kvm-unit-tests/kvm-unit-tests!68

riscv: Rewrite hartid_to_cpu in assembly

Some SBI HSM tests run without a stack being setup so they can't
run C code. Those tests still need to know the corresponding cpuid
for the hartid on which t

riscv: Rewrite hartid_to_cpu in assembly

Some SBI HSM tests run without a stack being setup so they can't
run C code. Those tests still need to know the corresponding cpuid
for the hartid on which they are running. Give those tests
hartid_to_cpu() by reimplementing it in assembly.

Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'riscv/fixes' into 'master'

riscv: Fix argc

See merge request kvm-unit-tests/kvm-unit-tests!66

riscv: Fix argc

__argc is 32 bits so even rv64 should load it with lw, not just rv32.
This fixes odd behavior such as getting false when testing argc < 2
even though we know argc should be 1. argc <

riscv: Fix argc

__argc is 32 bits so even rv64 should load it with lw, not just rv32.
This fixes odd behavior such as getting false when testing argc < 2
even though we know argc should be 1. argc < 2 being false comes from
the register comparison using the full register width and the upper
32 bits being loaded with junk.

Fixes: bd744d465910 ("riscv: Initial port, hello world")
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'riscv/sbi' into 'master'

Mainly riscv stuff, but also limits.h and pseudo random numbers

See merge request kvm-unit-tests/kvm-unit-tests!65

riscv: move REG_L/REG_W in a dedicated asm.h file

These assembly macros will be used as part of the SSE entry assembly
code, export them in asm.h header.

Signed-off-by: Clément Léger <cleger@rivosi

riscv: move REG_L/REG_W in a dedicated asm.h file

These assembly macros will be used as part of the SSE entry assembly
code, export them in asm.h header.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'riscv/queue' into 'master'

riscv: Add EFI support and SBI base ext tests

See merge request kvm-unit-tests/kvm-unit-tests!54

riscv: Enable building for EFI

Mimicking arm64 support, add configure and makefile changes to build
for EFI. Since the linker script is replaced also replace the initial
cstart code (also done like

riscv: Enable building for EFI

Mimicking arm64 support, add configure and makefile changes to build
for EFI. Since the linker script is replaced also replace the initial
cstart code (also done like arm64). Finally, provide a stub for
setup_efi() in order to allow compiling to complete (even though
tests can't yet run).

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'riscv/initial-port-v3' into 'master'

riscv: Initial port

See merge request kvm-unit-tests/kvm-unit-tests!50

riscv: Add SMP support

Implement the same SMP API that Arm has but using an SBI HSM
call instead of PSCI. Unlike Arm, riscv needs to always set
cpu0_calls_idle, because the boot hart doesn't have to

riscv: Add SMP support

Implement the same SMP API that Arm has but using an SBI HSM
call instead of PSCI. Unlike Arm, riscv needs to always set
cpu0_calls_idle, because the boot hart doesn't have to be the
first hart described in the DT, which means cpu0 may well be
a secondary. As usual, add a couple tests to selftest.c to
make sure everything works.

(The secondary boot process is also improved over Arm's a bit
by keeping boot data percpu, dropping the need for a lock. We
could create percpu data for Arm too, but that's left as future
work.)

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

show more ...

riscv: Add backtrace support

Enable stack unwinding, even when going through an exception, by
implementing backtrace() and pushing a frame pointer on the stack
in exception_vectors.

Signed-off-by:

riscv: Add backtrace support

Enable stack unwinding, even when going through an exception, by
implementing backtrace() and pushing a frame pointer on the stack
in exception_vectors.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

show more ...

riscv: Add exception handling

Steal more code from Linux to implement exception handling, but with
the same kvm-unit-tests API that Arm has. Also introduce struct
thread_info like Arm has in order t

riscv: Add exception handling

Steal more code from Linux to implement exception handling, but with
the same kvm-unit-tests API that Arm has. Also introduce struct
thread_info like Arm has in order to hold the handler pointers.
Finally, as usual, extend the selftest to make sure it all works.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

show more ...

riscv: Add riscv32 support

Make a few tweaks to allow also building and running riscv32.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

riscv: Initial port, hello world

Add the minimal amount of code possible in order to launch a first
test, which just prints "Hello, world" using the expected UART
address of the QEMU virt machine. A

riscv: Initial port, hello world

Add the minimal amount of code possible in order to launch a first
test, which just prints "Hello, world" using the expected UART
address of the QEMU virt machine. Add files, stubs, and some support,
such as barriers and MMIO read/write along the way in order to
satisfy the compiler. Basically everything is either copied from
the arm64 port of kvm-unit-tests, or at least inspired by it, and,
in that case, the RISC-V Linux kernel code was copied.

Run with
qemu-system-riscv64 -nographic -M virt -kernel riscv/selftest.flat

and then go to the monitor (ctrl-a c) and use 'q' to quit, since
the unit test will just hang after printing hello world and the
exit code.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

show more ...